Updating varDsc home after spill and refactoring

BrianBohe · BrianBohe · commit 946090095d88 · 2023-01-11T22:31:27.000-08:00
diff --git a/src/coreclr/jit/codegenarm64.cpp b/src/coreclr/jit/codegenarm64.cpp
@@ -2928,7 +2928,6 @@ void CodeGen::genCodeForStoreLclVar(GenTreeLclVar* lclNode)
                 if (targetReg != REG_NA)
                 {
                     emit->emitIns_R_I(INS_movi, emitActualTypeSize(targetType), targetReg, 0x00, INS_OPTS_16B);
-                    genProduceReg(lclNode);
                 }
                 else
                 {
@@ -2941,8 +2940,8 @@ void CodeGen::genCodeForStoreLclVar(GenTreeLclVar* lclNode)
                         assert(targetType == TYP_SIMD8);
                         GetEmitter()->emitIns_S_R(INS_str, EA_8BYTE, REG_ZR, varNum, 0);
                     }
-                    genUpdateLife(lclNode);
                 }
+                genUpdateLifeStore(lclNode, targetReg, varDsc);
                 return;
             }
             if (zeroInit)

Original file line number	Diff line number	Diff line change
`@@ -2928,7 +2928,6 @@ void CodeGen::genCodeForStoreLclVar(GenTreeLclVar* lclNode)`
`2928`	`2928`	`if (targetReg != REG_NA)`
`2929`	`2929`	`{`
`2930`	`2930`	`emit->emitIns_R_I(INS_movi, emitActualTypeSize(targetType), targetReg, 0x00, INS_OPTS_16B);`
`2931`		`- genProduceReg(lclNode);`
`2932`	`2931`	`}`
`2933`	`2932`	`else`
`2934`	`2933`	`{`
`@@ -2941,8 +2940,8 @@ void CodeGen::genCodeForStoreLclVar(GenTreeLclVar* lclNode)`
`2941`	`2940`	`assert(targetType == TYP_SIMD8);`
`2942`	`2941`	`GetEmitter()->emitIns_S_R(INS_str, EA_8BYTE, REG_ZR, varNum, 0);`
`2943`	`2942`	`}`
`2944`		`- genUpdateLife(lclNode);`
`2945`	`2943`	`}`
	`2944`	`+ genUpdateLifeStore(lclNode, targetReg, varDsc);`
`2946`	`2945`	`return;`
`2947`	`2946`	`}`
`2948`	`2947`	`if (zeroInit)`