Consider instruction input size when considering embedded mask optimization

Some instructions, such as instructions `vinserti32x4`, `vinserti32x8`, and
`vinserti64x2`, have specific mask sizes assumed, which don't match the simd
base type size of the intrinsics which generate them. Check the
instruction "input size" and reject embedded mask optimization if it is
mismatched.

There are a few diffs in the HWINTRINSIC test cases, where this
optimization doesn't kick in anymore. The diffs look correct.

Fixes #114921

Author: BruceForstall

src/coreclr/jit/lowerxarch.cpp

@@ -10573,7 +10573,7 @@ void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node)
                                 //
                                 // The managed API surface we expose doesn't directly support TYP_MASK
                                 // and we don't directly expose overloads for APIs like `vaddps` which
-                                // support embedded masking. Instead, we have decide to do pattern
+                                // support embedded masking. Instead, we have decided to do pattern
                                 // recognition over the relevant ternary select APIs which functionally
                                 // execute `cond ? selectTrue : selectFalse` on a per element basis.
                                 //
@@ -10598,14 +10598,37 @@ void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node)
                                         // TODO-AVX512-CQ: Ensure we can support embedded operations on RMW intrinsics
                                         isEmbeddedMask = false;
                                     }
+                                    else
+                                    {
+                                        uint32_t  maskSize        = genTypeSize(simdBaseType);
+                                        var_types op2SimdBaseType = op2->AsHWIntrinsic()->GetSimdBaseType();
+                                        uint32_t  operSize        = genTypeSize(op2SimdBaseType);
+
+                                        if (maskSize != operSize)
+                                        {
+                                            isEmbeddedMask = false;
+                                        }
+                                        else
+                                        {
+                                            // Check the op2 instruction input size to see if it's the same as the
+                                            // mask size.
+
+                                            NamedIntrinsic op2IntrinsicId = op2->AsHWIntrinsic()->GetHWIntrinsicId();
+                                            instruction    ins =
+                                                HWIntrinsicInfo::lookupIns(op2IntrinsicId, op2SimdBaseType);
+                                            assert(ins != INS_invalid);
+                                            unsigned inputSize = CodeGenInterface::instInputSize(ins);
+                                            if (maskSize != inputSize)
+                                            {
+                                                isEmbeddedMask = false;
+                                            }
+                                        }
+                                    }
                                 }
 
                                 if (isEmbeddedMask)
                                 {
-                                    uint32_t maskSize = genTypeSize(simdBaseType);
-                                    uint32_t operSize = genTypeSize(op2->AsHWIntrinsic()->GetSimdBaseType());
-
-                                    if ((maskSize == operSize) && IsInvariantInRange(op2, node))
+                                    if (IsInvariantInRange(op2, node))
                                     {
                                         MakeSrcContained(node, op2);
                                         op2->MakeEmbMaskOp();

src/tests/JIT/Regression/JitBlue/Runtime_114921/Runtime_114921.cs

@@ -0,0 +1,83 @@
+// Licensed to the .NET Foundation under one or more agreements.
+// The .NET Foundation licenses this file to you under the MIT license.
+//
+// Generated by Fuzzlyn v2.5 on 2025-04-22 17:32:36
+// Run on X64 Windows
+// Seed: 7915602115310323123-vectort,vector128,vector256,vector512,x86aes,x86avx,x86avx2,x86avx512bw,x86avx512bwvl,x86avx512cd,x86avx512cdvl,x86avx512dq,x86avx512dqvl,x86avx512f,x86avx512fvl,x86avx512fx64,x86avx512vbmi,x86avx512vbmivl,x86bmi1,x86bmi1x64,x86bmi2,x86bmi2x64,x86fma,x86lzcnt,x86lzcntx64,x86pclmulqdq,x86popcnt,x86popcntx64,x86sse,x86ssex64,x86sse2,x86sse2x64,x86sse3,x86sse41,x86sse41x64,x86sse42,x86sse42x64,x86ssse3,x86x86base
+// Reduced from 123.1 KiB to 0.5 KiB in 00:00:46
+// Debug: Outputs <0, 0, 0, 0, 0, 0, 0, 0>
+// Release: Outputs <0, 0, 0, 0, -1, -1, -1, -1>
+
+using System;
+using System.Numerics;
+using System.Runtime.Intrinsics;
+using System.Runtime.Intrinsics.X86;
+using Xunit;
+
+public class Runtime_114921
+{
+    public static Vector512<long> s_4 = Vector512.Create<long>(-1);
+    public static Vector128<long> s_8;
+
+    [Fact]
+    public static void Problem1()
+    {
+        if (Avx512F.IsSupported)
+        {
+            var vr1 = Vector512.Create<long>(0);
+            s_4 = Avx512F.BlendVariable(s_4, Avx512F.InsertVector128(vr1, s_8, 0), s_4);
+            System.Console.WriteLine(s_4);
+            Assert.Equal(Vector512.Create(0L, 0L, 0L, 0L, 0L, 0L, 0L, 0L), s_4);
+        }
+    }
+}
+
+// Generated by Fuzzlyn v2.5 on 2025-04-22 17:37:13
+// Run on X64 Windows
+// Seed: 14731447107126414231-vectort,vector128,vector256,vector512,x86aes,x86avx,x86avx2,x86avx512bw,x86avx512bwvl,x86avx512cd,x86avx512cdvl,x86avx512dq,x86avx512dqvl,x86avx512f,x86avx512fvl,x86avx512fx64,x86avx512vbmi,x86avx512vbmivl,x86bmi1,x86bmi1x64,x86bmi2,x86bmi2x64,x86fma,x86lzcnt,x86lzcntx64,x86pclmulqdq,x86popcnt,x86popcntx64,x86sse,x86ssex64,x86sse2,x86sse2x64,x86sse3,x86sse41,x86sse41x64,x86sse42,x86sse42x64,x86ssse3,x86x86base
+// Reduced from 217.7 KiB to 1.0 KiB in 00:02:50
+// Debug: Outputs <9223372036854775807, 0, 0, 0, 0, 0, 0, 0>
+// Release: Outputs <4294967295, 0, 0, 0, 0, 0, 0, 0>
+
+public struct S2
+{
+    public Vector128<long> F0;
+    public S2(Vector128<long> f0) : this()
+    {
+        F0 = f0;
+    }
+}
+
+public class Runtime_114921_2
+{
+    public static IRuntime s_rt;
+
+    [Fact]
+    public static void Problem2()
+    {
+        if (Avx512F.IsSupported)
+        {
+            s_rt = new Runtime();
+            long vr6 = default(long);
+            S2 vr7 = new S2(Vector128.CreateScalar(9223372036854775807L));
+            Vector512<long> vr14 = default(Vector512<long>);
+            var vr9 = Vector512.Create<long>(vr6);
+            var vr10 = vr7.F0;
+            var vr11 = Avx512F.InsertVector128(vr9, vr10, 0);
+            var vr12 = Vector512.CreateScalar(-9223372036854775808L);
+            var vr13 = Avx512F.BlendVariable(vr14, vr11, vr12);
+            s_rt.WriteLine(vr13);
+            Assert.Equal(Vector512.Create(9223372036854775807L, 0L, 0L, 0L, 0L, 0L, 0L, 0L), vr13);
+        }
+    }
+}
+
+public interface IRuntime
+{
+    void WriteLine<T>(T value);
+}
+
+public class Runtime : IRuntime
+{
+    public void WriteLine<T>(T value) => System.Console.WriteLine(value);
+}

src/tests/JIT/Regression/JitBlue/Runtime_114921/Runtime_114921.csproj

@@ -0,0 +1,8 @@
+<Project Sdk="Microsoft.NET.Sdk">
+  <PropertyGroup>
+    <Optimize>True</Optimize>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="$(MSBuildProjectName).cs" />
+  </ItemGroup>
+</Project>