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operators() that operate on regNum
1 parent 2d1d2bb commit 7542417

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4 files changed

+35
-12
lines changed

4 files changed

+35
-12
lines changed

src/coreclr/jit/lsra.cpp

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4949,7 +4949,7 @@ void LinearScan::freeRegisters(regMaskTP regsToFree)
49494949
if (regRecord->assignedInterval != nullptr && (regRecord->assignedInterval->registerType == TYP_DOUBLE))
49504950
{
49514951
assert(genIsValidDoubleReg(nextReg));
4952-
regsToFree ^= genRegMask(regNumber(nextReg + 1));
4952+
regsToFree ^= regNumber(nextReg + 1);
49534953
}
49544954
#endif
49554955
freeRegister(regRecord);
@@ -9750,8 +9750,7 @@ void LinearScan::resolveEdge(BasicBlock* fromBlock,
97509750
while (targetCandidates.IsNonEmpty())
97519751
{
97529752
regNumber targetReg = genFirstRegNumFromMask(targetCandidates);
9753-
regMaskTP targetRegMask = genRegMask(targetReg);
9754-
targetCandidates ^= targetRegMask;
9753+
targetCandidates ^= targetReg;
97559754
if (location[targetReg] == REG_NA)
97569755
{
97579756
#ifdef TARGET_ARM
@@ -9764,13 +9763,13 @@ void LinearScan::resolveEdge(BasicBlock* fromBlock,
97649763
regNumber anotherHalfRegNum = REG_NEXT(targetReg);
97659764
if (location[anotherHalfRegNum] == REG_NA)
97669765
{
9767-
targetRegsReady |= targetRegMask;
9766+
targetRegsReady |= targetReg;
97689767
}
97699768
}
97709769
else
97719770
#endif // TARGET_ARM
97729771
{
9773-
targetRegsReady |= targetRegMask;
9772+
targetRegsReady |= targetReg;
97749773
}
97759774
}
97769775
}
@@ -9781,9 +9780,8 @@ void LinearScan::resolveEdge(BasicBlock* fromBlock,
97819780
while (targetRegsReady.IsNonEmpty())
97829781
{
97839782
regNumber targetReg = genFirstRegNumFromMask(targetRegsReady);
9784-
regMaskTP targetRegMask = genRegMask(targetReg);
9785-
targetRegsToDo ^= targetRegMask;
9786-
targetRegsReady ^= targetRegMask;
9783+
targetRegsToDo ^= targetReg;
9784+
targetRegsReady ^= targetReg;
97879785
assert(location[targetReg] != targetReg);
97889786
assert(targetReg < REG_COUNT);
97899787
regNumber sourceReg = (regNumber)source[targetReg];

src/coreclr/jit/lsrabuild.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2116,12 +2116,12 @@ void LinearScan::UpdateRegStateForStructArg(LclVarDsc* argDsc)
21162116
if ((genRegMask(argDsc->GetArgReg()) & RBM_ALLFLOAT) != RBM_NONE)
21172117
{
21182118
assert((genRegMask(argDsc->GetArgReg()) & RBM_FLTARG_REGS) != RBM_NONE);
2119-
floatRegState->rsCalleeRegArgMaskLiveIn |= genRegMask(argDsc->GetArgReg());
2119+
floatRegState->rsCalleeRegArgMaskLiveIn |= argDsc->GetArgReg();
21202120
}
21212121
else
21222122
{
21232123
assert((genRegMask(argDsc->GetArgReg()) & fullIntArgRegMask(compiler->info.compCallConv)) != RBM_NONE);
2124-
intRegState->rsCalleeRegArgMaskLiveIn |= genRegMask(argDsc->GetArgReg());
2124+
intRegState->rsCalleeRegArgMaskLiveIn |= argDsc->GetArgReg();
21252125
}
21262126
}
21272127

@@ -2130,12 +2130,12 @@ void LinearScan::UpdateRegStateForStructArg(LclVarDsc* argDsc)
21302130
if (genRegMask(argDsc->GetOtherArgReg()) & (RBM_ALLFLOAT))
21312131
{
21322132
assert(genRegMask(argDsc->GetOtherArgReg()) & (RBM_FLTARG_REGS));
2133-
floatRegState->rsCalleeRegArgMaskLiveIn |= genRegMask(argDsc->GetOtherArgReg());
2133+
floatRegState->rsCalleeRegArgMaskLiveIn |= argDsc->GetOtherArgReg();
21342134
}
21352135
else
21362136
{
21372137
assert((genRegMask(argDsc->GetOtherArgReg()) & fullIntArgRegMask(compiler->info.compCallConv)) != RBM_NONE);
2138-
intRegState->rsCalleeRegArgMaskLiveIn |= genRegMask(argDsc->GetOtherArgReg());
2138+
intRegState->rsCalleeRegArgMaskLiveIn |= argDsc->GetOtherArgReg();
21392139
}
21402140
}
21412141
}

src/coreclr/jit/regMaskTPOps.cpp

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -229,3 +229,25 @@ void regMaskTP::RemoveRegsetForType(SingleTypeRegSet regsToRemove, var_types typ
229229

230230
return _registerTypeIndex[reg];
231231
}
232+
233+
void regMaskTP::operator|=(const regNumber reg)
234+
{
235+
#ifdef HAS_MORE_THAN_64_REGISTERS
236+
int index = getRegisterTypeIndex(reg);
237+
RegBitSet64 value = genRegMask(reg);
238+
_registers[index] |= encodeForRegisterIndex(index, value);
239+
#else
240+
low |= genSingleTypeRegMask(reg);
241+
#endif
242+
}
243+
244+
void regMaskTP::operator^=(const regNumber reg)
245+
{
246+
#ifdef HAS_MORE_THAN_64_REGISTERS
247+
int index = getRegisterTypeIndex(reg);
248+
RegBitSet64 value = genRegMask(reg);
249+
_registers[index] ^= encodeForRegisterIndex(index, value);
250+
#else
251+
low ^= genSingleTypeRegMask(reg);
252+
#endif
253+
}

src/coreclr/jit/target.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -413,6 +413,9 @@ struct regMaskTP
413413
high &= second.getHigh();
414414
#endif
415415
}
416+
417+
void operator|=(const regNumber reg);
418+
void operator^=(const regNumber reg);
416419
};
417420

418421
static regMaskTP operator^(const regMaskTP& first, const regMaskTP& second)

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