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[wasm] Simd refactoring (#84170)
* [wasm] Simd refactoring Rename few opcodes to contain `_SIMD_`. Use more SimdIntrinsic fields to simplify the code. * Fix build * Fix narrowing intrinsics * Verbose aot compilation * Feedback * Make it verbose on helix * Do not set op for narrowing methods Because `emit_hardware_intrinsics` doesn't call custom emit in such case and so we endup with code emitted with wrong zero c0. * Feedback * Be quiet again :-)
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4 files changed

+80
-81
lines changed

4 files changed

+80
-81
lines changed

‎src/mono/mono/mini/mini-llvm.c‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -7671,30 +7671,30 @@ MONO_RESTORE_WARNING
76717671
break;
76727672
}
76737673
#if defined(TARGET_ARM64) || defined(TARGET_WASM)
7674-
case OP_FCVTL:
7675-
case OP_FCVTL2: {
7674+
case OP_SIMD_FCVTL:
7675+
case OP_SIMD_FCVTL2: {
76767676
LLVMTypeRef ret_t = simd_class_to_llvm_type (ctx, ins->klass);
7677-
gboolean high = ins->opcode == OP_FCVTL2;
7677+
gboolean high = ins->opcode == OP_SIMD_FCVTL2;
76787678
LLVMValueRef result = lhs;
76797679
if (high)
76807680
result = extract_high_elements (ctx, result);
76817681
result = LLVMBuildFPExt (builder, result, ret_t, "fcvtl");
76827682
values [ins->dreg] = result;
76837683
break;
76847684
}
7685-
case OP_SHL:
7686-
case OP_SSHR:
7687-
case OP_SSRA:
7688-
case OP_USHR:
7689-
case OP_USRA: {
7685+
case OP_SIMD_SHL:
7686+
case OP_SIMD_SSHR:
7687+
case OP_SIMD_SSRA:
7688+
case OP_SIMD_USHR:
7689+
case OP_SIMD_USRA: {
76907690
gboolean right = FALSE;
76917691
gboolean add = FALSE;
76927692
gboolean arith = FALSE;
76937693
switch (ins->opcode) {
7694-
case OP_USHR: right = TRUE; break;
7695-
case OP_USRA: right = TRUE; add = TRUE; break;
7696-
case OP_SSHR: arith = TRUE; break;
7697-
case OP_SSRA: arith = TRUE; add = TRUE; break;
7694+
case OP_SIMD_USHR: right = TRUE; break;
7695+
case OP_SIMD_USRA: right = TRUE; add = TRUE; break;
7696+
case OP_SIMD_SSHR: arith = TRUE; break;
7697+
case OP_SIMD_SSRA: arith = TRUE; add = TRUE; break;
76987698
}
76997699
LLVMValueRef shiftarg = lhs;
77007700
LLVMValueRef shift = rhs;
@@ -7715,16 +7715,16 @@ MONO_RESTORE_WARNING
77157715
values [ins->dreg] = result;
77167716
break;
77177717
}
7718-
case OP_SSHLL:
7719-
case OP_SSHLL2:
7720-
case OP_USHLL:
7721-
case OP_USHLL2: {
7718+
case OP_SIMD_SSHLL:
7719+
case OP_SIMD_SSHLL2:
7720+
case OP_SIMD_USHLL:
7721+
case OP_SIMD_USHLL2: {
77227722
LLVMTypeRef ret_t = simd_class_to_llvm_type (ctx, ins->klass);
77237723
gboolean high = FALSE;
77247724
gboolean is_unsigned = FALSE;
77257725
switch (ins->opcode) {
7726-
case OP_SSHLL2: high = TRUE; break;
7727-
case OP_USHLL2: high = TRUE; case OP_USHLL: is_unsigned = TRUE; break;
7726+
case OP_SIMD_SSHLL2: high = TRUE; break;
7727+
case OP_SIMD_USHLL2: high = TRUE; case OP_SIMD_USHLL: is_unsigned = TRUE; break;
77287728
}
77297729
LLVMValueRef result = lhs;
77307730
if (high)

‎src/mono/mono/mini/mini-ops.h‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1772,17 +1772,17 @@ MINI_OP3(OP_ARM64_TBX_INDIRECT, "arm64_tbx_indirect", XREG, IREG, XREG, XREG)
17721772

17731773
#endif // TARGET_ARM64
17741774

1775-
MINI_OP(OP_FCVTL, "convert_to_higher_precision", XREG, XREG, NONE)
1776-
MINI_OP(OP_FCVTL2, "convert_to_higher_precision_2", XREG, XREG, NONE)
1777-
MINI_OP(OP_USHLL, "unsigned_shift_left_long", XREG, XREG, IREG)
1778-
MINI_OP(OP_USHLL2, "unsigned_shift_left_long_2", XREG, XREG, IREG)
1779-
MINI_OP(OP_SSHLL, "signed_shift_left_long", XREG, XREG, IREG)
1780-
MINI_OP(OP_SSHLL2, "signed_shift_left_long_2", XREG, XREG, IREG)
1781-
MINI_OP(OP_SHL, "shl", XREG, XREG, IREG)
1782-
MINI_OP(OP_SSHR, "sshr", XREG, XREG, IREG)
1783-
MINI_OP(OP_USHR, "ushr", XREG, XREG, IREG)
1784-
MINI_OP3(OP_USRA, "usra", XREG, XREG, XREG, IREG)
1785-
MINI_OP3(OP_SSRA, "ssra", XREG, XREG, XREG, IREG)
1775+
MINI_OP(OP_SIMD_FCVTL, "simd_convert_to_higher_precision", XREG, XREG, NONE)
1776+
MINI_OP(OP_SIMD_FCVTL2, "simd_convert_to_higher_precision_2", XREG, XREG, NONE)
1777+
MINI_OP(OP_SIMD_USHLL, "simd_unsigned_shift_left_long", XREG, XREG, IREG)
1778+
MINI_OP(OP_SIMD_USHLL2, "simd_unsigned_shift_left_long_2", XREG, XREG, IREG)
1779+
MINI_OP(OP_SIMD_SSHLL, "simd_signed_shift_left_long", XREG, XREG, IREG)
1780+
MINI_OP(OP_SIMD_SSHLL2, "simd_signed_shift_left_long_2", XREG, XREG, IREG)
1781+
MINI_OP(OP_SIMD_SHL, "simd_shl", XREG, XREG, IREG)
1782+
MINI_OP(OP_SIMD_SSHR, "simd_sshr", XREG, XREG, IREG)
1783+
MINI_OP(OP_SIMD_USHR, "simd_ushr", XREG, XREG, IREG)
1784+
MINI_OP3(OP_SIMD_USRA, "simd_usra", XREG, XREG, XREG, IREG)
1785+
MINI_OP3(OP_SIMD_SSRA, "simd_ssra", XREG, XREG, XREG, IREG)
17861786

17871787
#if defined(TARGET_WASM)
17881788
MINI_OP(OP_WASM_ONESCOMPLEMENT, "wasm_onescomplement", XREG, XREG, NONE)

‎src/mono/mono/mini/simd-intrinsics.c‎

Lines changed: 50 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -1864,11 +1864,11 @@ emit_sri_vector (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsi
18641864
int op = id == SN_WidenLower ? OP_XLOWER : OP_XUPPER;
18651865
MonoInst *lower_or_upper_half = emit_simd_ins_for_sig (cfg, klass, op, 0, arg0_type, fsig, args);
18661866
if (type_enum_is_float (arg0_type)) {
1867-
return emit_simd_ins (cfg, klass, OP_FCVTL, lower_or_upper_half->dreg, -1);
1867+
return emit_simd_ins (cfg, klass, OP_SIMD_FCVTL, lower_or_upper_half->dreg, -1);
18681868
} else {
18691869
int zero = alloc_ireg (cfg);
18701870
MONO_EMIT_NEW_ICONST (cfg, zero, 0);
1871-
op = type_enum_is_unsigned (arg0_type) ? OP_USHLL : OP_SSHLL;
1871+
op = type_enum_is_unsigned (arg0_type) ? OP_SIMD_USHLL : OP_SIMD_SSHLL;
18721872
return emit_simd_ins (cfg, klass, op, lower_or_upper_half->dreg, zero);
18731873
}
18741874
#else
@@ -2932,9 +2932,9 @@ static SimdIntrinsic advsimd_methods [] = {
29322932
{SN_CompareLessThanScalar, OP_XCOMPARE_SCALAR, CMP_LT, OP_XCOMPARE_SCALAR, CMP_LT_UN, OP_XCOMPARE_FP_SCALAR, CMP_LT},
29332933
{SN_CompareTest, OP_ARM64_CMTST},
29342934
{SN_CompareTestScalar, OP_ARM64_CMTST},
2935-
{SN_ConvertToDouble, OP_CVT_SI_FP, None, OP_CVT_UI_FP, None, OP_FCVTL},
2935+
{SN_ConvertToDouble, OP_CVT_SI_FP, None, OP_CVT_UI_FP, None, OP_SIMD_FCVTL},
29362936
{SN_ConvertToDoubleScalar, OP_CVT_SI_FP_SCALAR, None, OP_CVT_UI_FP_SCALAR},
2937-
{SN_ConvertToDoubleUpper, OP_FCVTL2},
2937+
{SN_ConvertToDoubleUpper, OP_SIMD_FCVTL2},
29382938
{SN_ConvertToInt32RoundAwayFromZero, OP_XOP_OVR_X_X, INTRINS_AARCH64_ADV_SIMD_FCVTAS},
29392939
{SN_ConvertToInt32RoundAwayFromZeroScalar, OP_XOP_OVR_SCALAR_X_X, INTRINS_AARCH64_ADV_SIMD_FCVTAS},
29402940
{SN_ConvertToInt32RoundToEven, OP_XOP_OVR_X_X, INTRINS_AARCH64_ADV_SIMD_FCVTNS},
@@ -3166,14 +3166,14 @@ static SimdIntrinsic advsimd_methods [] = {
31663166
{SN_ShiftArithmeticScalar, OP_XOP_OVR_X_X_X, INTRINS_AARCH64_ADV_SIMD_SSHL},
31673167
{SN_ShiftLeftAndInsert, OP_ARM64_SLI},
31683168
{SN_ShiftLeftAndInsertScalar, OP_ARM64_SLI},
3169-
{SN_ShiftLeftLogical, OP_SHL},
3169+
{SN_ShiftLeftLogical, OP_SIMD_SHL},
31703170
{SN_ShiftLeftLogicalSaturate},
31713171
{SN_ShiftLeftLogicalSaturateScalar},
31723172
{SN_ShiftLeftLogicalSaturateUnsigned, OP_ARM64_SQSHLU},
31733173
{SN_ShiftLeftLogicalSaturateUnsignedScalar, OP_ARM64_SQSHLU_SCALAR},
3174-
{SN_ShiftLeftLogicalScalar, OP_SHL},
3175-
{SN_ShiftLeftLogicalWideningLower, OP_SSHLL, None, OP_USHLL},
3176-
{SN_ShiftLeftLogicalWideningUpper, OP_SSHLL2, None, OP_USHLL2},
3174+
{SN_ShiftLeftLogicalScalar, OP_SIMD_SHL},
3175+
{SN_ShiftLeftLogicalWideningLower, OP_SIMD_SSHLL, None, OP_SIMD_USHLL},
3176+
{SN_ShiftLeftLogicalWideningUpper, OP_SIMD_SSHLL2, None, OP_SIMD_USHLL2},
31773177
{SN_ShiftLogical, OP_XOP_OVR_X_X_X, INTRINS_AARCH64_ADV_SIMD_USHL},
31783178
{SN_ShiftLogicalRounded, OP_XOP_OVR_X_X_X, INTRINS_AARCH64_ADV_SIMD_URSHL},
31793179
{SN_ShiftLogicalRoundedSaturate, OP_XOP_OVR_X_X_X, INTRINS_AARCH64_ADV_SIMD_UQRSHL},
@@ -3184,9 +3184,9 @@ static SimdIntrinsic advsimd_methods [] = {
31843184
{SN_ShiftLogicalScalar, OP_XOP_OVR_X_X_X, INTRINS_AARCH64_ADV_SIMD_USHL},
31853185
{SN_ShiftRightAndInsert, OP_ARM64_SRI},
31863186
{SN_ShiftRightAndInsertScalar, OP_ARM64_SRI},
3187-
{SN_ShiftRightArithmetic, OP_SSHR},
3188-
{SN_ShiftRightArithmeticAdd, OP_SSRA},
3189-
{SN_ShiftRightArithmeticAddScalar, OP_SSRA},
3187+
{SN_ShiftRightArithmetic, OP_SIMD_SSHR},
3188+
{SN_ShiftRightArithmeticAdd, OP_SIMD_SSRA},
3189+
{SN_ShiftRightArithmeticAddScalar, OP_SIMD_SSRA},
31903190
{SN_ShiftRightArithmeticNarrowingSaturateLower, OP_ARM64_XNSHIFT, INTRINS_AARCH64_ADV_SIMD_SQSHRN},
31913191
{SN_ShiftRightArithmeticNarrowingSaturateScalar, OP_ARM64_XNSHIFT_SCALAR, INTRINS_AARCH64_ADV_SIMD_SQSHRN},
31923192
{SN_ShiftRightArithmeticNarrowingSaturateUnsignedLower, OP_ARM64_XNSHIFT, INTRINS_AARCH64_ADV_SIMD_SQSHRUN},
@@ -3203,10 +3203,10 @@ static SimdIntrinsic advsimd_methods [] = {
32033203
{SN_ShiftRightArithmeticRoundedNarrowingSaturateUnsignedUpper, OP_ARM64_XNSHIFT2, INTRINS_AARCH64_ADV_SIMD_SQRSHRUN},
32043204
{SN_ShiftRightArithmeticRoundedNarrowingSaturateUpper, OP_ARM64_XNSHIFT2, INTRINS_AARCH64_ADV_SIMD_SQRSHRN},
32053205
{SN_ShiftRightArithmeticRoundedScalar, OP_ARM64_SRSHR},
3206-
{SN_ShiftRightArithmeticScalar, OP_SSHR},
3207-
{SN_ShiftRightLogical, OP_USHR},
3208-
{SN_ShiftRightLogicalAdd, OP_USRA},
3209-
{SN_ShiftRightLogicalAddScalar, OP_USRA},
3206+
{SN_ShiftRightArithmeticScalar, OP_SIMD_SSHR},
3207+
{SN_ShiftRightLogical, OP_SIMD_USHR},
3208+
{SN_ShiftRightLogicalAdd, OP_SIMD_USRA},
3209+
{SN_ShiftRightLogicalAddScalar, OP_SIMD_USRA},
32103210
{SN_ShiftRightLogicalNarrowingLower, OP_ARM64_SHRN},
32113211
{SN_ShiftRightLogicalNarrowingSaturateLower, OP_ARM64_XNSHIFT, INTRINS_AARCH64_ADV_SIMD_UQSHRN},
32123212
{SN_ShiftRightLogicalNarrowingSaturateScalar, OP_ARM64_XNSHIFT_SCALAR, INTRINS_AARCH64_ADV_SIMD_UQSHRN},
@@ -3221,7 +3221,7 @@ static SimdIntrinsic advsimd_methods [] = {
32213221
{SN_ShiftRightLogicalRoundedNarrowingSaturateUpper, OP_ARM64_XNSHIFT2, INTRINS_AARCH64_ADV_SIMD_UQRSHRN},
32223222
{SN_ShiftRightLogicalRoundedNarrowingUpper, OP_ARM64_XNSHIFT2, INTRINS_AARCH64_ADV_SIMD_RSHRN},
32233223
{SN_ShiftRightLogicalRoundedScalar, OP_ARM64_URSHR},
3224-
{SN_ShiftRightLogicalScalar, OP_USHR},
3224+
{SN_ShiftRightLogicalScalar, OP_SIMD_USHR},
32253225
{SN_SignExtendWideningLower, OP_ARM64_SXTL},
32263226
{SN_SignExtendWideningUpper, OP_ARM64_SXTL2},
32273227
{SN_Sqrt, OP_XOP_OVR_X_X, INTRINS_AARCH64_ADV_SIMD_FSQRT},
@@ -4750,24 +4750,24 @@ static SimdIntrinsic wasmbase_methods [] = {
47504750

47514751
static SimdIntrinsic packedsimd_methods [] = {
47524752
{SN_Add},
4753-
{SN_And},
4754-
{SN_Bitmask},
4753+
{SN_And, OP_XBINOP_FORCEINT, XBINOP_FORCEINT_AND},
4754+
{SN_Bitmask, OP_WASM_SIMD_BITMASK},
47554755
{SN_CompareEqual},
47564756
{SN_CompareNotEqual},
47574757
{SN_ConvertNarrowingSignedSaturate},
47584758
{SN_ConvertNarrowingUnsignedSaturate},
4759-
{SN_Dot},
4759+
{SN_Dot, OP_XOP_X_X_X, INTRINS_WASM_DOT},
47604760
{SN_ExtractLane},
47614761
{SN_Multiply},
47624762
{SN_Negate},
47634763
{SN_ReplaceLane},
4764-
{SN_ShiftLeft},
4765-
{SN_ShiftRightArithmetic},
4766-
{SN_ShiftRightLogical},
4767-
{SN_Shuffle},
4764+
{SN_ShiftLeft, OP_SIMD_SHL},
4765+
{SN_ShiftRightArithmetic, OP_SIMD_SSHR},
4766+
{SN_ShiftRightLogical, OP_SIMD_USHR},
4767+
{SN_Shuffle, OP_WASM_SIMD_SHUFFLE},
47684768
{SN_Splat},
47694769
{SN_Subtract},
4770-
{SN_Swizzle},
4770+
{SN_Swizzle, OP_WASM_SIMD_SWIZZLE},
47714771
{SN_get_IsSupported},
47724772
};
47734773

@@ -4839,54 +4839,59 @@ emit_wasm_supported_intrinsics (
48394839
id == SN_Splat && !MONO_TYPE_IS_VECTOR_PRIMITIVE(fsig->params [0]))
48404840
return NULL;
48414841

4842+
uint16_t op = info->default_op;
4843+
uint16_t c0 = info->default_instc0;
4844+
48424845
switch (id) {
48434846
case SN_Add:
48444847
case SN_Subtract:
48454848
case SN_Multiply:
48464849
return emit_simd_ins_for_binary_op (cfg, klass, fsig, args, arg0_type, id);
48474850
case SN_Negate:
48484851
return emit_simd_ins_for_unary_op (cfg, klass, fsig, args, arg0_type, id);
4849-
case SN_And:
4850-
return emit_simd_ins_for_sig (cfg, klass, OP_XBINOP_FORCEINT, XBINOP_FORCEINT_AND, arg0_type, fsig, args);
4851-
case SN_Bitmask:
4852-
return emit_simd_ins_for_sig (cfg, klass, OP_WASM_SIMD_BITMASK, -1, -1, fsig, args);
48534852
case SN_CompareEqual:
48544853
return emit_simd_ins_for_sig (cfg, klass, type_enum_is_float (arg0_type) ? OP_XCOMPARE_FP : OP_XCOMPARE, CMP_EQ, arg0_type, fsig, args);
48554854
case SN_CompareNotEqual:
48564855
return emit_simd_ins_for_sig (cfg, klass, type_enum_is_float (arg0_type) ? OP_XCOMPARE_FP : OP_XCOMPARE, CMP_NE, arg0_type, fsig, args);
48574856
case SN_ConvertNarrowingSignedSaturate: {
4858-
int intrins = -1;
4857+
op = OP_XOP_X_X_X;
4858+
48594859
switch (arg0_type) {
48604860
case MONO_TYPE_I2:
4861-
intrins = INTRINS_WASM_NARROW_SIGNED_V16;
4861+
c0 = INTRINS_WASM_NARROW_SIGNED_V16;
48624862
break;
48634863
case MONO_TYPE_I4:
4864-
intrins = INTRINS_WASM_NARROW_SIGNED_V8;
4864+
c0 = INTRINS_WASM_NARROW_SIGNED_V8;
48654865
break;
48664866
}
4867-
if (intrins != -1)
4868-
return emit_simd_ins_for_sig (cfg, klass, OP_XOP_X_X_X, intrins, arg0_type, fsig, args);
4867+
4868+
// continue with default emit
4869+
if (c0 != 0)
4870+
break;
48694871

48704872
return NULL;
48714873
}
48724874
case SN_ConvertNarrowingUnsignedSaturate: {
4873-
int intrins = -1;
4875+
op = OP_XOP_X_X_X;
4876+
48744877
switch (arg0_type) {
48754878
case MONO_TYPE_I2:
4876-
intrins = INTRINS_WASM_NARROW_UNSIGNED_V16;
4879+
c0 = INTRINS_WASM_NARROW_UNSIGNED_V16;
48774880
break;
48784881
case MONO_TYPE_I4:
4879-
intrins = INTRINS_WASM_NARROW_UNSIGNED_V8;
4882+
c0 = INTRINS_WASM_NARROW_UNSIGNED_V8;
48804883
break;
48814884
}
4882-
if (intrins != -1)
4883-
return emit_simd_ins_for_sig (cfg, klass, OP_XOP_X_X_X, intrins, arg0_type, fsig, args);
4885+
4886+
// continue with default emit
4887+
if (c0 != 0)
4888+
break;
48844889

48854890
return NULL;
48864891
}
48874892
case SN_ExtractLane: {
4888-
int extract_op = type_to_xextract_op (arg0_type);
4889-
return emit_simd_ins_for_sig (cfg, klass, extract_op, -1, arg0_type, fsig, args);
4893+
op = type_to_xextract_op (arg0_type);
4894+
break;
48904895
}
48914896
case SN_ReplaceLane: {
48924897
int insert_op = type_to_xinsert_op (arg0_type);
@@ -4895,25 +4900,18 @@ emit_wasm_supported_intrinsics (
48954900
ins->inst_c1 = arg0_type;
48964901
return ins;
48974902
}
4898-
case SN_ShiftLeft:
4899-
return emit_simd_ins_for_sig (cfg, klass, OP_SHL, -1, -1, fsig, args);
4900-
case SN_ShiftRightArithmetic:
4901-
return emit_simd_ins_for_sig (cfg, klass, OP_SSHR, -1, -1, fsig, args);
4902-
case SN_ShiftRightLogical:
4903-
return emit_simd_ins_for_sig (cfg, klass, OP_USHR, -1, -1, fsig, args);
49044903
case SN_Splat: {
49054904
MonoType *etype = get_vector_t_elem_type (fsig->ret);
49064905
g_assert (fsig->param_count == 1 && mono_metadata_type_equal (fsig->params [0], etype));
49074906
return emit_simd_ins (cfg, klass, type_to_expand_op (etype->type), args [0]->dreg, -1);
49084907
}
4909-
case SN_Dot:
4910-
return emit_simd_ins_for_sig (cfg, klass, OP_XOP_X_X_X, INTRINS_WASM_DOT, -1, fsig, args);
4911-
case SN_Shuffle:
4912-
return emit_simd_ins_for_sig (cfg, klass, OP_WASM_SIMD_SHUFFLE, -1, -1, fsig, args);
4913-
case SN_Swizzle:
4914-
return emit_simd_ins_for_sig (cfg, klass, OP_WASM_SIMD_SWIZZLE, -1, -1, fsig, args);
49154908
}
4909+
4910+
// default emit path for cases with op set
4911+
if (op != 0)
4912+
return emit_simd_ins_for_sig (cfg, klass, op, c0, arg0_type, fsig, args);
49164913
}
4914+
49174915
g_assert_not_reached ();
49184916

49194917
return NULL;

‎src/mono/wasm/build/WasmApp.Native.targets‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -583,6 +583,7 @@
583583
<MonoAOTCompilerDefaultAotArguments Include="direct-icalls" />
584584
<MonoAOTCompilerDefaultAotArguments Include="deterministic" />
585585
<MonoAOTCompilerDefaultAotArguments Include="mattr=simd" Condition="'$(WasmEnableSIMD)' == 'true'" />
586+
<MonoAOTCompilerDefaultProcessArguments Include="-v" Condition="'$(WasmAOTCompilerVerbose)' == 'true'" />
586587
<MonoAOTCompilerDefaultProcessArguments Include="--wasm-exceptions" Condition="'$(WasmEnableExceptionHandling)' == 'true'" />
587588
<MonoAOTCompilerDefaultProcessArguments Include="--wasm-gc-safepoints" Condition="'$(WasmEnableThreads)' == 'true' or '$(WasmEnablePerfTracing)' == 'true'" />
588589
<AotProfilePath Include="$(WasmAotProfilePath)"/>

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