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Simplify platform macro definitions in PAL
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55 files changed

+230
-141
lines changed

‎src/coreclr/debug/daccess/riscv64/primitives.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
// Licensed to the .NET Foundation under one or more agreements.
2+
// The .NET Foundation licenses this file to you under the MIT license.
3+
4+
//
5+
6+
#include "stdafx.h"
7+
8+
#include "../../shared/riscv64/primitives.cpp"

‎src/coreclr/debug/ee/CMakeLists.txt

Lines changed: 4 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -47,22 +47,12 @@ set(CORDBEE_HEADERS_DAC
4747
${CORDBEE_HEADERS_DAC_AND_WKS}
4848
)
4949

50+
list(APPEND CORDBEE_SOURCES_WKS ${ARCH_SOURCES_DIR}/walker.cpp)
51+
5052
if(CLR_CMAKE_TARGET_ARCH_AMD64)
51-
list(APPEND CORDBEE_SOURCES_WKS
52-
${ARCH_SOURCES_DIR}/debuggerregdisplayhelper.cpp
53-
${ARCH_SOURCES_DIR}/amd64walker.cpp
54-
)
53+
list(APPEND CORDBEE_SOURCES_WKS ${ARCH_SOURCES_DIR}/debuggerregdisplayhelper.cpp)
5554
elseif(CLR_CMAKE_TARGET_ARCH_I386)
56-
list(APPEND CORDBEE_SOURCES_WKS
57-
${ARCH_SOURCES_DIR}/debuggerregdisplayhelper.cpp
58-
${ARCH_SOURCES_DIR}/x86walker.cpp
59-
)
60-
elseif(CLR_CMAKE_TARGET_ARCH_ARM)
61-
list(APPEND CORDBEE_SOURCES_WKS ${ARCH_SOURCES_DIR}/armwalker.cpp)
62-
elseif(CLR_CMAKE_TARGET_ARCH_ARM64)
63-
list(APPEND CORDBEE_SOURCES_WKS ${ARCH_SOURCES_DIR}/arm64walker.cpp)
64-
elseif(CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
65-
list(APPEND CORDBEE_SOURCES_WKS ${ARCH_SOURCES_DIR}/loongarch64walker.cpp)
55+
list(APPEND CORDBEE_SOURCES_WKS ${ARCH_SOURCES_DIR}/debuggerregdisplayhelper.cpp)
6656
endif()
6757

6858
convert_to_absolute_path(CORDBEE_SOURCES_DAC ${CORDBEE_SOURCES_DAC})

‎src/coreclr/debug/ee/amd64/amd64walker.cpp renamed to ‎src/coreclr/debug/ee/amd64/walker.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,7 @@
11
// Licensed to the .NET Foundation under one or more agreements.
22
// The .NET Foundation licenses this file to you under the MIT license.
3-
//*****************************************************************************
4-
// File: Amd64walker.cpp
5-
//
63

4+
//*****************************************************************************
75
//
86
// AMD64 instruction decoding/stepping logic
97
//

‎src/coreclr/debug/ee/arm/armwalker.cpp renamed to ‎src/coreclr/debug/ee/arm/walker.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,7 @@
11
// Licensed to the .NET Foundation under one or more agreements.
22
// The .NET Foundation licenses this file to you under the MIT license.
3-
//*****************************************************************************
4-
// File: armwalker.cpp
5-
//
63

4+
//*****************************************************************************
75
//
86
// ARM instruction decoding/stepping logic
97
//

‎src/coreclr/debug/ee/arm64/arm64walker.cpp renamed to ‎src/coreclr/debug/ee/arm64/walker.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,7 @@
11
// Licensed to the .NET Foundation under one or more agreements.
22
// The .NET Foundation licenses this file to you under the MIT license.
3-
//*****************************************************************************
4-
// File: Arm64walker.cpp
5-
//
63

4+
//*****************************************************************************
75
//
86
// ARM64 instruction decoding/stepping logic
97
//

‎src/coreclr/debug/ee/i386/x86walker.cpp renamed to ‎src/coreclr/debug/ee/i386/walker.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,7 @@
11
// Licensed to the .NET Foundation under one or more agreements.
22
// The .NET Foundation licenses this file to you under the MIT license.
3-
//*****************************************************************************
4-
// File: x86walker.cpp
5-
//
63

4+
//*****************************************************************************
75
//
86
// x86 instruction decoding/stepping logic
97
//

‎src/coreclr/debug/ee/loongarch64/loongarch64walker.cpp renamed to ‎src/coreclr/debug/ee/loongarch64/walker.cpp

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,6 @@
22
// The .NET Foundation licenses this file to you under the MIT license.
33

44
//*****************************************************************************
5-
// File: Loongarch64walker.cpp
6-
//
7-
85
//
96
// LOONGARCH64 instruction decoding/stepping logic
107
//

‎src/coreclr/unwinder/s390x/unwinder_s390x.cpp renamed to ‎src/coreclr/debug/ee/ppc64le/walker.cpp

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,4 @@
11
// Licensed to the .NET Foundation under one or more agreements.
22
// The .NET Foundation licenses this file to you under the MIT license.
33

4-
//
5-
6-
#include "stdafx.h"
7-
#include "utilcode.h"
8-
#include "crosscomp.h"
9-
104
#error Unsupported platform
11-

‎src/coreclr/debug/ee/riscv64/dbghelpers.S

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
// Licensed to the .NET Foundation under one or more agreements.
2+
// The .NET Foundation licenses this file to you under the MIT license.
3+
4+
#include "asmconstants.h"
5+
#include "unixasmmacros.inc"
6+
7+
#error "TODO-RISCV64: missing implementation"

‎src/coreclr/debug/ee/riscv64/primitives.cpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
// Licensed to the .NET Foundation under one or more agreements.
2+
// The .NET Foundation licenses this file to you under the MIT license.
3+
4+
//
5+
6+
#include "stdafx.h"
7+
#include "threads.h"
8+
#include "../../shared/riscv64/primitives.cpp"
9+
10+
#error "TODO-RISCV64: missing implementation"

‎src/coreclr/debug/ee/riscv64/walker.cpp

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
// Licensed to the .NET Foundation under one or more agreements.
2+
// The .NET Foundation licenses this file to you under the MIT license.
3+
4+
//*****************************************************************************
5+
//
6+
// RISCV64 instruction decoding/stepping logic
7+
//
8+
//*****************************************************************************
9+
10+
#include "stdafx.h"
11+
#include "walker.h"
12+
#include "frames.h"
13+
#include "openum.h"
14+
15+
#ifdef TARGET_RISCV64
16+
17+
#error "TODO-RISCV64: missing implementation"
18+
19+
#endif

‎src/coreclr/debug/ee/s390x/walker.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
// Licensed to the .NET Foundation under one or more agreements.
2+
// The .NET Foundation licenses this file to you under the MIT license.
3+
4+
#error Unsupported platform

‎src/coreclr/debug/shared/riscv64/primitives.cpp

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
// Licensed to the .NET Foundation under one or more agreements.
2+
// The .NET Foundation licenses this file to you under the MIT license.
3+
4+
//*****************************************************************************
5+
// File: primitives.cpp
6+
//
7+
8+
//
9+
// Platform-specific debugger primitives
10+
//
11+
//*****************************************************************************
12+
13+
#include "primitives.h"
14+
15+
#error "TODO-RISCV64: missing implementation"

‎src/coreclr/gc/env/gcenv.interlocked.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ class Interlocked
1212
private:
1313

1414
#ifndef _MSC_VER
15-
static void ArmInterlockedOperationBarrier();
15+
static void InterlockedOperationBarrier();
1616
#endif // !_MSC_VER
1717

1818
public:

‎src/coreclr/gc/env/gcenv.interlocked.inl

Lines changed: 17 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -11,15 +11,12 @@
1111
#endif // _MSC_VER
1212

1313
#ifndef _MSC_VER
14-
__forceinline void Interlocked::ArmInterlockedOperationBarrier()
14+
__forceinline void Interlocked::InterlockedOperationBarrier()
1515
{
16-
#ifdef HOST_ARM64
17-
// See PAL_ArmInterlockedOperationBarrier() in the PAL
16+
#if defined(HOST_ARM64) || defined(HOST_LOONGARCH64)
17+
// See PAL_InterlockedOperationBarrier() in the PAL
1818
__sync_synchronize();
19-
#endif // HOST_ARM64
20-
#ifdef HOST_LOONGARCH64
21-
__sync_synchronize();
22-
#endif //HOST_LOONGARCH64
19+
#endif
2320
}
2421
#endif // !_MSC_VER
2522

@@ -36,7 +33,7 @@ __forceinline T Interlocked::Increment(T volatile *addend)
3633
return _InterlockedIncrement((long*)addend);
3734
#else
3835
T result = __sync_add_and_fetch(addend, 1);
39-
ArmInterlockedOperationBarrier();
36+
InterlockedOperationBarrier();
4037
return result;
4138
#endif
4239
}
@@ -54,7 +51,7 @@ __forceinline T Interlocked::Decrement(T volatile *addend)
5451
return _InterlockedDecrement((long*)addend);
5552
#else
5653
T result = __sync_sub_and_fetch(addend, 1);
57-
ArmInterlockedOperationBarrier();
54+
InterlockedOperationBarrier();
5855
return result;
5956
#endif
6057
}
@@ -73,7 +70,7 @@ __forceinline T Interlocked::Exchange(T volatile *destination, T value)
7370
return _InterlockedExchange((long*)destination, value);
7471
#else
7572
T result = __atomic_exchange_n(destination, value, __ATOMIC_ACQ_REL);
76-
ArmInterlockedOperationBarrier();
73+
InterlockedOperationBarrier();
7774
return result;
7875
#endif
7976
}
@@ -94,7 +91,7 @@ __forceinline T Interlocked::CompareExchange(T volatile *destination, T exchange
9491
return _InterlockedCompareExchange((long*)destination, exchange, comparand);
9592
#else
9693
T result = __sync_val_compare_and_swap(destination, comparand, exchange);
97-
ArmInterlockedOperationBarrier();
94+
InterlockedOperationBarrier();
9895
return result;
9996
#endif
10097
}
@@ -113,7 +110,7 @@ __forceinline T Interlocked::ExchangeAdd(T volatile *addend, T value)
113110
return _InterlockedExchangeAdd((long*)addend, value);
114111
#else
115112
T result = __sync_fetch_and_add(addend, value);
116-
ArmInterlockedOperationBarrier();
113+
InterlockedOperationBarrier();
117114
return result;
118115
#endif
119116
}
@@ -126,7 +123,7 @@ __forceinline T Interlocked::ExchangeAdd64(T volatile* addend, T value)
126123
return _InterlockedExchangeAdd64((int64_t*)addend, value);
127124
#else
128125
T result = __sync_fetch_and_add(addend, value);
129-
ArmInterlockedOperationBarrier();
126+
InterlockedOperationBarrier();
130127
return result;
131128
#endif
132129
}
@@ -144,7 +141,7 @@ __forceinline T Interlocked::ExchangeAddPtr(T volatile* addend, T value)
144141
#endif
145142
#else
146143
T result = __sync_fetch_and_add(addend, value);
147-
ArmInterlockedOperationBarrier();
144+
InterlockedOperationBarrier();
148145
return result;
149146
#endif
150147
}
@@ -161,7 +158,7 @@ __forceinline void Interlocked::And(T volatile *destination, T value)
161158
_InterlockedAnd((long*)destination, value);
162159
#else
163160
__sync_and_and_fetch(destination, value);
164-
ArmInterlockedOperationBarrier();
161+
InterlockedOperationBarrier();
165162
#endif
166163
}
167164

@@ -177,7 +174,7 @@ __forceinline void Interlocked::Or(T volatile *destination, T value)
177174
_InterlockedOr((long*)destination, value);
178175
#else
179176
__sync_or_and_fetch(destination, value);
180-
ArmInterlockedOperationBarrier();
177+
InterlockedOperationBarrier();
181178
#endif
182179
}
183180

@@ -198,7 +195,7 @@ __forceinline T Interlocked::ExchangePointer(T volatile * destination, T value)
198195
#endif
199196
#else
200197
T result = (T)(TADDR)__atomic_exchange_n((void* volatile *)destination, value, __ATOMIC_ACQ_REL);
201-
ArmInterlockedOperationBarrier();
198+
InterlockedOperationBarrier();
202199
return result;
203200
#endif
204201
}
@@ -214,7 +211,7 @@ __forceinline T Interlocked::ExchangePointer(T volatile * destination, std::null
214211
#endif
215212
#else
216213
T result = (T)(TADDR)__atomic_exchange_n((void* volatile *)destination, value, __ATOMIC_ACQ_REL);
217-
ArmInterlockedOperationBarrier();
214+
InterlockedOperationBarrier();
218215
return result;
219216
#endif
220217
}
@@ -238,7 +235,7 @@ __forceinline T Interlocked::CompareExchangePointer(T volatile *destination, T e
238235
#endif
239236
#else
240237
T result = (T)(TADDR)__sync_val_compare_and_swap((void* volatile *)destination, comparand, exchange);
241-
ArmInterlockedOperationBarrier();
238+
InterlockedOperationBarrier();
242239
return result;
243240
#endif
244241
}
@@ -254,7 +251,7 @@ __forceinline T Interlocked::CompareExchangePointer(T volatile *destination, T e
254251
#endif
255252
#else
256253
T result = (T)(TADDR)__sync_val_compare_and_swap((void* volatile *)destination, (void*)comparand, (void*)exchange);
257-
ArmInterlockedOperationBarrier();
254+
InterlockedOperationBarrier();
258255
return result;
259256
#endif
260257
}

‎src/coreclr/jit/hashbv.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
#ifndef HASHBV_H
55
#define HASHBV_H
66

7-
#if defined(_M_AMD64) || defined(_M_X86)
7+
#if defined(HOST_AMD64) || defined(HOST_X86)
88
#include <xmmintrin.h>
99
#endif
1010

‎src/coreclr/nativeaot/Runtime/arm64/AsmMacros.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -249,7 +249,7 @@ __SECTIONREL_tls_CurrentThread SETS "$__SECTIONREL_tls_CurrentThread":CC:"_"
249249
;;
250250

251251
MACRO
252-
ArmInterlockedOperationBarrier
252+
InterlockedOperationBarrier
253253

254254
dmb ish
255255
MEND

‎src/coreclr/nativeaot/Runtime/arm64/Interlocked.S

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ ALTERNATE_ENTRY RhpLockCmpXchg32AVLocation
2020
cbnz w9, 1b
2121

2222
2: // exit
23-
ArmInterlockedOperationBarrier
23+
InterlockedOperationBarrier
2424
ret
2525
LEAF_END RhpLockCmpXchg32, _TEXT
2626

@@ -40,6 +40,6 @@ ALTERNATE_ENTRY RhpLockCmpXchg64AVLocation
4040
stlxr w9, x1, [x8] // if (x0 == x2) { try *x8 = x1 and goto loop if failed or goto exit }
4141
cbnz w9, 1b
4242
2: // exit
43-
ArmInterlockedOperationBarrier
43+
InterlockedOperationBarrier
4444
ret
4545
LEAF_END RhpLockCmpXchg64, _TEXT

‎src/coreclr/nativeaot/Runtime/arm64/Interlocked.asm

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@
2222
cbnz w9, %bt1
2323

2424
2 ;; exit
25-
ArmInterlockedOperationBarrier
25+
InterlockedOperationBarrier
2626
ret
2727
LEAF_END RhpLockCmpXchg32
2828

@@ -43,7 +43,7 @@
4343
cbnz w9, %bt1
4444

4545
2 ;; exit
46-
ArmInterlockedOperationBarrier
46+
InterlockedOperationBarrier
4747
ret
4848
LEAF_END RhpLockCmpXchg64
4949

‎src/coreclr/nativeaot/Runtime/arm64/WriteBarriers.S

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -268,7 +268,7 @@ CmpXchgRetry:
268268
CmpXchgNoUpdate:
269269
// x10 still contains the original value.
270270
mov x0, x10
271-
ArmInterlockedOperationBarrier
271+
InterlockedOperationBarrier
272272
ret lr
273273

274274
LEAF_END RhpCheckedLockCmpXchg, _TEXT
@@ -309,7 +309,7 @@ ExchangeRetry:
309309

310310
// x10 still contains the original value.
311311
mov x0, x10
312-
ArmInterlockedOperationBarrier
312+
InterlockedOperationBarrier
313313
ret
314314

315315
LEAF_END RhpCheckedXchg, _TEXT

‎src/coreclr/nativeaot/Runtime/arm64/WriteBarriers.asm

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -275,7 +275,7 @@ CmpXchgRetry
275275
CmpXchgNoUpdate
276276
;; x10 still contains the original value.
277277
mov x0, x10
278-
ArmInterlockedOperationBarrier
278+
InterlockedOperationBarrier
279279
ret lr
280280

281281
LEAF_END RhpCheckedLockCmpXchg
@@ -318,7 +318,7 @@ ExchangeRetry
318318

319319
;; x10 still contains the original value.
320320
mov x0, x10
321-
ArmInterlockedOperationBarrier
321+
InterlockedOperationBarrier
322322
ret
323323

324324
LEAF_END RhpCheckedXchg

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