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ARM64-SVE: Saturating*ByActiveElementCount (#102994)
* ARM64-SVE: Saturating*ByActiveElementCount * formatting * Missing bracket
1 parent 990003d commit 08056f9

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10 files changed

+1401
-3
lines changed

10 files changed

+1401
-3
lines changed

‎src/coreclr/jit/hwintrinsicarm64.cpp

Lines changed: 30 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2620,8 +2620,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
26202620
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
26212621
op1 = impPopStack().val;
26222622

2623-
CorInfoType op1BaseJitType = getBaseJitTypeOfSIMDType(argClass);
2624-
26252623
assert(HWIntrinsicInfo::isImmOp(intrinsic, op2));
26262624
HWIntrinsicInfo::lookupImmBounds(intrinsic, simdSize, simdBaseType, 1, &immLowerBound, &immUpperBound);
26272625
op2 = addRangeCheckIfNeeded(intrinsic, op2, (!op2->IsCnsIntOrI()), immLowerBound, immUpperBound);
@@ -2637,6 +2635,36 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
26372635
break;
26382636
}
26392637

2638+
case NI_Sve_SaturatingDecrementByActiveElementCount:
2639+
case NI_Sve_SaturatingIncrementByActiveElementCount:
2640+
{
2641+
assert(sig->numArgs == 2);
2642+
2643+
CORINFO_ARG_LIST_HANDLE arg1 = sig->args;
2644+
CORINFO_ARG_LIST_HANDLE arg2 = info.compCompHnd->getArgNext(arg1);
2645+
var_types argType = TYP_UNKNOWN;
2646+
CORINFO_CLASS_HANDLE argClass = NO_CLASS_HANDLE;
2647+
2648+
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
2649+
op2 = getArgForHWIntrinsic(argType, argClass);
2650+
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
2651+
op1 = impPopStack().val;
2652+
2653+
CorInfoType op1BaseJitType = getBaseJitTypeOfSIMDType(argClass);
2654+
2655+
// HWInstrinsic requires a mask for op2
2656+
if (!varTypeIsMask(op2))
2657+
{
2658+
op2 = gtNewSimdConvertVectorToMaskNode(retType, op2, simdBaseJitType, simdSize);
2659+
}
2660+
2661+
retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, intrinsic, simdBaseJitType, simdSize);
2662+
2663+
retNode->AsHWIntrinsic()->SetSimdBaseJitType(simdBaseJitType);
2664+
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(op1BaseJitType);
2665+
break;
2666+
}
2667+
26402668
default:
26412669
{
26422670
return nullptr;

‎src/coreclr/jit/hwintrinsiccodegenarm64.cpp

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1940,6 +1940,33 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
19401940
break;
19411941
}
19421942

1943+
case NI_Sve_SaturatingDecrementByActiveElementCount:
1944+
case NI_Sve_SaturatingIncrementByActiveElementCount:
1945+
{
1946+
// RMW semantics
1947+
if (targetReg != op1Reg)
1948+
{
1949+
assert(targetReg != op2Reg);
1950+
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
1951+
}
1952+
1953+
// Switch instruction if arg1 is unsigned.
1954+
if (varTypeIsUnsigned(node->GetAuxiliaryType()))
1955+
{
1956+
ins =
1957+
(intrin.id == NI_Sve_SaturatingDecrementByActiveElementCount) ? INS_sve_uqdecp : INS_sve_uqincp;
1958+
}
1959+
1960+
// If this is the scalar variant, get the correct size.
1961+
if (!varTypeIsSIMD(node->gtType))
1962+
{
1963+
emitSize = emitActualTypeSize(intrin.op1);
1964+
}
1965+
1966+
GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op2Reg, opt);
1967+
break;
1968+
}
1969+
19431970
default:
19441971
unreached();
19451972
}

‎src/coreclr/jit/hwintrinsiclistarm64sve.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -149,10 +149,12 @@ HARDWARE_INTRINSIC(Sve, SaturatingDecrementBy16BitElementCount,
149149
HARDWARE_INTRINSIC(Sve, SaturatingDecrementBy32BitElementCount, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_sqdecw, INS_sve_uqdecw, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_HasEnumOperand|HW_Flag_SpecialCodeGen|HW_Flag_HasScalarInputVariant|HW_Flag_SpecialImport|HW_Flag_HasRMWSemantics)
150150
HARDWARE_INTRINSIC(Sve, SaturatingDecrementBy64BitElementCount, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_sqdecd, INS_sve_uqdecd, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_HasEnumOperand|HW_Flag_SpecialCodeGen|HW_Flag_HasScalarInputVariant|HW_Flag_SpecialImport|HW_Flag_HasRMWSemantics)
151151
HARDWARE_INTRINSIC(Sve, SaturatingDecrementBy8BitElementCount, 0, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_sqdecb, INS_sve_uqdecb, INS_sve_sqdecb, INS_sve_uqdecb, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_HasEnumOperand|HW_Flag_SpecialCodeGen|HW_Flag_SpecialImport|HW_Flag_HasRMWSemantics)
152+
HARDWARE_INTRINSIC(Sve, SaturatingDecrementByActiveElementCount, -1, 2, true, {INS_invalid, INS_sve_sqdecp, INS_sve_sqdecp, INS_sve_sqdecp, INS_sve_sqdecp, INS_sve_sqdecp, INS_sve_sqdecp, INS_sve_sqdecp, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_SpecialImport|HW_Flag_BaseTypeFromSecondArg|HW_Flag_HasRMWSemantics)
152153
HARDWARE_INTRINSIC(Sve, SaturatingIncrementBy16BitElementCount, -1, 3, true, {INS_invalid, INS_invalid, INS_sve_sqinch, INS_sve_uqinch, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_HasEnumOperand|HW_Flag_SpecialCodeGen|HW_Flag_HasScalarInputVariant|HW_Flag_SpecialImport|HW_Flag_HasRMWSemantics)
153154
HARDWARE_INTRINSIC(Sve, SaturatingIncrementBy32BitElementCount, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_sqincw, INS_sve_uqincw, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_HasEnumOperand|HW_Flag_SpecialCodeGen|HW_Flag_HasScalarInputVariant|HW_Flag_SpecialImport|HW_Flag_HasRMWSemantics)
154155
HARDWARE_INTRINSIC(Sve, SaturatingIncrementBy64BitElementCount, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_sqincd, INS_sve_uqincd, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_HasEnumOperand|HW_Flag_SpecialCodeGen|HW_Flag_HasScalarInputVariant|HW_Flag_SpecialImport|HW_Flag_HasRMWSemantics)
155156
HARDWARE_INTRINSIC(Sve, SaturatingIncrementBy8BitElementCount, 0, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_sqincb, INS_sve_uqincb, INS_sve_sqincb, INS_sve_uqincb, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_HasEnumOperand|HW_Flag_SpecialCodeGen|HW_Flag_SpecialImport|HW_Flag_HasRMWSemantics)
157+
HARDWARE_INTRINSIC(Sve, SaturatingIncrementByActiveElementCount, -1, 2, true, {INS_invalid, INS_sve_sqincp, INS_sve_sqincp, INS_sve_sqincp, INS_sve_sqincp, INS_sve_sqincp, INS_sve_sqincp, INS_sve_sqincp, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_SpecialImport|HW_Flag_BaseTypeFromSecondArg|HW_Flag_HasRMWSemantics)
156158
HARDWARE_INTRINSIC(Sve, SignExtend16, -1, -1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_sxth, INS_invalid, INS_sve_sxth, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation)
157159
HARDWARE_INTRINSIC(Sve, SignExtend32, -1, -1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_sxtw, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation)
158160
HARDWARE_INTRINSIC(Sve, SignExtend8, -1, -1, false, {INS_invalid, INS_invalid, INS_sve_sxtb, INS_invalid, INS_sve_sxtb, INS_invalid, INS_sve_sxtb, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation)

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