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dineshannayyadineshannayya
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semaphore + pinmux reg realignement + multi-core bug fix in riscv core
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‎Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -151,7 +151,7 @@ run-precheck: check-pdk check-precheck
151151
$(eval INPUT_DIRECTORY := $(shell pwd))
152152
cd $(PRECHECK_ROOT) && \
153153
docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) \
154-
-u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_root $(PDK_ROOT)"
154+
-u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_path $(PDK_ROOT)"
155155

156156

157157

‎README.md

Lines changed: 38 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -86,6 +86,9 @@ Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arduino pla
8686
<tr>
8787
<td align="center"><img src="./docs/source/_static/Riscduino-derivatives.png" ></td>
8888
</tr>
89+
<tr>
90+
<td align="center"><img src="./docs/source/_static/Riscduino_Series_placement.png" ></td>
91+
</tr>
8992

9093
</table>
9194

@@ -127,27 +130,51 @@ Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arduino pla
127130
<tr>
128131
<td align="center"> MPW-5 </td>
129132
<td align="center"> 21-Mar-2022 </td>
130-
<td align="center"> Riscduino-SCORE</td>
133+
<td align="center"> Riscduino-SCORE (S0)</td>
131134
<td align="center"> Single 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar</td>
132135
<td align="center"> <a href="https://github.com/dineshannayya/riscduino">Link</a></td>
133136
<td align="center"> <a href="https://platform.efabless.com/projects/670">Link</a></td>
134137
</tr>
135138
<tr>
136139
<td align="center"> MPW-5 </td>
137140
<td align="center"> 21-Mar-2022 </td>
138-
<td align="center"> Riscduino-DCORE</td>
141+
<td align="center"> Riscduino-DCORE (D0)</td>
139142
<td align="center"> Dual 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar</td>
140143
<td align="center"> <a href="https://github.com/dineshannayya/riscduino_dcore">Link</a></td>
141144
<td align="center"> <a href="https://platform.efabless.com/projects/718">Link</a></td>
142145
</tr>
143146
<tr>
144147
<td align="center"> MPW-5 </td>
145148
<td align="center"> 21-Mar-2022 </td>
146-
<td align="center"> Riscduino-QCORE</td>
149+
<td align="center"> Riscduino-QCORE (Q0)</td>
147150
<td align="center"> Quad 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar</td>
148151
<td align="center"> <a href="https://github.com/dineshannayya/riscduino_qcore">Link</a></td>
149152
<td align="center"> <a href="https://platform.efabless.com/projects/782">Link</a></td>
150153
</tr>
154+
<tr>
155+
<td align="center"> MPW-6 </td>
156+
<td align="center"> 07-June-2022 </td>
157+
<td align="center"> Riscduino-SCORE (S3)</td>
158+
<td align="center"> Single 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar</td>
159+
<td align="center"> <a href="https://github.com/dineshannayya/riscduino">Link</a></td>
160+
<td align="center"> <a href="https://platform.efabless.com/projects/1047">Link</a></td>
161+
</tr>
162+
<tr>
163+
<td align="center"> MPW-6 </td>
164+
<td align="center"> 07-June-2022 </td>
165+
<td align="center"> Riscduino-DCORE (D1)</td>
166+
<td align="center"> Dual 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar</td>
167+
<td align="center"> <a href="https://github.com/dineshannayya/riscduino_dcore">Link</a></td>
168+
<td align="center"> <a href="https://platform.efabless.com/projects/838">Link</a></td>
169+
</tr>
170+
<tr>
171+
<td align="center"> MPW-6 </td>
172+
<td align="center"> 07-June-2022 </td>
173+
<td align="center"> Riscduino-QCORE (Q1)</td>
174+
<td align="center"> Quad 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar</td>
175+
<td align="center"> <a href="https://github.com/dineshannayya/riscduino_qcore">Link</a></td>
176+
<td align="center"> <a href="https://platform.efabless.com/projects/839">Link</a></td>
177+
</tr>
151178
</table>
152179

153180
# SOC Pin Mapping
@@ -639,6 +666,14 @@ Examples:
639666
make verify-riscv_regress - standalone riscv compliance test suite
640667
make verify-arduino_risc_boot - standalone riscv core-0 boot using arduino tool set
641668
make verify-arduino_hello_world - standalone riscv core-0 hello world test using arduino tool set
669+
make verify-arduino_digital_port_control - standalone riscv core-0 digital port control using arduino tool set
670+
make verify-arduino_ascii_table - standalone riscv core-0 ascii table using arduino tool set
671+
make verify-arduino_character_analysis - standalone riscv core-0 character analysis using arduino tool set
672+
make verify-arduino_multi_serial - standalone riscv core-0 multi uart test using arduino tool set
673+
make verify-arduino_switchCase2 - standalone riscv core-0 switch case using arduino tool set
674+
make verify-arduino_risc_boot - standalone riscv core-0 boot test using arduino tool set
675+
make verify-arduino_string - standalone riscv core-0 string usage test using arduino tool set
676+
642677
make verify-user_mcore - standalone riscv multi-core test
643678
make verify-user_sram_exec RISC_CORE=1 - standalone riscv core-1 test with executing code from data memory
644679
make verify-user_sram_exec RISC_CORE=2 - standalone riscv core-2 test with executing code from data memory

‎openlane/Makefile

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ endif
4343
@sleep 1
4444

4545
@if [ -f ./$*/interactive.tcl ]; then\
46-
docker run --rm -v $(OPENLANE_ROOT):/openlane \
46+
docker run --rm \
4747
-v $(PDK_ROOT):$(PDK_ROOT) \
4848
-v $(PWD)/..:$(PWD)/.. \
4949
-v $(MCW_ROOT):$(MCW_ROOT) \
@@ -57,7 +57,7 @@ endif
5757
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
5858
$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
5959
else\
60-
docker run --rm -v $(OPENLANE_ROOT):/openlane \
60+
docker run --rm \
6161
-v $(PDK_ROOT):$(PDK_ROOT) \
6262
-v $(PWD)/..:$(PWD)/.. \
6363
-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \

‎openlane/pinmux_top/base.sdc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ create_clock -name mclk -period 10.0000 [get_ports {mclk}]
1010
set_propagated_clock [get_clocks {mclk}]
1111

1212
set_clock_transition 0.1500 [all_clocks]
13-
set_clock_uncertainty -setup 0.2500 [all_clocks]
13+
set_clock_uncertainty -setup 0.5000 [all_clocks]
1414
set_clock_uncertainty -hold 0.2500 [all_clocks]
1515

1616
set ::env(SYNTH_TIMING_DERATE) 0.05

‎openlane/pinmux_top/config.tcl

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@
2020
set script_dir [file dirname [file normalize [info script]]]
2121
# Name
2222

23-
set ::env(DESIGN_NAME) pinmux
23+
set ::env(DESIGN_NAME) pinmux_top
2424

2525
set ::env(DESIGN_IS_CORE) "0"
2626
set ::env(FP_PDN_CORE_RING) "0"
@@ -42,11 +42,19 @@ set ::env(CLOCK_BUFFER_FANOUT) "8"
4242
# Local sources + no2usb sources
4343
set ::env(VERILOG_FILES) "\
4444
$::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
45+
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux_top.sv \
4546
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux.sv \
46-
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux_reg.sv \
47-
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/gpio_intr.sv \
48-
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pwm.sv \
49-
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/timer.sv \
47+
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/glbl_reg.sv \
48+
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/gpio_top.sv \
49+
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/gpio_reg.sv \
50+
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/gpio_intr.sv \
51+
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pwm_top.sv \
52+
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pwm_reg.sv \
53+
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pwm.sv \
54+
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/timer_top.sv \
55+
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/timer_reg.sv \
56+
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/timer.sv \
57+
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/semaphore_reg.sv \
5058
$::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type1.sv \
5159
$::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type2.sv \
5260
$::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \
@@ -82,7 +90,7 @@ set ::env(RUN_CVC) 0
8290

8391

8492
set ::env(PL_TIME_DRIVEN) 1
85-
set ::env(PL_TARGET_DENSITY) "0.38"
93+
set ::env(PL_TARGET_DENSITY) "0.40"
8694
set ::env(CELL_PAD) "4"
8795

8896
set ::env(FP_IO_VEXTEND) {6}

‎openlane/pinmux_top/pin_order.cfg

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -131,6 +131,7 @@ mclk
131131

132132
reg_cs 200 0
133133
reg_wr
134+
reg_addr\[8\]
134135
reg_addr\[7\]
135136
reg_addr\[6\]
136137
reg_addr\[5\]

‎openlane/uart_i2cm_usb_spi_top/base.sdc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@ set_input_delay -min 1.5000 -clock [get_clocks {app_clk}] -add_delay [get_ports
4646

4747
set_input_delay -max 5.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_addr[*]}]
4848
set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_be[*]}]
49-
set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_cs}]
49+
set_input_delay -max 5.7500 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_cs}]
5050
set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_wdata[*]}]
5151
set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_wr}]
5252

‎openlane/uart_i2cm_usb_spi_top/config.tcl

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,7 @@ set ::env(VERILOG_FILES) "\
6868
$::env(DESIGN_DIR)/../../verilog/rtl/sspim/src/sspim_ctl.sv \
6969
$::env(DESIGN_DIR)/../../verilog/rtl/sspim/src/sspim_if.sv \
7070
$::env(DESIGN_DIR)/../../verilog/rtl/sspim/src/sspim_cfg.sv \
71+
$::env(DESIGN_DIR)/../../verilog/rtl/sspim/src/sspim_clkgen.sv \
7172
$::env(DESIGN_DIR)/../../verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv\
7273
$::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
7374
"

‎openlane/user_project_wrapper/config.tcl

Lines changed: 56 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -20,11 +20,11 @@ set ::env(PDK) "sky130A"
2020
set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
2121

2222
# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS
23-
source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/fixed_wrapper_cfgs.tcl
23+
source $::env(DESIGN_DIR)/fixed_dont_change/fixed_wrapper_cfgs.tcl
2424

2525

2626
# YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL
27-
source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/default_wrapper_cfgs.tcl
27+
source $::env(DESIGN_DIR)/fixed_dont_change/default_wrapper_cfgs.tcl
2828

2929

3030
set script_dir [file dirname [file normalize [info script]]]
@@ -39,7 +39,6 @@ set gds_root $::env(DESIGN_DIR)/../../gds/
3939
# User Configurations
4040
#
4141
set ::env(DESIGN_IS_CORE) 1
42-
set ::env(FP_PDN_CORE_RING) 1
4342

4443

4544
## Source Verilog Files
@@ -56,10 +55,9 @@ set ::env(CLOCK_PERIOD) "10"
5655

5756
## Internal Macros
5857
### Macro Placement
59-
set ::env(FP_SIZING) "absolute"
6058
set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
6159

62-
set ::env(PDN_CFG) $proj_dir/pdn_cfg.tcl
60+
#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn_cfg.tcl
6361

6462
set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
6563
set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
@@ -70,40 +68,40 @@ set ::env(SYNTH_READ_BLACKBOX_LIB) 1
7068
set ::env(VERILOG_FILES_BLACKBOX) "\
7169
$::env(DESIGN_DIR)/../../verilog/gl/qspim_top.v \
7270
$::env(DESIGN_DIR)/../../verilog/gl/wb_interconnect.v \
73-
$::env(DESIGN_DIR)/../../verilog/gl/pinmux.v \
71+
$::env(DESIGN_DIR)/../../verilog/gl/pinmux_top.v \
7472
$::env(DESIGN_DIR)/../../verilog/gl/uart_i2c_usb_spi_top.v \
75-
$::env(DESIGN_DIR)/../../verilog/gl/wb_host.v \
76-
$::env(DESIGN_DIR)/../../verilog/gl/ycr_intf.v \
77-
$::env(DESIGN_DIR)/../../verilog/gl/ycr_core_top.v \
78-
$::env(DESIGN_DIR)/../../verilog/gl/ycr4_iconnect.v \
79-
$::env(DESIGN_DIR)/../../verilog/gl/digital_pll.v \
80-
$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
73+
$::env(DESIGN_DIR)/../../verilog/gl/wb_host.v \
74+
$::env(DESIGN_DIR)/../../verilog/gl/ycr_intf.v \
75+
$::env(DESIGN_DIR)/../../verilog/gl/ycr_core_top.v \
76+
$::env(DESIGN_DIR)/../../verilog/gl/ycr4_iconnect.v \
77+
$::env(DESIGN_DIR)/../../verilog/gl/digital_pll.v \
78+
$::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
8179
"
8280

8381
set ::env(EXTRA_LEFS) "\
8482
$lef_root/qspim_top.lef \
85-
$lef_root/pinmux.lef \
83+
$lef_root/pinmux_top.lef \
8684
$lef_root/wb_interconnect.lef \
8785
$lef_root/uart_i2c_usb_spi_top.lef \
8886
$lef_root/wb_host.lef \
8987
$lef_root/ycr_intf.lef \
9088
$lef_root/ycr_core_top.lef \
9189
$lef_root/ycr4_iconnect.lef \
9290
$lef_root/digital_pll.lef \
93-
$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
91+
$::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
9492
"
9593

9694
set ::env(EXTRA_GDS_FILES) "\
9795
$gds_root/qspim_top.gds \
98-
$gds_root/pinmux.gds \
96+
$gds_root/pinmux_top.gds \
9997
$gds_root/wb_interconnect.gds \
10098
$gds_root/uart_i2c_usb_spi_top.gds \
10199
$gds_root/wb_host.gds \
102100
$gds_root/ycr_intf.gds \
103101
$gds_root/ycr_core_top.gds \
104102
$gds_root/ycr4_iconnect.gds \
105103
$gds_root/digital_pll.gds \
106-
$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
104+
$::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
107105
"
108106

109107
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
@@ -119,52 +117,54 @@ set ::env(FP_PDN_CHECK_NODES) 0
119117
## Internal Macros
120118
### Macro PDN Connections
121119
set ::env(FP_PDN_ENABLE_MACROS_GRID) "1"
122-
set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1"
120+
#set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1"
123121

124-
set ::env(VDD_NETS) {vccd1 vccd2 vdda1 vdda2}
125-
set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2}
126-
#
122+
set ::env(VDD_NET) {vccd1}
127123
set ::env(VDD_PIN) {vccd1}
124+
set ::env(GND_NET) {vssd1}
128125
set ::env(GND_PIN) {vssd1}
129126

130-
set ::env(GLB_RT_OBS) " \
127+
128+
set ::env(GRT_OBS) " \
131129
li1 150 130 833.1 546.54,\
132130
met1 150 130 833.1 546.54,\
133131
met2 150 130 833.1 546.54,\
134-
met3 150 130 833.1 546.54,\
132+
met3 150 130 833.1 546.54,\
133+
135134
li1 950 130 1633.1 546.54,\
136135
met1 950 130 1633.1 546.54,\
137136
met2 950 130 1633.1 546.54,\
138-
met3 950 130 1633.1 546.54,\
139-
li1 150 750 833.1 1166.54,\
140-
met1 150 750 833.1 1166.54,\
141-
met2 150 750 833.1 1166.54,\
142-
met3 150 750 833.1 1166.54,\
137+
met3 950 130 1633.1 546.54,\
138+
139+
li1 150 750 833.1 1166.54,\
140+
met1 150 750 833.1 1166.54,\
141+
met2 150 750 833.1 1166.54,\
142+
met3 150 750 833.1 1166.54,\
143143
met5 0 0 2920 3520"
144144

145-
set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0"
146-
147-
#set ::env(FP_PDN_MACRO_HOOKS) " \
148-
# u_intercon vccd1 vssd1,\
149-
# u_pinmux vccd1 vssd1,\
150-
# u_qspi_master vccd1 vssd1,\
151-
# u_riscv_top vccd1 vssd1,\
152-
# u_tsram0_2kb vccd1 vssd1,\
153-
# u_icache_2kb vccd1 vssd1,\
154-
# u_dcache_2kb vccd1 vssd1,\
155-
# u_sram0_2kb vccd1 vssd1,\
156-
# u_sram1_2kb vccd1 vssd1,\
157-
# u_sram2_2kb vccd1 vssd1,\
158-
# u_sram3_2kb vccd1 vssd1,\
159-
# u_uart_i2c_usb_spi vccd1 vssd1,\
160-
# u_wb_host vccd1 vssd1,\
161-
# u_riscv_top.i_core_top_0 vccd1 vssd1, \
162-
# u_riscv_top.u_intf vccd1 vssd1 \
163-
# "
145+
#set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 1, vdda2 vssa2 1"
146+
147+
set ::env(FP_PDN_MACRO_HOOKS) " \
148+
u_pll vccd1 vssd1 VPWR VGND, \
149+
u_intercon vccd1 vssd1 vccd1 vssd1,\
150+
u_pinmux vccd1 vssd1 vccd1 vssd1,\
151+
u_qspi_master vccd1 vssd1 vccd1 vssd1,\
152+
u_tsram0_2kb vccd1 vssd1 vccd1 vssd1,\
153+
u_icache_2kb vccd1 vssd1 vccd1 vssd1,\
154+
u_dcache_2kb vccd1 vssd1 vccd1 vssd1,\
155+
u_uart_i2c_usb_spi vccd1 vssd1 vccd1 vssd1,\
156+
u_wb_host vccd1 vssd1 vccd1 vssd1,\
157+
u_riscv_top.i_core_top_0 vccd1 vssd1 vccd1 vssd1, \
158+
u_riscv_top.i_core_top_1 vccd1 vssd1 vccd1 vssd1, \
159+
u_riscv_top.i_core_top_2 vccd1 vssd1 vccd1 vssd1, \
160+
u_riscv_top.i_core_top_3 vccd1 vssd1 vccd1 vssd1, \
161+
u_riscv_top.u_connect vccd1 vssd1 VPWR VGND, \
162+
u_riscv_top.u_intf vccd1 vssd1 vccd1 vssd1 \
163+
"
164+
164165

165166

166167
# The following is because there are no std cells in the example wrapper project.
167-
set ::env(CELL_PAD) "4"
168168
set ::env(SYNTH_TOP_LEVEL) 0
169169
set ::env(PL_RANDOM_GLB_PLACEMENT) 1
170170
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
@@ -181,14 +181,15 @@ set ::env(QUIT_ON_MAGIC_DRC) "0"
181181
set ::env(QUIT_ON_NEGATIVE_WNS) "0"
182182
set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
183183
set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
184-
set ::env(FP_PDN_IRDROP) "0"
184+
185+
set ::env(FP_PDN_IRDROP) "1"
185186
set ::env(FP_PDN_HORIZONTAL_HALO) "10"
186187
set ::env(FP_PDN_VERTICAL_HALO) "10"
188+
189+
#
190+
187191
set ::env(FP_PDN_VOFFSET) "5"
188-
set ::env(FP_PDN_VPITCH) "80"
189-
set ::env(FP_PDN_VSPACING) "15.5"
190-
set ::env(FP_PDN_VWIDTH) "3.1"
191-
set ::env(FP_PDN_HOFFSET) "10"
192-
set ::env(FP_PDN_HPITCH) "90"
193-
set ::env(FP_PDN_HSPACING) "10"
194-
set ::env(FP_PDN_HWIDTH) "3.1"
192+
set ::env(FP_PDN_VPITCH) "180"
193+
set ::env(FP_PDN_HOFFSET) "5"
194+
set ::env(FP_PDN_HPITCH) "180"
195+

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