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reginfo.c
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reginfo.c
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#include "reginfo.h"
#include "chipid.h"
#include "hal/hisi/hal_hisi.h"
#include "tools.h"
#include <assert.h>
#include <ctype.h>
#include <getopt.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
typedef const struct {
uint32_t address;
const char *funcs[];
} muxctrl_reg_t;
#define MUXCTRL(name, addr, ...) \
static muxctrl_reg_t name = {addr, {__VA_ARGS__, 0}};
MUXCTRL(CV100_0, 0x200f0000, "GPIO1_0", "SHUTTER_TRIG")
MUXCTRL(CV100_1, 0x200f0004, "GPIO1_1", "SDIO_CCLK_OUT")
MUXCTRL(CV100_2, 0x200f0008, "GPIO1_2", "SENSOR_CLK")
MUXCTRL(CV100_3, 0x200f000c, "GPIO1_4", "SPI0_SCLK")
MUXCTRL(CV100_4, 0x200f0010, "GPIO1_5", "SPI0_SDO")
MUXCTRL(CV100_5, 0x200f0014, "GPIO1_6", "SPI0_SDI")
MUXCTRL(CV100_6, 0x200f0018, "GPIO2_0", "I2C_SDA")
MUXCTRL(CV100_7, 0x200f001c, "GPIO2_1", "I2C_SCL")
MUXCTRL(CV100_8, 0x200f0020, "GPIO2_2", "UART1_RTSN")
MUXCTRL(CV100_9, 0x200f0024, "GPIO2_3", "UART1_RXD")
MUXCTRL(CV100_10, 0x200f0028, "GPIO2_4", "UART1_CTSN")
MUXCTRL(CV100_11, 0x200f002c, "GPIO2_5", "UART1_TXD")
MUXCTRL(CV100_12, 0x200f0030, "GPIO3_0", "MII_CRS", "VOU1120_DATA10")
MUXCTRL(CV100_13, 0x200f0034, "GPIO3_1", "MII_COL", "VOU1120_DATA9")
MUXCTRL(CV100_14, 0x200f0038, "GPIO4_3", "MII_RXD3", "VOU1120_DATA15")
MUXCTRL(CV100_15, 0x200f003c, "GPIO4_2", "MII_RXD2", "VOU1120_DATA11")
MUXCTRL(CV100_16, 0x200f0040, "GPIO4_1", "MII_RXD1", "VOU1120_DATA8")
MUXCTRL(CV100_17, 0x200f0044, "GPIO4_0", "MII_RXD0", "VOU1120_DATA12")
MUXCTRL(CV100_18, 0x200f0048, "GPIO4_7", "MII_TXD3", "VOU1120_DATA3")
MUXCTRL(CV100_19, 0x200f004c, "GPIO4_6", "MII_TXD2", "VOU1120_DATA13")
MUXCTRL(CV100_20, 0x200f0050, "GPIO4_5", "MII_TXD1", "VOU1120_DATA0")
MUXCTRL(CV100_21, 0x200f0054, "GPIO4_4", "MII_TXD0", "VOU1120_DATA4")
MUXCTRL(CV100_22, 0x200f0058, "GPIO3_2", "MII_RXCK", "VOU1120_CLK")
MUXCTRL(CV100_23, 0x200f005c, "GPIO3_3", "MII_TXCK", "VOU1120_DATA7",
"RMII_CLK")
MUXCTRL(CV100_24, 0x200f0060, "GPIO3_4", "MII_RXDV", "VOU1120_DATA1")
MUXCTRL(CV100_25, 0x200f0064, "GPIO3_5", "MII_TXEN", "VOU1120_DATA5")
MUXCTRL(CV100_26, 0x200f0068, "GPIO2_6", "MII_TXER")
MUXCTRL(CV100_27, 0x200f006c, "GPIO2_7", "MII_RXER")
MUXCTRL(CV100_28, 0x200f0070, "GPIO1_3", "EPHY_CLK", "VOU1120_DATA2")
MUXCTRL(CV100_29, 0x200f0074, "GPIO3_6", "MDCK", "VOU1120_DATA6", "BOOT_SEL")
MUXCTRL(CV100_30, 0x200f0078, "GPIO3_7", "MDIO", "VOU1120_DATA14")
MUXCTRL(CV100_31, 0x200f007c, "GPIO1_7", "FLASH_TRIG")
MUXCTRL(CV100_32, 0x200f0080, "GPIO6_0", "SDIO_CARD_DETECT")
MUXCTRL(CV100_33, 0x200f0084, "GPIO6_1", "SDIO_CARD_POWER_EN")
MUXCTRL(CV100_34, 0x200f0088, "GPIO6_2", "SDIO_CWPR")
MUXCTRL(CV100_35, 0x200f008c, "GPIO6_3", "SDIO_CCMD")
MUXCTRL(CV100_36, 0x200f0090, "GPIO6_4", "SDIO_CDATA0", "CLK_TEST_OUT0",
"CLK_TEST_OUT1", "CLK_TEST_OUT2", "CLK_TEST_OUT3")
MUXCTRL(CV100_37, 0x200f0094, "PLL_TEST_OUT0", "SDIO_CDATA1", "GPIO6_5",
"PLL_TEST_OUT1", "PLL_TEST_OUT2", "PLL_TEST_OUT3", "RTC_TEST_CLK")
MUXCTRL(CV100_38, 0x200f0098, "GPIO6_6", "SDIO_CDATA2")
MUXCTRL(CV100_39, 0x200f009c, "GPIO6_7", "SDIO_CDATA3")
MUXCTRL(CV100_40, 0x200f00a0, "SFC_DIO", "GPIO7_0")
MUXCTRL(CV100_41, 0x200f00a4, "SFC_WP_IO2", "GPIO7_1")
MUXCTRL(CV100_42, 0x200f00a8, "SFC_CLK", "GPIO7_2", "SFC_ADDR_MODE")
MUXCTRL(CV100_43, 0x200f00ac, "SFC_DOI", "GPIO7_3")
MUXCTRL(CV100_44, 0x200f00b0, "SFC_HOLD_IO3", "GPIO7_4")
MUXCTRL(CV100_45, 0x200f00b4, "GPIO5_0", "USB_OVRCUR")
MUXCTRL(CV100_46, 0x200f00b8, "GPIO5_1", "USB_PWREN")
MUXCTRL(CV100_47, 0x200f00bc, "GPIO5_2", "PWM_OUT0")
MUXCTRL(CV100_48, 0x200f00c0, "GPIO5_3", "PWM_OUT1")
MUXCTRL(CV100_49, 0x200f00c4, "IR_IN", "GPIO7_5")
MUXCTRL(CV100_50, 0x200f00c8, "reserved", "GPIO9_0")
MUXCTRL(CV100_51, 0x200f00cc, "reserved", "GPIO9_1")
MUXCTRL(CV100_52, 0x200f00d0, "reserved", "GPIO9_2")
MUXCTRL(CV100_53, 0x200f00d4, "reserved", "GPIO9_3")
MUXCTRL(CV100_54, 0x200f00d8, "reserved", "GPIO9_4")
MUXCTRL(CV100_55, 0x200f00dc, "reserved", "GPIO9_5")
MUXCTRL(CV100_56, 0x200f00e0, "reserved", "GPIO9_6")
MUXCTRL(CV100_57, 0x200f00e4, "reserved", "GPIO9_7")
MUXCTRL(CV100_66, 0x200f0108, "GPIO7_6", "UART2_RXD")
MUXCTRL(CV100_67, 0x200f010c, "GPIO7_7", "UART2_TXD")
MUXCTRL(CV100_68, 0x200f0110, "GPIO5_4", "SPI1_SCLK")
MUXCTRL(CV100_69, 0x200f0114, "GPIO5_5", "SPI1_SDO")
MUXCTRL(CV100_70, 0x200f0118, "GPIO5_6", "SPI1_SDI")
MUXCTRL(CV100_71, 0x200f011c, "GPIO5_7", "SPI1_CSN")
MUXCTRL(CV100_72, 0x200f0120, "GPIO0_0", "JTAG_TRSTN", "TEMPER_DQ")
MUXCTRL(CV100_73, 0x200f0124, "GPIO0_1", "JTAG_TCK", "TEMPER_DQ")
MUXCTRL(CV100_74, 0x200f0128, "GPIO0_2", "JTAG_TMS", "TEMPER_DQ")
MUXCTRL(CV100_75, 0x200f012c, "GPIO0_3", "JTAG_TDO", "TEMPER_DQ")
MUXCTRL(CV100_76, 0x200f0130, "GPIO0_4", "JTAG_TDI", "TEMPER_DQ")
MUXCTRL(CV100_77, 0x200f0134, "SVB_PWM", "GPIO0_5", "TEMPER_DQ")
MUXCTRL(CV100_78, 0x200f0138, "GPIO0_6", "SVB_PWM", "TEMPER_DQ")
MUXCTRL(CV100_79, 0x200f013c, "SYS_RSTN_OUT", "GPIO0_7", "TEMPER_DQ")
MUXCTRL(CV100_80, 0x200f0140, "VIU_CLK", "GPIO11_6")
MUXCTRL(CV100_81, 0x200f0144, "VIU_VS", "GPIO11_5")
MUXCTRL(CV100_82, 0x200f0148, "VIU_HS", "GPIO11_4")
MUXCTRL(CV100_83, 0x200f014c, "VIU_DAT11", "GPIO11_3")
MUXCTRL(CV100_84, 0x200f0150, "VIU_DAT10", "GPIO11_2")
MUXCTRL(CV100_85, 0x200f0154, "VIU_DAT9", "GPIO11_1")
MUXCTRL(CV100_86, 0x200f0158, "VIU_DAT8", "GPIO11_0")
MUXCTRL(CV100_87, 0x200f015c, "VIU_DAT7", "GPIO10_7")
MUXCTRL(CV100_88, 0x200f0160, "VIU_DAT6", "GPIO10_6")
MUXCTRL(CV100_89, 0x200f0164, "VIU_DAT5", "GPIO10_5")
MUXCTRL(CV100_90, 0x200f0168, "VIU_DAT4", "GPIO10_4")
MUXCTRL(CV100_91, 0x200f016c, "VIU_DAT3", "GPIO10_3")
MUXCTRL(CV100_92, 0x200f0170, "VIU_DAT2", "GPIO10_2")
MUXCTRL(CV100_93, 0x200f0174, "VIU_DAT1", "GPIO10_1")
MUXCTRL(CV100_94, 0x200f0178, "VIU_DAT0", "GPIO10_0")
static const muxctrl_reg_t *CV100regs[] = {
&CV100_0, &CV100_1, &CV100_2, &CV100_3, &CV100_4, &CV100_5, &CV100_6,
&CV100_7, &CV100_8, &CV100_9, &CV100_10, &CV100_11, &CV100_12, &CV100_13,
&CV100_14, &CV100_15, &CV100_16, &CV100_17, &CV100_18, &CV100_19, &CV100_20,
&CV100_21, &CV100_22, &CV100_23, &CV100_24, &CV100_25, &CV100_26, &CV100_27,
&CV100_28, &CV100_29, &CV100_30, &CV100_31, &CV100_32, &CV100_33, &CV100_34,
&CV100_35, &CV100_36, &CV100_37, &CV100_38, &CV100_39, &CV100_40, &CV100_41,
&CV100_42, &CV100_43, &CV100_44, &CV100_45, &CV100_46, &CV100_47, &CV100_48,
&CV100_49, &CV100_50, &CV100_51, &CV100_52, &CV100_53, &CV100_54, &CV100_55,
&CV100_56, &CV100_57, &CV100_66, &CV100_67, &CV100_68, &CV100_69, &CV100_70,
&CV100_71, &CV100_72, &CV100_73, &CV100_74, &CV100_75, &CV100_76, &CV100_77,
&CV100_78, &CV100_79, &CV100_80, &CV100_81, &CV100_82, &CV100_83, &CV100_84,
&CV100_85, &CV100_86, &CV100_87, &CV100_88, &CV100_89, &CV100_90, &CV100_91,
&CV100_92, &CV100_93, &CV100_94, 0,
};
MUXCTRL(AV100_0, 0x200f0000, "GPIO0_5", "SENSOR_CLK")
MUXCTRL(AV100_1, 0x200f0004, "GPIO0_6", "FLASH_TRIG", "SPI1_CSN1")
MUXCTRL(AV100_2, 0x200f0008, "GPIO0_7", "SHUTTER_TRIG", "SPI1_CSN2")
MUXCTRL(AV100_3, 0x200f000c, "GPIO1_0", "VO_CLK")
MUXCTRL(AV100_4, 0x200f0010, "GPIO6_0", "VO_DAT15")
MUXCTRL(AV100_5, 0x200f0014, "GPIO6_1", "VO_DAT14")
MUXCTRL(AV100_6, 0x200f0018, "GPIO6_2", "VO_DAT13")
MUXCTRL(AV100_7, 0x200f001c, "GPIO6_3", "VO_DAT12")
MUXCTRL(AV100_8, 0x200f0020, "GPIO6_4", "VO_DAT11", "SFC_NAND_BOOT_PIN2")
MUXCTRL(AV100_9, 0x200f0024, "GPIO6_5", "VO_DAT10", "SFC_NAND_BOOT_PIN1")
MUXCTRL(AV100_10, 0x200f0028, "GPIO6_6", "VO_DAT9", "SFC_NAND_BOOT_PIN0")
MUXCTRL(AV100_11, 0x200f002c, "GPIO6_7", "VO_DAT8")
MUXCTRL(AV100_12, 0x200f0030, "GPIO7_0", "VO_DAT7")
MUXCTRL(AV100_13, 0x200f0034, "GPIO7_1", "VO_DAT6")
MUXCTRL(AV100_14, 0x200f0038, "GPIO7_2", "VO_DAT5")
MUXCTRL(AV100_15, 0x200f003c, "GPIO7_3", "VO_DAT4")
MUXCTRL(AV100_16, 0x200f0040, "GPIO7_4", "VO_DAT3", "SFC_DEVICE_MODE")
MUXCTRL(AV100_17, 0x200f0044, "GPIO7_5", "VO_DAT2")
MUXCTRL(AV100_18, 0x200f0048, "GPIO7_6", "VO_DAT1", "BOOTROM_SEL")
MUXCTRL(AV100_19, 0x200f004c, "GPIO7_7", "VO_DAT0", "BOOT_SEL")
MUXCTRL(AV100_20, 0x200f0050, "GPIO8_0", "SPI0_SCLK", "I2C0_SCL")
MUXCTRL(AV100_21, 0x200f0054, "GPIO8_1", "SPI0_SDO", "I2C0_SDA")
MUXCTRL(AV100_22, 0x200f0058, "GPIO8_2", "SPI0_SDI")
MUXCTRL(AV100_23, 0x200f005c, "GPIO8_3", "SPI0_CSN")
MUXCTRL(AV100_24, 0x200f0060, "GPIO8_4", "SPI1_SCLK", "I2C1_SCL")
MUXCTRL(AV100_25, 0x200f0064, "GPIO8_5", "SPI1_SDO", "I2C1_SDA")
MUXCTRL(AV100_26, 0x200f0068, "GPIO8_6", "SPI1_SDI")
MUXCTRL(AV100_27, 0x200f006c, "GPIO8_7", "SPI1_CSN0")
MUXCTRL(AV100_28, 0x200f0070, "GPIO9_0", "I2C2_SDA")
MUXCTRL(AV100_29, 0x200f0074, "GPIO9_1", "I2C2_SCL")
MUXCTRL(AV100_30, 0x200f0078, "GPIO9_2", "UART1_RTSN", "UART3_RXD")
MUXCTRL(AV100_31, 0x200f007c, "GPIO9_3", "UART1_RXD")
MUXCTRL(AV100_32, 0x200f0080, "GPIO9_4", "UART1_CTSN", "UART3_TXD")
MUXCTRL(AV100_33, 0x200f0084, "GPIO9_5", "UART1_TXD")
MUXCTRL(AV100_34, 0x200f0088, "GPIO9_6", "UART2_RXD", "I2S_BCLK_RX")
MUXCTRL(AV100_35, 0x200f008c, "GPIO9_7", "UART2_TXD", "I2S_WS_RX")
MUXCTRL(AV100_36, 0x200f0090, "GPIO10_0", "JTAG_TRSTN", "I2S_MCLK")
MUXCTRL(AV100_37, 0x200f0094, "GPIO10_1", "JTAG_TCK", "I2S_BCLK_TX")
MUXCTRL(AV100_38, 0x200f0098, "GPIO10_2", "JTAG_TMS", "I2S_WS_TX")
MUXCTRL(AV100_39, 0x200f009c, "GPIO10_3", "JTAG_TDO", "I2S_SD_RX")
MUXCTRL(AV100_40, 0x200f00a0, "GPIO10_4", "JTAG_TDI", "I2S_SD_TX")
MUXCTRL(AV100_41, 0x200f00a4, "GPIO10_5", "IR_IN", "PWM4")
MUXCTRL(AV100_42, 0x200f00a8, "GPIO10_6", "USB_OVRCUR")
MUXCTRL(AV100_43, 0x200f00ac, "GPIO10_7", "USB_PWREN")
MUXCTRL(AV100_44, 0x200f00b0, "GPIO2_0", "SDIO0_CCLK_OUT", "I2S_MCLK")
MUXCTRL(AV100_45, 0x200f00b4, "GPIO2_1", "SDIO0_CARD_POWER_EN", "I2S_BCLK_TX")
MUXCTRL(AV100_46, 0x200f00b8, "GPIO2_2", "SDIO0_CARD_DETECT", "I2S_WS_TX")
MUXCTRL(AV100_47, 0x200f00bc, "GPIO2_3", "SDIO0_CWPR", "I2S_SD_TX")
MUXCTRL(AV100_48, 0x200f00c0, "GPIO2_4", "SDIO0_CCMD", "I2S_BCLK_RX")
MUXCTRL(AV100_49, 0x200f00c4, "GPIO2_5", "SDIO0_CDATA0", "I2S_WS_RX")
MUXCTRL(AV100_50, 0x200f00c8, "GPIO2_6", "SDIO0_CDATA1", "I2S_SD_RX")
MUXCTRL(AV100_51, 0x200f00cc, "GPIO2_7", "SDIO0_CDATA2")
MUXCTRL(AV100_52, 0x200f00d0, "GPIO1_1", "SDIO0_CDATA3")
MUXCTRL(AV100_53, 0x200f00d4, "SENSOR_RSTN", "GPIO0_0", "TEMPER_DQ")
MUXCTRL(AV100_54, 0x200f00d8, "GPIO0_1", "TEMPER_DQ")
MUXCTRL(AV100_55, 0x200f00dc, "GPIO0_2", "PWM5", "TEMPER_DQ")
MUXCTRL(AV100_56, 0x200f00e0, "GPIO0_3", "PWM6", "TEMPER_DQ")
MUXCTRL(AV100_57, 0x200f00e4, "GPIO0_4", "PWM7", "TEMPER_DQ")
MUXCTRL(AV100_58, 0x200f00e8, "GPIO11_0", "SDIO1_CCLK_OUT")
MUXCTRL(AV100_59, 0x200f00ec, "GPIO11_1", "SDIO1_CARD_POWER_EN")
MUXCTRL(AV100_60, 0x200f00f0, "GPIO11_2", "SDIO1_CARD_DETECT")
MUXCTRL(AV100_61, 0x200f00f4, "GPIO11_3", "SDIO1_CWPR")
MUXCTRL(AV100_62, 0x200f00f8, "GPIO11_4", "SDIO1_CCMD")
MUXCTRL(AV100_63, 0x200f00fc, "GPIO11_5", "SDIO1_CDATA0", "CLK_TEST_OUT0",
"CLK_TEST_OUT1", "CLK_TEST_OUT2", "CLK_TEST_OUT3", "RTC_TEST_CLK",
"OSC_TEST_CLK")
MUXCTRL(AV100_64, 0x200f0100, "PLL_TEST_OUT0", "SDIO1_CDATA1", "PLL_TEST_OUT1",
"PLL_TEST_OUT2", "PLL_TEST_OUT3", "GPIO11_6")
MUXCTRL(AV100_65, 0x200f0104, "GPIO11_7", "SDIO1_CDATA2")
MUXCTRL(AV100_66, 0x200f0108, "GPIO1_2", "SDIO1_CDATA3")
MUXCTRL(AV100_67, 0x200f010c, "NF_DQ0", "GPIO5_0")
MUXCTRL(AV100_68, 0x200f0110, "NF_DQ1", "GPIO5_1")
MUXCTRL(AV100_69, 0x200f0114, "NF_DQ2", "GPIO5_2")
MUXCTRL(AV100_70, 0x200f0118, "NF_DQ3", "GPIO5_3")
MUXCTRL(AV100_71, 0x200f011c, "NF_DQ4", "GPIO5_4")
MUXCTRL(AV100_72, 0x200f0120, "NF_DQ5", "GPIO5_5")
MUXCTRL(AV100_73, 0x200f0124, "NF_DQ6", "GPIO5_6")
MUXCTRL(AV100_74, 0x200f0128, "NF_DQ7", "GPIO5_7")
MUXCTRL(AV100_75, 0x200f012c, "NF_RDY0", "GPIO3_0")
MUXCTRL(AV100_76, 0x200f0130, "NF_RDY1", "GPIO3_1")
MUXCTRL(AV100_77, 0x200f0134, "NF_REN", "GPIO3_2")
MUXCTRL(AV100_78, 0x200f0138, "NF_CSN0", "GPIO3_3")
MUXCTRL(AV100_79, 0x200f013c, "NF_CSN1", "GPIO3_4", "SFC_CSN0")
MUXCTRL(AV100_80, 0x200f0140, "NF_CLE", "GPIO3_5")
MUXCTRL(AV100_81, 0x200f0144, "NF_ALE", "GPIO3_6")
MUXCTRL(AV100_82, 0x200f0148, "NF_WEN", "GPIO3_7")
MUXCTRL(AV100_83, 0x200f014c, "PWM0", "GPIO14_0", "PMC_I2C_SCL")
MUXCTRL(AV100_84, 0x200f0150, "PWM1", "GPIO14_1", "PMC_I2C_SDA")
MUXCTRL(AV100_85, 0x200f0154, "PWM2", "GPIO14_2")
MUXCTRL(AV100_86, 0x200f0158, "PWM3", "GPIO14_3")
MUXCTRL(AV100_87, 0x200f015c, "SAR_ADC_CH0", "GPIO1_6")
MUXCTRL(AV100_88, 0x200f0160, "SAR_ADC_CH1", "GPIO1_7")
MUXCTRL(AV100_89, 0x200f0164, "GPIO14_4", "EPHY_CLK")
MUXCTRL(AV100_90, 0x200f0168, "GPIO14_5", "MDCK")
MUXCTRL(AV100_91, 0x200f016c, "GPIO14_6", "MDIO")
MUXCTRL(AV100_92, 0x200f0170, "GPIO14_7", "RGMII_TX_EN")
MUXCTRL(AV100_93, 0x200f0174, "GPIO4_0", "RGMII_TX_CLK",
"RMII_CLK_OUT/MII_TX_CLK")
MUXCTRL(AV100_94, 0x200f0178, "GPIO4_1", "RGMII_TXD0")
MUXCTRL(AV100_95, 0x200f017c, "GPIO4_2", "RGMII_TXD1")
MUXCTRL(AV100_96, 0x200f0180, "GPIO4_3", "RGMII_TXD2")
MUXCTRL(AV100_97, 0x200f0184, "GPIO4_4", "RGMII_TXD3")
MUXCTRL(AV100_98, 0x200f0188, "GPIO4_5", "RGMII_RX_CLK")
MUXCTRL(AV100_99, 0x200f018c, "GPIO4_6", "RGMII_RX_DV")
MUXCTRL(AV100_100, 0x200f0190, "GPIO4_7", "RGMII_RXD0")
MUXCTRL(AV100_101, 0x200f0194, "GPIO1_3", "RGMII_RXD1")
MUXCTRL(AV100_102, 0x200f0198, "GPIO1_4", "RGMII_RXD2")
MUXCTRL(AV100_103, 0x200f019c, "GPIO1_5", "RGMII_RXD3")
MUXCTRL(AV100_104, 0x200f01a0, "GPIO15_0", "VI_CLK")
MUXCTRL(AV100_105, 0x200f01a4, "GPIO15_1", "VI_HS")
MUXCTRL(AV100_106, 0x200f01a8, "GPIO15_2", "VI_VS")
MUXCTRL(AV100_107, 0x200f01ac, "GPIO12_0", "VI_DAT15", "I2S_MCLK")
MUXCTRL(AV100_108, 0x200f01b0, "GPIO12_1", "VI_DAT14", "I2S_BCLK_TX")
MUXCTRL(AV100_109, 0x200f01b4, "GPIO12_2", "VI_DAT13", "I2S_WS_TX")
MUXCTRL(AV100_110, 0x200f01b8, "GPIO12_3", "VI_DAT12", "I2S_SD_TX")
MUXCTRL(AV100_111, 0x200f01bc, "GPIO12_4", "VI_DAT11", "I2S_BCLK_RX")
MUXCTRL(AV100_112, 0x200f01c0, "GPIO12_5", "VI_DAT10", "I2S_WS_RX")
MUXCTRL(AV100_113, 0x200f01c4, "GPIO12_6", "VI_DAT9", "I2S_SD_RX")
MUXCTRL(AV100_114, 0x200f01c8, "GPIO12_7", "VI_DAT8")
MUXCTRL(AV100_115, 0x200f01cc, "GPIO13_0", "VI_DAT7")
MUXCTRL(AV100_116, 0x200f01d0, "GPIO13_1", "VI_DAT6")
MUXCTRL(AV100_117, 0x200f01d4, "GPIO13_2", "VI_DAT5")
MUXCTRL(AV100_118, 0x200f01d8, "GPIO13_3", "VI_DAT4")
MUXCTRL(AV100_119, 0x200f01dc, "GPIO13_4", "VI_DAT3")
MUXCTRL(AV100_120, 0x200f01e0, "GPIO13_5", "VI_DAT2")
MUXCTRL(AV100_121, 0x200f01e4, "GPIO13_6", "VI_DAT1")
MUXCTRL(AV100_122, 0x200f01e8, "GPIO13_7", "VI_DAT0", "PWM4")
static const muxctrl_reg_t *AV100regs[] = {
&AV100_0, &AV100_1, &AV100_2, &AV100_3, &AV100_4, &AV100_5,
&AV100_6, &AV100_7, &AV100_8, &AV100_9, &AV100_10, &AV100_11,
&AV100_12, &AV100_13, &AV100_14, &AV100_15, &AV100_16, &AV100_17,
&AV100_18, &AV100_19, &AV100_20, &AV100_21, &AV100_22, &AV100_23,
&AV100_24, &AV100_25, &AV100_26, &AV100_27, &AV100_28, &AV100_29,
&AV100_30, &AV100_31, &AV100_32, &AV100_33, &AV100_34, &AV100_35,
&AV100_36, &AV100_37, &AV100_38, &AV100_39, &AV100_40, &AV100_41,
&AV100_42, &AV100_43, &AV100_44, &AV100_45, &AV100_46, &AV100_47,
&AV100_48, &AV100_49, &AV100_50, &AV100_51, &AV100_52, &AV100_53,
&AV100_54, &AV100_55, &AV100_56, &AV100_57, &AV100_58, &AV100_59,
&AV100_60, &AV100_61, &AV100_62, &AV100_63, &AV100_64, &AV100_65,
&AV100_66, &AV100_67, &AV100_68, &AV100_69, &AV100_70, &AV100_71,
&AV100_72, &AV100_73, &AV100_74, &AV100_75, &AV100_76, &AV100_77,
&AV100_78, &AV100_79, &AV100_80, &AV100_81, &AV100_82, &AV100_83,
&AV100_84, &AV100_85, &AV100_86, &AV100_87, &AV100_88, &AV100_89,
&AV100_90, &AV100_91, &AV100_92, &AV100_93, &AV100_94, &AV100_95,
&AV100_96, &AV100_97, &AV100_98, &AV100_99, &AV100_100, &AV100_101,
&AV100_102, &AV100_103, &AV100_104, &AV100_105, &AV100_106, &AV100_107,
&AV100_108, &AV100_109, &AV100_110, &AV100_111, &AV100_112, &AV100_113,
&AV100_114, &AV100_115, &AV100_116, &AV100_117, &AV100_118, &AV100_119,
&AV100_120, &AV100_121, &AV100_122, 0,
};
MUXCTRL(CV200_0, 0x200f0000, "GPIO0_4", "SENSOR_CLK")
MUXCTRL(CV200_1, 0x200f0004, "SENSOR_RSTN", "GPIO0_5")
MUXCTRL(CV200_2, 0x200f0008, "GPIO0_6", "FLASH_TRIG", "SFC_EMMC_BOOT_MODE",
"SPI1_CSN1", "VI_VS_BT1120")
MUXCTRL(CV200_3, 0x200f000c, "GPIO0_7", "SHUTTER_TRIG", "SFC_DEVICE_MODE",
"VI_HS_BT1120")
MUXCTRL(CV200_4, 0x200f0010, "GPIO2_0", "RMII_CLK", "VO_CLK", "SDIO1_CCLK_OUT")
MUXCTRL(CV200_5, 0x200f0014, "GPIO2_1", "RMII_TX_EN", "VO_VS",
"SDIO1_CARD_DETECT")
MUXCTRL(CV200_6, 0x200f0018, "GPIO2_2", "RMII_TXD0", "VO_DATA5", "SDIO1_CWPR")
MUXCTRL(CV200_7, 0x200f001c, "GPIO2_3", "RMII_TXD1", "VO_DE", "SDIO1_CDATA1")
MUXCTRL(CV200_8, 0x200f0020, "GPIO2_4", "RMII_RX_DV", "VO_DATA7",
"SDIO1_CDATA0")
MUXCTRL(CV200_9, 0x200f0024, "GPIO2_5", "RMII_RXD0", "VO_DATA2", "SDIO1_CDATA3")
MUXCTRL(CV200_10, 0x200f0028, "GPIO2_6", "RMII_RXD1", "VO_DATA3", "SDIO1_CCMD")
MUXCTRL(CV200_11, 0x200f002c, "GPIO2_7", "EPHY_RST", "BOOT_SEL", "VO_HS",
"SDIO1_CARD_POWER_EN")
MUXCTRL(CV200_12, 0x200f0030, "GPIO0_3", "SPI1_CSN1", "VO_DATA0")
MUXCTRL(CV200_13, 0x200f0034, "GPIO3_0", "EPHY_CLK", "VO_DATA1", "SDIO1_CDATA2")
MUXCTRL(CV200_14, 0x200f0038, "GPIO3_1", "MDCK", "BOOTROM_SEL", "VO_DATA6")
MUXCTRL(CV200_15, 0x200f003c, "GPIO3_2", "MDIO", "VO_DATA4")
MUXCTRL(CV200_16, 0x200f0040, "GPIO3_3", "SPI0_SCLK", "I2C0_SCL")
MUXCTRL(CV200_17, 0x200f0044, "GPIO3_4", "SPI0_SDO", "I2C0_SDA")
MUXCTRL(CV200_18, 0x200f0048, "GPIO3_5", "SPI0_SDI")
MUXCTRL(CV200_19, 0x200f004c, "GPIO3_6", "SPI0_CSN")
MUXCTRL(CV200_20, 0x200f0050, "GPIO3_7", "SPI1_SCLK", "I2C1_SCL")
MUXCTRL(CV200_21, 0x200f0054, "GPIO4_0", "SPI1_SDO", "I2C1_SDA")
MUXCTRL(CV200_22, 0x200f0058, "GPIO4_1", "SPI1_SDI")
MUXCTRL(CV200_23, 0x200f005c, "GPIO4_2", "SPI1_CSN0")
MUXCTRL(CV200_24, 0x200f0060, "GPIO4_3", "I2C2_SDA")
MUXCTRL(CV200_25, 0x200f0064, "GPIO4_4", "I2C2_SCL")
MUXCTRL(CV200_26, 0x200f0068, "GPIO4_5", "USB_OVRCUR")
MUXCTRL(CV200_27, 0x200f006c, "GPIO4_6", "USB_PWREN")
MUXCTRL(CV200_28, 0x200f0070, "GPIO0_0", "IR_IN", "TEMPER_DQ")
MUXCTRL(CV200_29, 0x200f0074, "GPIO0_1", "TEMPER_DQ")
MUXCTRL(CV200_30, 0x200f0078, "GPIO0_2", "TEMPER_DQ")
MUXCTRL(CV200_31, 0x200f007c, "GPIO1_0", "VI_DATA13", "I2S_BCLK_TX", "PWM0")
MUXCTRL(CV200_32, 0x200f0080, "GPIO1_1", "VI_DATA10", "I2S_SD_TX", "UART1_TXD")
MUXCTRL(CV200_33, 0x200f0084, "GPIO1_2", "VI_DATA12", "I2S_MCLK", "UART1_CTSN")
MUXCTRL(CV200_34, 0x200f0088, "GPIO1_3", "VI_DATA11", "I2S_WS_TX", "UART2_RXD")
MUXCTRL(CV200_35, 0x200f008c, "GPIO1_4", "VI_DATA15", "VI_VS_SEN", "I2S_WS_RX",
"UART1_RXD")
MUXCTRL(CV200_36, 0x200f0090, "GPIO1_5", "VI_DATA14", "VI_HS_SEN",
"I2S_BCLK_RX", "UART1_RTSN")
MUXCTRL(CV200_37, 0x200f0094, "GPIO1_6", "VI_DATA9", "I2S_SD_RX", "UART2_TXD")
MUXCTRL(CV200_38, 0x200f0098, "GPIO1_7", "SDIO0_CARD_POWER_EN")
MUXCTRL(CV200_39, 0x200f009c, "GPIO4_7", "SDIO0_CARD_DETECT")
MUXCTRL(CV200_40, 0x200f00a0, "GPIO5_0", "SDIO0_CWPR")
MUXCTRL(CV200_41, 0x200f00a4, "GPIO5_1", "SDIO0_CCLK_OUT")
MUXCTRL(CV200_42, 0x200f00a8, "GPIO5_2", "SDIO0_CCMD")
MUXCTRL(CV200_43, 0x200f00ac, "GPIO5_3", "SDIO0_CDATA0")
MUXCTRL(CV200_44, 0x200f00b0, "TEST_CLK", "SDIO0_CDATA1", "GPIO5_4")
MUXCTRL(CV200_45, 0x200f00b4, "GPIO5_5", "SDIO0_CDATA2")
MUXCTRL(CV200_46, 0x200f00b8, "GPIO5_6", "SDIO0_CDATA3")
MUXCTRL(CV200_47, 0x200f00bc, "GPIO5_7", "EMMC_DATA6", "I2S_SD_TX",
"UART1_RTSN")
MUXCTRL(CV200_48, 0x200f00c0, "GPIO6_0", "EMMC_DATA5", "I2S_WS_TX", "UART1_RXD")
MUXCTRL(CV200_49, 0x200f00c4, "GPIO6_1", "EMMC_DATA7", "I2S_MCLK", "UART1_CTSN")
MUXCTRL(CV200_50, 0x200f00c8, "GPIO6_2", "EMMC_DS", "I2S_SD_RX", "UART1_TXD")
MUXCTRL(CV200_51, 0x200f00cc, "GPIO6_3", "EMMC_DATA1", "UART2_RXD")
MUXCTRL(CV200_52, 0x200f00d0, "GPIO6_4", "EMMC_DATA2", "I2S_BCLK_TX",
"UART2_TXD")
MUXCTRL(CV200_53, 0x200f00d4, "GPIO6_5", "JTAG_TRSTN", "SPI1_CSN1", "I2S_MCLK")
MUXCTRL(CV200_54, 0x200f00d8, "GPIO6_6", "JTAG_TCK", "SPI1_SCLK", "I2S_WS_TX",
"I2C1_SCL")
MUXCTRL(CV200_55, 0x200f00dc, "GPIO6_7", "JTAG_TMS", "SPI1_CSN0", "I2S_SD_TX")
MUXCTRL(CV200_56, 0x200f00e0, "GPIO7_0", "JTAG_TDO", "SPI1_SDO", "I2S_SD_RX",
"I2C1_SDA")
MUXCTRL(CV200_57, 0x200f00e4, "GPIO7_1", "JTAG_TDI", "SPI1_SDI", "I2S_BCLK_TX")
MUXCTRL(CV200_58, 0x200f00e8, "PMC_PWM", "GPIO7_2", "PWM0")
MUXCTRL(CV200_59, 0x200f00ec, "PWM1", "GPIO7_3")
MUXCTRL(CV200_60, 0x200f00f0, "PWM2", "GPIO7_4", "SPI1_CSN1")
MUXCTRL(CV200_61, 0x200f00f4, "PWM3", "GPIO7_5")
MUXCTRL(CV200_62, 0x200f00f8, "SAR_ADC_CH0", "GPIO7_6")
MUXCTRL(CV200_63, 0x200f00fc, "SAR_ADC_CH1", "GPIO7_7")
MUXCTRL(CV200_64, 0x200f0100, "SAR_ADC_CH2", "GPIO8_0")
MUXCTRL(CV200_65, 0x200f0104, "SAR_ADC_CH3", "GPIO8_1")
static const muxctrl_reg_t *CV200regs[] = {
&CV200_0, &CV200_1, &CV200_2, &CV200_3, &CV200_4, &CV200_5, &CV200_6,
&CV200_7, &CV200_8, &CV200_9, &CV200_10, &CV200_11, &CV200_12, &CV200_13,
&CV200_14, &CV200_15, &CV200_16, &CV200_17, &CV200_18, &CV200_19, &CV200_20,
&CV200_21, &CV200_22, &CV200_23, &CV200_24, &CV200_25, &CV200_26, &CV200_27,
&CV200_28, &CV200_29, &CV200_30, &CV200_31, &CV200_32, &CV200_33, &CV200_34,
&CV200_35, &CV200_36, &CV200_37, &CV200_38, &CV200_39, &CV200_40, &CV200_41,
&CV200_42, &CV200_43, &CV200_44, &CV200_45, &CV200_46, &CV200_47, &CV200_48,
&CV200_49, &CV200_50, &CV200_51, &CV200_52, &CV200_53, &CV200_54, &CV200_55,
&CV200_56, &CV200_57, &CV200_58, &CV200_59, &CV200_60, &CV200_61, &CV200_62,
&CV200_63, &CV200_64, &CV200_65, 0,
};
MUXCTRL(EV20X_0, 0x200f0000, "GPIO0_4", "SENSOR_CLK")
MUXCTRL(EV20X_1, 0x200f0004, "SENSOR_RSTN", "GPIO0_5")
MUXCTRL(EV20X_2, 0x200f0008, "GPIO0_6", "FLASH_TRIG", "SFC_EMMC_BOOT_MODE",
"SPI1_CSN1", "VI_VS_BT1120")
MUXCTRL(EV20X_3, 0x200f000c, "GPIO0_7", "SHUTTER_TRIG", "SFC_DEVICE_MODE",
"VI_HS_BT1120")
MUXCTRL(EV20X_4, 0x200f0010, "GPIO2_0", "RMII_CLK", "VO_CLK", "SDIO1_CCLK_OUT")
MUXCTRL(EV20X_5, 0x200f0014, "GPIO2_1", "RMII_TX_EN", "VO_VS",
"SDIO1_CARD_DETECT")
MUXCTRL(EV20X_6, 0x200f0018, "GPIO2_2", "RMII_TXD0", "VO_DATA5", "SDIO1_CWPR")
MUXCTRL(EV20X_7, 0x200f001c, "GPIO2_3", "RMII_TXD1", "VO_DE", "SDIO1_CDATA1")
MUXCTRL(EV20X_8, 0x200f0020, "GPIO2_4", "RMII_RX_DV", "VO_DATA7",
"SDIO1_CDATA0")
MUXCTRL(EV20X_9, 0x200f0024, "GPIO2_5", "RMII_RXD0", "VO_DATA2", "SDIO1_CDATA3")
MUXCTRL(EV20X_10, 0x200f0028, "GPIO2_6", "RMII_RXD1", "VO_DATA3", "SDIO1_CCMD")
MUXCTRL(EV20X_11, 0x200f002c, "GPIO2_7", "EPHY_RST", "BOOT_SEL", "VO_HS",
"SDIO1_CARD_POWER_EN")
MUXCTRL(EV20X_12, 0x200f0030, "GPIO0_3", "SPI1_CSN1", "VO_DATA0")
MUXCTRL(EV20X_13, 0x200f0034, "GPIO3_0", "EPHY_CLK", "VO_DATA1", "SDIO1_CDATA2")
MUXCTRL(EV20X_14, 0x200f0038, "GPIO3_1", "MDCK", "BOOTROM_SEL", "VO_DATA6")
MUXCTRL(EV20X_15, 0x200f003c, "GPIO3_2", "MDIO", "VO_DATA4")
MUXCTRL(EV20X_16, 0x200f0040, "GPIO3_3", "SPI0_SCLK", "I2C0_SCL")
MUXCTRL(EV20X_17, 0x200f0044, "GPIO3_4", "SPI0_SDO", "I2C0_SDA")
MUXCTRL(EV20X_18, 0x200f0048, "GPIO3_5", "SPI0_SDI")
MUXCTRL(EV20X_19, 0x200f004c, "GPIO3_6", "SPI0_CSN")
MUXCTRL(EV20X_20, 0x200f0050, "GPIO3_7", "SPI1_SCLK", "I2C1_SCL")
MUXCTRL(EV20X_21, 0x200f0054, "GPIO4_0", "SPI1_SDO", "I2C1_SDA")
MUXCTRL(EV20X_22, 0x200f0058, "GPIO4_1", "SPI1_SDI")
MUXCTRL(EV20X_23, 0x200f005c, "GPIO4_2", "SPI1_CSN0")
MUXCTRL(EV20X_24, 0x200f0060, "GPIO4_3", "I2C2_SDA")
MUXCTRL(EV20X_25, 0x200f0064, "GPIO4_4", "I2C2_SCL")
MUXCTRL(EV20X_26, 0x200f0068, "GPIO4_5", "USB_OVRCUR")
MUXCTRL(EV20X_27, 0x200f006c, "GPIO4_6", "USB_PWREN")
MUXCTRL(EV20X_28, 0x200f0070, "GPIO0_0", "IR_IN", "TEMPER_DQ")
MUXCTRL(EV20X_29, 0x200f0074, "GPIO0_1", "TEMPER_DQ")
MUXCTRL(EV20X_30, 0x200f0078, "GPIO0_2", "TEMPER_DQ")
MUXCTRL(EV20X_31, 0x200f007c, "GPIO1_0", "VI_DATA13", "I2S_BCLK_TX", "PWM0")
MUXCTRL(EV20X_32, 0x200f0080, "GPIO1_1", "VI_DATA10", "I2S_SD_TX", "UART1_TXD")
MUXCTRL(EV20X_33, 0x200f0084, "GPIO1_2", "VI_DATA12", "I2S_MCLK", "UART1_CTSN")
MUXCTRL(EV20X_34, 0x200f0088, "GPIO1_3", "VI_DATA11", "I2S_WS_TX", "UART2_RXD")
MUXCTRL(EV20X_35, 0x200f008c, "GPIO1_4", "VI_DATA15", "VI_VS_SEN", "I2S_WS_RX",
"UART1_RXD")
MUXCTRL(EV20X_36, 0x200f0090, "GPIO1_5", "VI_DATA14", "VI_HS_SEN",
"I2S_BCLK_RX", "UART1_RTSN")
MUXCTRL(EV20X_37, 0x200f0094, "GPIO1_6", "VI_DATA9", "I2S_SD_RX", "UART2_TXD")
MUXCTRL(EV20X_38, 0x200f0098, "GPIO1_7", "SDIO0_CARD_POWER_EN")
MUXCTRL(EV20X_39, 0x200f009c, "GPIO4_7", "SDIO0_CARD_DETECT")
MUXCTRL(EV20X_40, 0x200f00a0, "GPIO5_0", "SDIO0_CWPR")
MUXCTRL(EV20X_41, 0x200f00a4, "GPIO5_1", "SDIO0_CCLK_OUT")
MUXCTRL(EV20X_42, 0x200f00a8, "GPIO5_2", "SDIO0_CCMD")
MUXCTRL(EV20X_43, 0x200f00ac, "GPIO5_3", "SDIO0_CDATA0")
MUXCTRL(EV20X_44, 0x200f00b0, "TEST_CLK", "SDIO0_CDATA1", "GPIO5_4")
MUXCTRL(EV20X_45, 0x200f00b4, "GPIO5_5", "SDIO0_CDATA2")
MUXCTRL(EV20X_46, 0x200f00b8, "GPIO5_6", "SDIO0_CDATA3")
MUXCTRL(EV20X_47, 0x200f00bc, "GPIO5_7", "EMMC_DATA6", "I2S_SD_TX",
"UART1_RTSN")
MUXCTRL(EV20X_48, 0x200f00c0, "GPIO6_0", "EMMC_DATA5", "I2S_WS_TX", "UART1_RXD")
MUXCTRL(EV20X_49, 0x200f00c4, "GPIO6_1", "EMMC_DATA7", "I2S_MCLK", "UART1_CTSN")
MUXCTRL(EV20X_50, 0x200f00c8, "GPIO6_2", "EMMC_DS", "I2S_SD_RX", "UART1_TXD")
MUXCTRL(EV20X_51, 0x200f00cc, "GPIO6_3", "EMMC_DATA1", "UART2_RXD")
MUXCTRL(EV20X_52, 0x200f00d0, "GPIO6_4", "EMMC_DATA2", "I2S_BCLK_TX",
"UART2_TXD")
MUXCTRL(EV20X_53, 0x200f00d4, "GPIO6_5", "JTAG_TRSTN", "SPI1_CSN1", "I2S_MCLK")
MUXCTRL(EV20X_54, 0x200f00d8, "GPIO6_6", "JTAG_TCK", "SPI1_SCLK", "I2S_WS_TX",
"I2C1_SCL")
MUXCTRL(EV20X_55, 0x200f00dc, "GPIO6_7", "JTAG_TMS", "SPI1_CSN0", "I2S_SD_TX")
MUXCTRL(EV20X_56, 0x200f00e0, "GPIO7_0", "JTAG_TDO", "SPI1_SDO", "I2S_SD_RX",
"I2C1_SDA")
MUXCTRL(EV20X_57, 0x200f00e4, "GPIO7_1", "JTAG_TDI", "SPI1_SDI", "I2S_BCLK_TX")
MUXCTRL(EV20X_58, 0x200f00e8, "PMC_PWM", "GPIO7_2", "PWM0")
MUXCTRL(EV20X_59, 0x200f00ec, "PWM1", "GPIO7_3")
MUXCTRL(EV20X_60, 0x200f00f0, "PWM2", "GPIO7_4", "SPI1_CSN1")
MUXCTRL(EV20X_61, 0x200f00f4, "PWM3", "GPIO7_5")
MUXCTRL(EV20X_62, 0x200f00f8, "SAR_ADC_CH0", "GPIO7_6")
MUXCTRL(EV20X_63, 0x200f00fc, "SAR_ADC_CH1", "GPIO7_7")
MUXCTRL(EV20X_64, 0x200f0100, "SAR_ADC_CH2", "GPIO8_0")
MUXCTRL(EV20X_65, 0x200f0104, "SAR_ADC_CH3", "GPIO8_1")
static const muxctrl_reg_t *EV20Xregs[] = {
&EV20X_0, &EV20X_1, &EV20X_2, &EV20X_3, &EV20X_4, &EV20X_5, &EV20X_6,
&EV20X_7, &EV20X_8, &EV20X_9, &EV20X_10, &EV20X_11, &EV20X_12, &EV20X_13,
&EV20X_14, &EV20X_15, &EV20X_16, &EV20X_17, &EV20X_18, &EV20X_19, &EV20X_20,
&EV20X_21, &EV20X_22, &EV20X_23, &EV20X_24, &EV20X_25, &EV20X_26, &EV20X_27,
&EV20X_28, &EV20X_29, &EV20X_30, &EV20X_31, &EV20X_32, &EV20X_33, &EV20X_34,
&EV20X_35, &EV20X_36, &EV20X_37, &EV20X_38, &EV20X_39, &EV20X_40, &EV20X_41,
&EV20X_42, &EV20X_43, &EV20X_44, &EV20X_45, &EV20X_46, &EV20X_47, &EV20X_48,
&EV20X_49, &EV20X_50, &EV20X_51, &EV20X_52, &EV20X_53, &EV20X_54, &EV20X_55,
&EV20X_56, &EV20X_57, &EV20X_58, &EV20X_59, &EV20X_60, &EV20X_61, &EV20X_62,
&EV20X_63, &EV20X_64, &EV20X_65, 0,
};
MUXCTRL(AV200_muxctrl_reg0, 0x12040000, "GPIO1_0", "FLASH_TRIG", "SPI2_CSN1",
"PWM4")
MUXCTRL(AV200_muxctrl_reg1, 0x12040004, "GPIO1_1", "SHUTTER_TRIG", "reserved",
"PWM5")
MUXCTRL(AV200_muxctrl_reg2, 0x12040008, "GPIO0_0", "SENSOR1_CLK")
MUXCTRL(AV200_muxctrl_reg3, 0x1204000C, "SENSOR1_RSTN", "GPIO0_1")
MUXCTRL(AV200_muxctrl_reg4, 0x12040010, "GPIO0_2", "SENSOR0_HS", "SENSOR1_HS")
MUXCTRL(AV200_muxctrl_reg5, 0x12040014, "GPIO0_3", "SENSOR0_VS", "SENSOR1_VS")
MUXCTRL(AV200_muxctrl_reg6, 0x12040018, "GPIO0_4", "SPI1_SCLK", "I2C1_SCL",
"SPI1_3WIRE_CLK")
MUXCTRL(AV200_muxctrl_reg7, 0x1204001C, "GPIO0_5", "SPI1_SDO", "I2C1_SDA",
"SPI1_3WIRE_DATA")
MUXCTRL(AV200_muxctrl_reg8, 0x12040020, "GPIO0_6", "SPI1_SDI")
MUXCTRL(AV200_muxctrl_reg9, 0x12040024, "GPIO0_7", "SPI1_CSN", "reserved",
"SPI1_3WIRE_CSN")
MUXCTRL(AV200_muxctrl_reg10, 0x12040028, "GPIO3_0", "VI1_HS")
MUXCTRL(AV200_muxctrl_reg11, 0x1204002C, "GPIO2_0", "VI1_VS")
MUXCTRL(AV200_muxctrl_reg12, 0x12040030, "GPIO2_1", "VI1_CLK")
MUXCTRL(AV200_muxctrl_reg13, 0x12040034, "GPIO2_2", "VI1_DATA0")
MUXCTRL(AV200_muxctrl_reg14, 0x12040038, "GPIO2_3", "VI1_DATA1")
MUXCTRL(AV200_muxctrl_reg15, 0x1204003C, "GPIO2_4", "VI1_DATA2")
MUXCTRL(AV200_muxctrl_reg16, 0x12040040, "GPIO2_5", "VI1_DATA3")
MUXCTRL(AV200_muxctrl_reg17, 0x12040044, "GPIO2_6", "VI1_DATA4")
MUXCTRL(AV200_muxctrl_reg18, 0x12040048, "GPIO2_7", "VI1_DATA5")
MUXCTRL(AV200_muxctrl_reg19, 0x1204004C, "GPIO1_2", "SPI2_SCLK", "I2S_BCLK_RX")
MUXCTRL(AV200_muxctrl_reg20, 0x12040050, "GPIO1_3", "SPI2_SDO", "I2S_WS_RX")
MUXCTRL(AV200_muxctrl_reg21, 0x12040054, "GPIO1_4", "SPI2_SDI")
MUXCTRL(AV200_muxctrl_reg22, 0x12040058, "GPIO1_5", "SPI2_CSN0")
MUXCTRL(AV200_muxctrl_reg23, 0x1204005C, "GPIO1_6", "I2C2_SDA")
MUXCTRL(AV200_muxctrl_reg24, 0x12040060, "GPIO1_7", "I2C2_SCL")
MUXCTRL(AV200_muxctrl_reg25, 0x12040064, "GPIO3_1", "JTAG_TRSTN", "I2S_WS_TX",
"PWM4")
MUXCTRL(AV200_muxctrl_reg26, 0x12040068, "GPIO3_2", "JTAG_TCK", "I2S_MCLK",
"PWM5")
MUXCTRL(AV200_muxctrl_reg27, 0x1204006C, "GPIO3_3", "JTAG_TMS", "I2S_BCLK_TX",
"PWM6")
MUXCTRL(AV200_muxctrl_reg28, 0x12040070, "GPIO3_4", "JTAG_TDO", "I2S_SD_TX",
"PWM7")
MUXCTRL(AV200_muxctrl_reg29, 0x12040074, "GPIO3_5", "JTAG_TDI", "I2S_SD_RX",
"IR_IN")
MUXCTRL(AV200_muxctrl_reg30, 0x12040078, "PMC_PWM0", "GPIO3_6", "reserved",
"PWM0")
MUXCTRL(AV200_muxctrl_reg31, 0x1204007C, "PMC_PWM1", "GPIO3_7", "reserved",
"PWM1")
MUXCTRL(AV200_muxctrl_reg32, 0x12040080, "PMC_PWM2", "GPIO4_0", "reserved",
"PWM2")
MUXCTRL(AV200_muxctrl_reg33, 0x12040084, "PMC_PWM3", "GPIO4_1", "reserved",
"PWM3")
MUXCTRL(AV200_muxctrl_reg34, 0x12040088, "GPIO5_0", "UART1_RTSN", "UART3_RXD",
"PWM3")
MUXCTRL(AV200_muxctrl_reg35, 0x1204008C, "GPIO5_1", "UART1_RXD")
MUXCTRL(AV200_muxctrl_reg36, 0x12040090, "GPIO5_2", "UART1_CTSN", "UART3_TXD")
MUXCTRL(AV200_muxctrl_reg37, 0x12040094, "GPIO5_3", "UART1_TXD")
MUXCTRL(AV200_muxctrl_reg38, 0x12040098, "GPIO5_4", "UART2_RXD", "reserved",
"PWM4")
MUXCTRL(AV200_muxctrl_reg39, 0x1204009C, "GPIO5_5", "UART2_TXD", "reserved",
"PWM5")
MUXCTRL(AV200_muxctrl_reg40, 0x120400A0, "GPIO5_6", "UART2_RTSN", "UART4_RXD",
"PWM6", "reserved", "TEMPER_DQ")
MUXCTRL(AV200_muxctrl_reg41, 0x120400A4, "GPIO5_7", "UART2_CTSN", "UART4_TXD",
"PWM7")
MUXCTRL(AV200_muxctrl_reg42, 0x120400A8, "GPIO4_2", "USB3_PWREN",
"PCIE_CLK_REQ_N")
MUXCTRL(AV200_muxctrl_reg43, 0x120400AC, "GPIO4_3", "SDIO0_CARD_POWER_EN")
MUXCTRL(AV200_muxctrl_reg44, 0x120400B0, "GPIO6_0", "SDIO0_CARD_DETECT")
MUXCTRL(AV200_muxctrl_reg45, 0x120400B4, "GPIO6_1", "SDIO0_CWPR")
MUXCTRL(AV200_muxctrl_reg46, 0x120400B8, "GPIO6_2", "SDIO0_CCLK_OUT")
MUXCTRL(AV200_muxctrl_reg47, 0x120400BC, "GPIO6_3", "SDIO0_CCMD")
MUXCTRL(AV200_muxctrl_reg48, 0x120400C0, "GPIO6_4", "SDIO0_CDATA0")
MUXCTRL(AV200_muxctrl_reg49, 0x120400C4, "TEST_CLK", "SDIO0_CDATA1", "GPIO6_5")
MUXCTRL(AV200_muxctrl_reg50, 0x120400C8, "GPIO6_6", "SDIO0_CDATA2")
MUXCTRL(AV200_muxctrl_reg51, 0x120400CC, "GPIO6_7", "SDIO0_CDATA3")
MUXCTRL(AV200_muxctrl_reg52, 0x120400D0, "GPIO4_4", "SDIO1_CARD_POWER_EN")
MUXCTRL(AV200_muxctrl_reg53, 0x120400D4, "GPIO7_0", "SDIO1_CARD_DETECT")
MUXCTRL(AV200_muxctrl_reg54, 0x120400D8, "GPIO7_1", "SDIO1_CWPR")
MUXCTRL(AV200_muxctrl_reg55, 0x120400DC, "GPIO7_2", "SDIO1_CCLK_OUT")
MUXCTRL(AV200_muxctrl_reg56, 0x120400E0, "GPIO7_3", "SDIO1_CCMD")
MUXCTRL(AV200_muxctrl_reg57, 0x120400E4, "GPIO7_4", "SDIO1_CDATA0")
MUXCTRL(AV200_muxctrl_reg58, 0x120400E8, "GPIO7_5", "SDIO1_CDATA1")
MUXCTRL(AV200_muxctrl_reg59, 0x120400EC, "GPIO7_6", "SDIO1_CDATA2")
MUXCTRL(AV200_muxctrl_reg60, 0x120400F0, "GPIO7_7", "SDIO1_CDATA3")
MUXCTRL(AV200_muxctrl_reg61, 0x120400F4, "GPIO4_5", "USB2_PWREN")
MUXCTRL(AV200_muxctrl_reg62, 0x120400F8, "GPIO4_6", "VO_CLK")
MUXCTRL(AV200_muxctrl_reg63, 0x120400FC, "GPIO8_0", "VO_DATA0")
MUXCTRL(AV200_muxctrl_reg64, 0x12040100, "GPIO8_1", "VO_DATA1")
MUXCTRL(AV200_muxctrl_reg65, 0x12040104, "GPIO8_2", "VO_DATA2")
MUXCTRL(AV200_muxctrl_reg66, 0x12040108, "GPIO8_3", "VO_DATA3")
MUXCTRL(AV200_muxctrl_reg67, 0x1204010C, "GPIO8_4", "VO_DATA4")
MUXCTRL(AV200_muxctrl_reg68, 0x12040110, "GPIO8_5", "VO_DATA5")
MUXCTRL(AV200_muxctrl_reg69, 0x12040114, "GPIO8_6", "VO_DATA6")
MUXCTRL(AV200_muxctrl_reg70, 0x12040118, "GPIO8_7", "VO_DATA7")
MUXCTRL(AV200_muxctrl_reg71, 0x1204011C, "GPIO9_0", "VO_DATA8")
MUXCTRL(AV200_muxctrl_reg72, 0x12040120, "GPIO9_1", "VO_DATA9", "reserved",
"VO_VS")
MUXCTRL(AV200_muxctrl_reg73, 0x12040124, "GPIO9_2", "VO_DATA10", "reserved",
"VO_HS")
MUXCTRL(AV200_muxctrl_reg74, 0x12040128, "GPIO9_3", "VO_DATA11", "reserved",
"VO_DE")
MUXCTRL(AV200_muxctrl_reg75, 0x1204012C, "GPIO9_4", "VO_DATA12", "SPI3_SCLK",
"I2C3_SCL")
MUXCTRL(AV200_muxctrl_reg76, 0x12040130, "GPIO9_5", "VO_DATA13", "SPI3_SDO",
"I2C3_SDA")
MUXCTRL(AV200_muxctrl_reg77, 0x12040134, "GPIO9_6", "VO_DATA14", "SPI3_SDI")
MUXCTRL(AV200_muxctrl_reg78, 0x12040138, "GPIO9_7", "VO_DATA15", "SPI3_CSN")
MUXCTRL(AV200_muxctrl_reg79, 0x1204013C, "GPIO10_0", "VO_VS", "RGMII_TX_EN")
MUXCTRL(AV200_muxctrl_reg80, 0x12040140, "GPIO10_1", "VO_DATA18",
"RGMII_TX_CLK", "RMII_CLK")
MUXCTRL(AV200_muxctrl_reg81, 0x12040144, "GPIO10_2", "VO_DATA16", "RGMII_TXD0")
MUXCTRL(AV200_muxctrl_reg82, 0x12040148, "GPIO10_3", "VO_DATA20", "RGMII_TXD1")
MUXCTRL(AV200_muxctrl_reg83, 0x1204014C, "GPIO10_4", "VO_DATA17", "RGMII_TXD2")
MUXCTRL(AV200_muxctrl_reg84, 0x12040150, "GPIO10_5", "VO_HS", "RGMII_TXD3")
MUXCTRL(AV200_muxctrl_reg85, 0x12040154, "GPIO10_6", "VO_DATA19",
"RGMII_RX_CLK")
MUXCTRL(AV200_muxctrl_reg86, 0x12040158, "GPIO10_7", "VO_DATA23", "RGMII_RX_DV")
MUXCTRL(AV200_muxctrl_reg87, 0x1204015C, "GPIO11_0", "VO_DATA22", "RGMII_RXD0")
MUXCTRL(AV200_muxctrl_reg88, 0x12040160, "GPIO11_1", "SPI3_SCLK", "RGMII_RXD1",
"I2C3_SCL")
MUXCTRL(AV200_muxctrl_reg89, 0x12040164, "GPIO11_2", "VO_DE", "RGMII_RXD2")
MUXCTRL(AV200_muxctrl_reg90, 0x12040168, "GPIO11_3", "VO_DATA21", "RGMII_RXD3")
MUXCTRL(AV200_muxctrl_reg91, 0x1204016C, "GPIO11_4", "reserved", "EPHY_RSTN")
MUXCTRL(AV200_muxctrl_reg92, 0x12040170, "GPIO11_5", "SPI3_SDI", "EPHY_CLK")
MUXCTRL(AV200_muxctrl_reg93, 0x12040174, "GPIO11_6", "SPI3_CSN", "MDCK")
MUXCTRL(AV200_muxctrl_reg94, 0x12040178, "GPIO11_7", "SPI3_SDO", "MDIO",
"I2C3_SDA")
MUXCTRL(AV200_muxctrl_reg95, 0x1204017C, "GPIO12_0", "SENSOR0_CLK")
MUXCTRL(AV200_muxctrl_reg96, 0x12040180, "SENSOR0_RSTN", "GPIO12_1")
MUXCTRL(AV200_muxctrl_reg97, 0x12040184, "GPIO12_2", "SENSOR0_HS", "SENSOR1_HS")
MUXCTRL(AV200_muxctrl_reg98, 0x12040188, "GPIO12_3", "SENSOR0_VS", "SENSOR1_VS")
MUXCTRL(AV200_muxctrl_reg99, 0x1204018C, "GPIO12_4", "SPI0_SCLK", "I2C0_SCL",
"SPI0_3WIRE_CLK")
MUXCTRL(AV200_muxctrl_reg100, 0x12040190, "GPIO12_5", "SPI0_SDO", "I2C0_SDA",
"SPI0_3WIRE_DATA")
MUXCTRL(AV200_muxctrl_reg101, 0x12040194, "GPIO12_6", "SPI0_SDI")
MUXCTRL(AV200_muxctrl_reg102, 0x12040198, "GPIO12_7", "SPI0_CSN", "reserved",
"SPI0_3WIRE_CSN")
MUXCTRL(AV200_muxctrl_reg118, 0x120401D8, "SAR_ADC_CH1", "GPIO16_1")
MUXCTRL(AV200_muxctrl_reg119, 0x120401DC, "SAR_ADC_CH2", "GPIO16_2")
MUXCTRL(AV200_muxctrl_reg120, 0x120401E0, "SAR_ADC_CH3", "GPIO16_3", "reserved",
"TEMPER_DQ")
static const muxctrl_reg_t *AV200regs[] = {
&AV200_muxctrl_reg0,
&AV200_muxctrl_reg1,
&AV200_muxctrl_reg2,
&AV200_muxctrl_reg3,
&AV200_muxctrl_reg4,
&AV200_muxctrl_reg5,
&AV200_muxctrl_reg6,
&AV200_muxctrl_reg7,
&AV200_muxctrl_reg8,
&AV200_muxctrl_reg9,
&AV200_muxctrl_reg10,
&AV200_muxctrl_reg11,
&AV200_muxctrl_reg12,
&AV200_muxctrl_reg13,
&AV200_muxctrl_reg14,
&AV200_muxctrl_reg15,
&AV200_muxctrl_reg16,
&AV200_muxctrl_reg17,
&AV200_muxctrl_reg18,
&AV200_muxctrl_reg19,
&AV200_muxctrl_reg20,
&AV200_muxctrl_reg21,
&AV200_muxctrl_reg22,
&AV200_muxctrl_reg23,
&AV200_muxctrl_reg24,
&AV200_muxctrl_reg25,
&AV200_muxctrl_reg26,
&AV200_muxctrl_reg27,
&AV200_muxctrl_reg28,
&AV200_muxctrl_reg29,
&AV200_muxctrl_reg30,
&AV200_muxctrl_reg31,
&AV200_muxctrl_reg32,
&AV200_muxctrl_reg33,
&AV200_muxctrl_reg34,
&AV200_muxctrl_reg35,
&AV200_muxctrl_reg36,
&AV200_muxctrl_reg37,
&AV200_muxctrl_reg38,
&AV200_muxctrl_reg39,
&AV200_muxctrl_reg40,
&AV200_muxctrl_reg41,
&AV200_muxctrl_reg42,
&AV200_muxctrl_reg43,
&AV200_muxctrl_reg44,
&AV200_muxctrl_reg45,
&AV200_muxctrl_reg46,
&AV200_muxctrl_reg47,
&AV200_muxctrl_reg48,
&AV200_muxctrl_reg49,
&AV200_muxctrl_reg50,
&AV200_muxctrl_reg51,
&AV200_muxctrl_reg52,
&AV200_muxctrl_reg53,
&AV200_muxctrl_reg54,
&AV200_muxctrl_reg55,
&AV200_muxctrl_reg56,
&AV200_muxctrl_reg57,
&AV200_muxctrl_reg58,
&AV200_muxctrl_reg59,
&AV200_muxctrl_reg60,
&AV200_muxctrl_reg61,
&AV200_muxctrl_reg62,
&AV200_muxctrl_reg63,
&AV200_muxctrl_reg64,
&AV200_muxctrl_reg65,
&AV200_muxctrl_reg66,
&AV200_muxctrl_reg67,
&AV200_muxctrl_reg68,
&AV200_muxctrl_reg69,
&AV200_muxctrl_reg70,
&AV200_muxctrl_reg71,
&AV200_muxctrl_reg72,
&AV200_muxctrl_reg73,
&AV200_muxctrl_reg74,
&AV200_muxctrl_reg75,
&AV200_muxctrl_reg76,
&AV200_muxctrl_reg77,
&AV200_muxctrl_reg78,
&AV200_muxctrl_reg79,
&AV200_muxctrl_reg80,
&AV200_muxctrl_reg81,
&AV200_muxctrl_reg82,
&AV200_muxctrl_reg83,
&AV200_muxctrl_reg84,
&AV200_muxctrl_reg85,
&AV200_muxctrl_reg86,
&AV200_muxctrl_reg87,
&AV200_muxctrl_reg88,
&AV200_muxctrl_reg89,
&AV200_muxctrl_reg90,
&AV200_muxctrl_reg91,
&AV200_muxctrl_reg92,
&AV200_muxctrl_reg93,
&AV200_muxctrl_reg94,
&AV200_muxctrl_reg95,
&AV200_muxctrl_reg96,
&AV200_muxctrl_reg97,
&AV200_muxctrl_reg98,
&AV200_muxctrl_reg99,
&AV200_muxctrl_reg100,
&AV200_muxctrl_reg101,
&AV200_muxctrl_reg102,
&AV200_muxctrl_reg118,
&AV200_muxctrl_reg119,
&AV200_muxctrl_reg120,
0,
};
MUXCTRL(CV300_muxctrl_reg0, 0x12040000, "GPIO1_7", "PWM3", "SVB_PWM")
MUXCTRL(CV300_muxctrl_reg1, 0x12040004, "GPIO6_5", "PWM0")
MUXCTRL(CV300_muxctrl_reg2, 0x12040008, "GPIO6_6", "PWM1")
MUXCTRL(CV300_muxctrl_reg3, 0x1204000C, "GPIO6_7", "PWM2")
MUXCTRL(CV300_muxctrl_reg4, 0x12040010, "GPIO6_2", "UART0_RXD")
MUXCTRL(CV300_muxctrl_reg5, 0x12040014, "GPIO6_3", "UART0_TXD")
MUXCTRL(CV300_muxctrl_reg6, 0x12040018, "GPIO6_1", "SHUTTER_TRIG")
MUXCTRL(CV300_muxctrl_reg7, 0x1204001C, "GPIO6_0", "FLASH_TRIG")
MUXCTRL(CV300_muxctrl_reg8, 0x12040020, "GPIO3_6", "I2C1_SDA")
MUXCTRL(CV300_muxctrl_reg9, 0x12040024, "GPIO3_7", "I2C1_SCL")
MUXCTRL(CV300_muxctrl_reg10, 0x12040028, "GPIO0_5", "SPI0_SDI")
MUXCTRL(CV300_muxctrl_reg11, 0x1204002C, "GPIO0_4", "SPI0_SDO",
"SPI_3LINE_SDATA", "I2C0_SDA")
MUXCTRL(CV300_muxctrl_reg12, 0x12040030, "GPIO8_3", "SPI0_SCLK",
"SPI_3LINE_SCLK", "I2C0_SCL")
MUXCTRL(CV300_muxctrl_reg13, 0x12040034, "GPIO0_6", "SPI0_CSN", "SPI_3LINE_CSN")
MUXCTRL(CV300_muxctrl_reg14, 0x12040038, "GPIO0_7", "SENSOR_RSTN")
MUXCTRL(CV300_muxctrl_reg15, 0x1204003C, "GPIO6_4", "SENSOR_CLK")
MUXCTRL(CV300_muxctrl_reg16, 0x12040040, "GPIO1_0", "VI_DATA13", "VOU656_CLK",
"LCD_CLK", "I2S_MCLK", "SDIO2_CCLK_OUT")
MUXCTRL(CV300_muxctrl_reg17, 0x12040044, "GPIO1_1", "VI_DATA10", "VOU656_DATA3",
"LCD_DATA1", "I2S_SD_TX", "SDIO2_CDATA3")
MUXCTRL(CV300_muxctrl_reg18, 0x12040048, "GPIO1_2", "VI_DATA12", "VOU656_DATA7",
"LCD_DATA3", "I2S_BCLK_TX", "SDIO2_CDATA1")
MUXCTRL(CV300_muxctrl_reg19, 0x1204004C, "GPIO1_3", "VI_DATA11", "VOU656_DATA2",
"LCD_DATA2", "I2S_WS_TX", "SDIO2_CDATA2")
MUXCTRL(CV300_muxctrl_reg20, 0x12040050, "GPIO1_4", "VI_DATA9", "VOU656_DATA6",
"LCD_DATA4")
MUXCTRL(CV300_muxctrl_reg21, 0x12040054, "GPIO1_5", "VI_DATA14", "VOU656_DATA5",
"LCD_DATA5", "reserved", "SDIO2_CDATA0")
MUXCTRL(CV300_muxctrl_reg22, 0x12040058, "GPIO1_6", "VI_DATA15", "VOU656_DATA4",
"LCD_DATA0", "I2S_SD_RX", "SDIO2_CCMD")
MUXCTRL(CV300_muxctrl_reg23, 0x1204005C, "GPIO3_4", "VI_VS", "VOU656_DATA1",
"LCD_HSYNC", "UART2_RXD")
MUXCTRL(CV300_muxctrl_reg24, 0x12040060, "GPIO3_5", "VI_HS", "VOU656_DATA0",
"LCD_VSYNC", "UART2_TXD")
MUXCTRL(CV300_muxctrl_reg25, 0x12040064, "GPIO7_7", "USB_PWREN", "reserved",
"LCD_DE")
MUXCTRL(CV300_muxctrl_reg26, 0x12040068, "GPIO4_1", "SDIO0_CARD_DETECT")
MUXCTRL(CV300_muxctrl_reg27, 0x1204006C, "GPIO4_0", "SDIO0_CARD_POWER_EN",
"JTAG_TCK")
MUXCTRL(CV300_muxctrl_reg28, 0x12040070, "GPIO4_4", "SDIO0_CDATA0")
MUXCTRL(CV300_muxctrl_reg29, 0x12040074, "GPIO4_5", "SDIO0_CDATA1", "JTAG_TMS")
MUXCTRL(CV300_muxctrl_reg30, 0x12040078, "GPIO4_3", "SDIO0_CCMD")
MUXCTRL(CV300_muxctrl_reg31, 0x1204007C, "GPIO4_2", "SDIO0_CCLK_OUT",
"JTAG_TRSTN")
MUXCTRL(CV300_muxctrl_reg32, 0x12040080, "GPIO4_7", "SDIO0_CDATA3", "JTAG_TDI")
MUXCTRL(CV300_muxctrl_reg33, 0x12040084, "GPIO4_6", "SDIO0_CDATA2", "JTAG_TDO")
MUXCTRL(CV300_muxctrl_reg34, 0x12040088, "GPIO3_3", "UART1_TXD")
MUXCTRL(CV300_muxctrl_reg35, 0x1204008C, "GPIO3_2", "UART1_CTSN")
MUXCTRL(CV300_muxctrl_reg36, 0x12040090, "GPIO3_1", "UART1_RXD")
MUXCTRL(CV300_muxctrl_reg37, 0x12040094, "GPIO3_0", "UART1_RTSN")
MUXCTRL(CV300_muxctrl_reg38, 0x12040098, "GPIO2_5", "RMII_RXD0", "SDIO1_CDATA2",
"LCD_HSYNC")
MUXCTRL(CV300_muxctrl_reg39, 0x1204009C, "GPIO2_4", "RMII_RX_DV",
"SDIO1_CARD_POWER_EN", "LCD_DATA0")
MUXCTRL(CV300_muxctrl_reg40, 0x120400A0, "GPIO2_6", "RMII_RXD1", "SDIO1_CCMD",
"LCD_DATA5")
MUXCTRL(CV300_muxctrl_reg41, 0x120400A4, "GPIO5_6", "MDCK")
MUXCTRL(CV300_muxctrl_reg42, 0x120400A8, "GPIO5_7", "MDIO", "SDIO1_CARD_DETECT",
"LCD_DATA1")
MUXCTRL(CV300_muxctrl_reg43, 0x120400AC, "GPIO2_3", "RMII_TXD1", "SDIO1_CDATA1",
"LCD_DATA2")
MUXCTRL(CV300_muxctrl_reg44, 0x120400B0, "GPIO2_2", "RMII_TXD0", "SDIO1_CDATA0",
"LCD_DATA3", "TEST_CLK")
MUXCTRL(CV300_muxctrl_reg45, 0x120400B4, "GPIO2_1", "RMII_TX_EN",
"SDIO1_CDATA3", "LCD_DATA4")
MUXCTRL(CV300_muxctrl_reg46, 0x120400B8, "GPIO2_0", "RMII_CLK",
"SDIO1_CCLK_OUT", "LCD_CLK")
MUXCTRL(CV300_muxctrl_reg47, 0x120400BC, "GPIO5_5", "EPHY_CLK", "reserved",
"LCD_VSYNC")
MUXCTRL(CV300_muxctrl_reg48, 0x120400C0, "GPIO2_7", "EPHY_RSTN", "reserved",
"LCD_DE")
MUXCTRL(CV300_muxctrl_reg49, 0x120400C4, "GPIO5_4", "SPI1_CSN1", "UART2_RXD",
"JTAG_TDI", "I2S_SD_TX")
MUXCTRL(CV300_muxctrl_reg50, 0x120400C8, "GPIO5_3", "SPI1_CSN0", "UART2_TXD",
"JTAG_TMS", "I2S_WS_TX")
MUXCTRL(CV300_muxctrl_reg51, 0x120400CC, "GPIO5_1", "SPI1_SDO", "reserved",
"JTAG_TCK", "I2S_BCLK_TX")
MUXCTRL(CV300_muxctrl_reg52, 0x120400D0, "GPIO5_2", "SPI1_SDI", "reserved",
"JTAG_TDO", "I2S_MCLK")
MUXCTRL(CV300_muxctrl_reg53, 0x120400D4, "GPIO5_0", "SPI1_SCLK", "reserved",
"JTAG_TRSTN", "I2S_SD_RX")
MUXCTRL(CV300_muxctrl_reg55, 0x120400DC, "PWR_WAKEUP", "GPIO7_1")
MUXCTRL(CV300_muxctrl_reg56, 0x120400E0, "PWR_SEQ0", "GPIO7_2")
MUXCTRL(CV300_muxctrl_reg57, 0x120400E4, "PWR_SEQ1", "GPIO7_3")
MUXCTRL(CV300_muxctrl_reg58, 0x120400E8, "PWR_SEQ2", "GPIO7_4")
MUXCTRL(CV300_muxctrl_reg59, 0x120400EC, "PWR_EN_OUT", "GPIO7_5")
MUXCTRL(CV300_muxctrl_reg60, 0x120400F0, "PWR_BUTTON", "GPIO7_6")
MUXCTRL(CV300_muxctrl_reg61, 0x120400F4, "GPIO0_0", "IR_IN")
MUXCTRL(CV300_muxctrl_reg62, 0x120400F8, "GPIO0_1", "TEMPER_DQ")
MUXCTRL(CV300_muxctrl_reg63, 0x120400FC, "GPIO8_0", "SAR_ADC_CH0")
MUXCTRL(CV300_muxctrl_reg64, 0x12040100, "GPIO8_1", "SAR_ADC_CH1")
MUXCTRL(CV300_muxctrl_reg65, 0x12040104, "GPIO8_2", "SAR_ADC_CH2")
static const muxctrl_reg_t *CV300regs[] = {
&CV300_muxctrl_reg0, &CV300_muxctrl_reg1, &CV300_muxctrl_reg2,
&CV300_muxctrl_reg3, &CV300_muxctrl_reg4, &CV300_muxctrl_reg5,
&CV300_muxctrl_reg6, &CV300_muxctrl_reg7, &CV300_muxctrl_reg8,
&CV300_muxctrl_reg9, &CV300_muxctrl_reg10, &CV300_muxctrl_reg11,
&CV300_muxctrl_reg12, &CV300_muxctrl_reg13, &CV300_muxctrl_reg14,
&CV300_muxctrl_reg15, &CV300_muxctrl_reg16, &CV300_muxctrl_reg17,
&CV300_muxctrl_reg18, &CV300_muxctrl_reg19, &CV300_muxctrl_reg20,
&CV300_muxctrl_reg21, &CV300_muxctrl_reg22, &CV300_muxctrl_reg23,
&CV300_muxctrl_reg24, &CV300_muxctrl_reg25, &CV300_muxctrl_reg26,
&CV300_muxctrl_reg27, &CV300_muxctrl_reg28, &CV300_muxctrl_reg29,
&CV300_muxctrl_reg30, &CV300_muxctrl_reg31, &CV300_muxctrl_reg32,
&CV300_muxctrl_reg33, &CV300_muxctrl_reg34, &CV300_muxctrl_reg35,
&CV300_muxctrl_reg36, &CV300_muxctrl_reg37, &CV300_muxctrl_reg38,
&CV300_muxctrl_reg39, &CV300_muxctrl_reg40, &CV300_muxctrl_reg41,
&CV300_muxctrl_reg42, &CV300_muxctrl_reg43, &CV300_muxctrl_reg44,
&CV300_muxctrl_reg45, &CV300_muxctrl_reg46, &CV300_muxctrl_reg47,
&CV300_muxctrl_reg48, &CV300_muxctrl_reg49, &CV300_muxctrl_reg50,
&CV300_muxctrl_reg51, &CV300_muxctrl_reg52, &CV300_muxctrl_reg53,
&CV300_muxctrl_reg55, &CV300_muxctrl_reg56, &CV300_muxctrl_reg57,
&CV300_muxctrl_reg58, &CV300_muxctrl_reg59, &CV300_muxctrl_reg60,
&CV300_muxctrl_reg61, &CV300_muxctrl_reg62, &CV300_muxctrl_reg63,
&CV300_muxctrl_reg64, &CV300_muxctrl_reg65, 0,
};
MUXCTRL(CV500_iocfg_reg0, 0x10FF0000, "EMMC_CLK", "SFC_CLK", "SFC_BOOT_MODE")
MUXCTRL(CV500_iocfg_reg1, 0x10FF0004, "EMMC_CMD", "SFC_HOLD_IO3")
MUXCTRL(CV500_iocfg_reg2, 0x10FF0008, "EMMC_DATA0", "SFC_WP_IO2")
MUXCTRL(CV500_iocfg_reg3, 0x10FF000C, "EMMC_DATA1", "SFC_MISO_IO1")
MUXCTRL(CV500_iocfg_reg4, 0x10FF0010, "EMMC_DATA2", "SFC_CSN", "GPIO0_7")
MUXCTRL(CV500_iocfg_reg5, 0x10FF0014, "EMMC_DATA3", "SFC_MOSI_IO0")
MUXCTRL(CV500_iocfg_reg6, 0x10FF0018, "EMMC_RST_N", "SYS_RSTN_OUT", "GPIO10_5")
MUXCTRL(CV500_iocfg_reg7, 0x10FF001C, "GPIO1_0", "SDIO0_CARD_POWER_EN",
"JTAG_TCK", "USBPHY_TEST_OBS0")
MUXCTRL(CV500_iocfg_reg8, 0x10FF0020, "GPIO1_1", "SDIO0_CARD_DETECT",
"reserved", "USBPHY_TEST_OBS1")
MUXCTRL(CV500_iocfg_reg9, 0x10FF0024, "GPIO1_2", "SDIO0_CCLK_OUT", "JTAG_TRSTN",
"USBPHY_TEST_OBS2")
MUXCTRL(CV500_iocfg_reg10, 0x10FF0028, "GPIO1_3", "SDIO0_CCMD", "reserved",
"USBPHY_TEST_OBS3")
MUXCTRL(CV500_iocfg_reg11, 0x10FF002C, "GPIO1_4", "SDIO0_CDATA0", "reserved",
"USBPHY_TEST_OBS4")
MUXCTRL(CV500_iocfg_reg12, 0x10FF0030, "GPIO1_5", "SDIO0_CDATA1", "JTAG_TMS",
"USBPHY_TEST_OBS5")
MUXCTRL(CV500_iocfg_reg13, 0x10FF0034, "GPIO1_6", "SDIO0_CDATA2", "JTAG_TDO",
"USBPHY_TEST_OBS6")
MUXCTRL(CV500_iocfg_reg14, 0x10FF0038, "GPIO1_7", "SDIO0_CDATA3", "JTAG_TDI",
"USBPHY_TEST_OBS7")
MUXCTRL(CV500_iocfg_reg15, 0x10FF003C, "GPIO2_0", "USB_OVRCUR")
MUXCTRL(CV500_iocfg_reg16, 0x10FF0040, "GPIO2_1", "USB_VBUS")
MUXCTRL(CV500_iocfg_reg17, 0x10FF0044, "GPIO2_2", "USB_PWREN")
MUXCTRL(CV500_iocfg_reg22, 0x114F0010, "reserved", "VI_DATA8")
MUXCTRL(CV500_iocfg_reg23, 0x114F0014, "reserved", "VI_DATA9")
MUXCTRL(CV500_iocfg_reg24, 0x114F0018, "MIPI_RX_D2N", "VI_DATA15")
MUXCTRL(CV500_iocfg_reg25, 0x114F001C, "MIPI_RX_D2P", "VI_DATA14")
MUXCTRL(CV500_iocfg_reg26, 0x114F0020, "MIPI_RX_D3N", "VI_DATA10")
MUXCTRL(CV500_iocfg_reg27, 0x114F0024, "MIPI_RX_D3P", "VI_DATA11")
MUXCTRL(CV500_iocfg_reg28, 0x114F0028, "MIPI_RX_CK0N", "VI_DATA13")
MUXCTRL(CV500_iocfg_reg29, 0x114F002C, "MIPI_RX_CK0P", "VI_DATA12")
MUXCTRL(CV500_iocfg_reg30, 0x114F0030, "MIPI_RX_D0N")
MUXCTRL(CV500_iocfg_reg31, 0x114F0034, "MIPI_RX_D0P")
MUXCTRL(CV500_iocfg_reg32, 0x114F0038, "MIPI_RX_D1N")
MUXCTRL(CV500_iocfg_reg33, 0x114F003C, "MIPI_RX_D1P")
MUXCTRL(CV500_iocfg_reg34, 0x114F0040, "GPIO3_0", "VI_DATA0", "VOU656_DATA0",
"I2C5_SCL")
MUXCTRL(CV500_iocfg_reg35, 0x114F0044, "GPIO3_1", "VI_DATA1", "VOU656_DATA1",
"I2C5_SDA")
MUXCTRL(CV500_iocfg_reg36, 0x114F0048, "GPIO3_2", "VI_DATA2", "VOU656_DATA2",
"I2C6_SCL")
MUXCTRL(CV500_iocfg_reg37, 0x114F004C, "GPIO3_3", "VI_DATA3", "VOU656_DATA3",
"I2C6_SDA")
MUXCTRL(CV500_iocfg_reg38, 0x114F0050, "GPIO3_4", "VI_DATA4", "VOU656_DATA4",
"UART2_RTSN", "SPI2_SCLK")
MUXCTRL(CV500_iocfg_reg39, 0x114F0054, "GPIO3_5", "VI_DATA5", "VOU656_DATA5",
"UART2_CTSN", "SPI2_SDO")
MUXCTRL(CV500_iocfg_reg40, 0x114F0058, "GPIO3_6", "VI_DATA6", "VOU656_DATA6",
"UART2_RXD", "SPI2_SDI")
MUXCTRL(CV500_iocfg_reg41, 0x114F005C, "GPIO3_7", "VI_DATA7", "VOU656_DATA7",
"UART2_TXD", "SPI2_CSN")
MUXCTRL(CV500_iocfg_reg42, 0x114F0060, "GPIO4_6", "VI_VS", "reserved",
"FLASH_TRIG", "SENSOR_VS")
MUXCTRL(CV500_iocfg_reg43, 0x114F0064, "GPIO4_7", "VI_HS", "reserved",
"SHUTTER_TRIG", "SENSOR_HS")
MUXCTRL(CV500_iocfg_reg44, 0x114F0068, "GPIO2_3", "VI_CLK", "VOU656_CLK")
MUXCTRL(CV500_iocfg_reg45, 0x114F006C, "GPIO4_0", "SENSOR0_CLK")
MUXCTRL(CV500_iocfg_reg46, 0x114F0070, "GPIO4_1", "SENSOR0_RSTN", "BOOT_SEL1")
MUXCTRL(CV500_iocfg_reg47, 0x114F0074, "GPIO4_2", "SPI0_SCLK", "I2C0_SCL",
"SPI_3LINE_SCLK")
MUXCTRL(CV500_iocfg_reg48, 0x114F0078, "GPIO4_3", "SPI0_SDO", "I2C0_SDA",
"SPI_3LINE_SDATA")
MUXCTRL(CV500_iocfg_reg49, 0x114F007C, "GPIO4_4", "SPI0_SDI", "I2C1_SDA",
"reserved", "SENSOR_VS")
MUXCTRL(CV500_iocfg_reg50, 0x114F0080, "GPIO4_5", "SPI0_CSN", "I2C1_SCL",
"SPI_3LINE_CSN", "SENSOR_HS")
MUXCTRL(CV500_iocfg_reg51, 0x111F0000, "GPIO5_0", "UART1_RTSN", "UART4_RXD")
MUXCTRL(CV500_iocfg_reg52, 0x111F0004, "GPIO5_1", "UART1_CTSN", "UART4_TXD")
MUXCTRL(CV500_iocfg_reg53, 0x111F0008, "GPIO5_2", "UART1_RXD")
MUXCTRL(CV500_iocfg_reg54, 0x111F000C, "GPIO5_3", "UART1_TXD")
MUXCTRL(CV500_iocfg_reg55, 0x111F0010, "GPIO5_4", "UART0_RXD")
MUXCTRL(CV500_iocfg_reg56, 0x111F0014, "GPIO5_5", "UART0_TXD")
MUXCTRL(CV500_iocfg_reg57, 0x111F0018, "GPIO5_6", "I2C2_SDA")
MUXCTRL(CV500_iocfg_reg58, 0x111F001C, "GPIO5_7", "I2C2_SCL")
MUXCTRL(CV500_iocfg_reg59, 0x111F0020, "TEST_MODE")
MUXCTRL(CV500_iocfg_reg60, 0x111F0024, "GPIO6_6", "PWM0")
MUXCTRL(CV500_iocfg_reg61, 0x111F0028, "GPIO6_7", "PWM1")
MUXCTRL(CV500_iocfg_reg62, 0x111F002C, "SVB_PWM", "GPIO10_2")
MUXCTRL(CV500_iocfg_reg63, 0x111F0030, "LSADC_CH0", "GPIO10_3")
MUXCTRL(CV500_iocfg_reg64, 0x111F0034, "LSADC_CH1", "GPIO10_4")
MUXCTRL(CV500_iocfg_reg65, 0x112F0000, "GPIO10_6", "I2C7_SCL")
MUXCTRL(CV500_iocfg_reg66, 0x112F0004, "GPIO10_7", "I2C7_SDA", "RMII_CLK")
MUXCTRL(CV500_iocfg_reg67, 0x112F0008, "GPIO6_0", "SDIO1_CCLK_OUT",
"RMII_RX_DV")
MUXCTRL(CV500_iocfg_reg68, 0x112F000C, "GPIO6_1", "SDIO1_CCMD", "EPHY_CLK")
MUXCTRL(CV500_iocfg_reg69, 0x112F0010, "GPIO6_2", "SDIO1_CDATA0", "MDCK")
MUXCTRL(CV500_iocfg_reg70, 0x112F0014, "GPIO6_3", "SDIO1_CDATA1", "MDIO")
MUXCTRL(CV500_iocfg_reg71, 0x112F0018, "GPIO6_4", "SDIO1_CDATA2", "RMII_TX_EN")
MUXCTRL(CV500_iocfg_reg72, 0x112F001C, "GPIO6_5", "SDIO1_CDATA3", "EPHY_RSTN")
MUXCTRL(CV500_iocfg_reg73, 0x112F0020, "JTAG_TRSTN", "SPI1_SCLK", "RMII_TXD1",
"I2S_MCLK", "GPIO8_0")
MUXCTRL(CV500_iocfg_reg74, 0x112F0024, "JTAG_TCK", "SPI1_SDO", "RMII_RXD1",
"I2S_BCLK_TX", "GPIO8_1")
MUXCTRL(CV500_iocfg_reg75, 0x112F0028, "JTAG_TMS", "SPI1_CSN0", "RMII_TXD0",
"I2S_WS_TX", "GPIO8_2")
MUXCTRL(CV500_iocfg_reg76, 0x112F002C, "JTAG_TDO", "SPI1_SDI", "RMII_RXD0",
"I2S_SD_TX", "GPIO8_3")
MUXCTRL(CV500_iocfg_reg77, 0x112F0030, "JTAG_TDI", "SPI1_CSN1", "LCD_DATA23",
"I2S_SD_RX", "GPIO8_4")
MUXCTRL(CV500_iocfg_reg78, 0x112F0034, "GPIO0_6", "reserved", "LCD_CLK",
"VOU1120_CLK/VOU656_CLK")
MUXCTRL(CV500_iocfg_reg79, 0x112F0038, "GPIO8_5", "MDIO", "LCD_DATA5",
"VOU1120_DATA2/VOU656_DATA2")
MUXCTRL(CV500_iocfg_reg80, 0x112F003C, "GPIO8_6", "MDCK", "LCD_DATA4",
"VOU1120_DATA3/VOU656_DATA3", "BOOT_SEL0")
MUXCTRL(CV500_iocfg_reg81, 0x112F0040, "TEST_CLK", "RMII_TXD1", "LCD_DATA1",
"VOU1120_DATA6/VOU656_DATA6", "GPIO8_7")
MUXCTRL(CV500_iocfg_reg82, 0x112F0044, "GPIO7_0", "RMII_TX_EN", "LCD_DATA2",
"VOU1120_DATA5/VOU656_DATA5")
MUXCTRL(CV500_iocfg_reg83, 0x112F0048, "GPIO7_1", "RMII_TXD0", "LCD_DATA0",
"VOU1120_DATA7/VOU656_DATA7")
MUXCTRL(CV500_iocfg_reg84, 0x112F004C, "GPIO7_2", "RMII_CLK", "LCD_HSYNC")
MUXCTRL(CV500_iocfg_reg85, 0x112F0050, "GPIO7_3", "RMII_RX_DV", "LCD_DATA6",
"VOU1120_DATA1/VOU656_DATA1")
MUXCTRL(CV500_iocfg_reg86, 0x112F0054, "GPIO7_4", "RMII_RXD1", "LCD_VSYNC")
MUXCTRL(CV500_iocfg_reg87, 0x112F0058, "GPIO7_5", "RMII_RXD0", "LCD_DE")
MUXCTRL(CV500_iocfg_reg88, 0x112F005C, "GPIO7_6", "EPHY_RSTN", "LCD_DATA3",
"VOU1120_DATA4/VOU656_DATA4", "SFC_DEVICE_MODE")
MUXCTRL(CV500_iocfg_reg89, 0x112F0060, "GPIO7_7", "EPHY_CLK", "LCD_DATA7",
"VOU1120_DATA0/VOU656_DATA0")
MUXCTRL(CV500_iocfg_reg90, 0x112F0064, "DSI_D3P", "GPIO9_0", "LCD_DATA16",
"SHUTTER_TRIG", "LCD_DATA5")
MUXCTRL(CV500_iocfg_reg91, 0x112F0068, "DSI_D3N", "GPIO9_1", "LCD_DATA17",
"FLASH_TRIG", "LCD_CLK")
MUXCTRL(CV500_iocfg_reg92, 0x112F006C, "DSI_D2N", "GPIO9_2", "LCD_DATA14",
"VOU1120_DATA9", "LCD_DATA3")
MUXCTRL(CV500_iocfg_reg93, 0x112F0070, "DSI_D2P", "GPIO9_3", "LCD_DATA15",
"VOU1120_DATA8", "LCD_DATA4")
MUXCTRL(CV500_iocfg_reg94, 0x112F0074, "DSI_CKP", "GPIO9_4", "LCD_DATA12",
"VOU1120_DATA11", "LCD_DATA1")
MUXCTRL(CV500_iocfg_reg95, 0x112F0078, "DSI_CKN", "GPIO9_5", "LCD_DATA13",
"VOU1120_DATA10", "LCD_DATA2")
MUXCTRL(CV500_iocfg_reg96, 0x112F007C, "DSI_D1N", "GPIO9_6", "LCD_DATA10",
"VOU1120_DATA13", "LCD_HSYNC")
MUXCTRL(CV500_iocfg_reg97, 0x112F0080, "DSI_D1P", "GPIO9_7", "LCD_DATA11",
"VOU1120_DATA12", "LCD_DATA0")
MUXCTRL(CV500_iocfg_reg98, 0x112F0084, "DSI_D0P", "GPIO10_0", "LCD_DATA8",
"VOU1120_DATA15", "LCD_DE")
MUXCTRL(CV500_iocfg_reg99, 0x112F0088, "DSI_D0N", "GPIO10_1", "LCD_DATA9",
"VOU1120_DATA14", "LCD_VSYNC")
MUXCTRL(CV500_iocfg_reg100, 0x112F008C, "GPIO0_1", "I2C3_SDA", "LCD_DATA20")
MUXCTRL(CV500_iocfg_reg101, 0x112F0090, "GPIO0_2", "I2C3_SCL", "LCD_DATA19")
MUXCTRL(CV500_iocfg_reg102, 0x112F0094, "GPIO0_3", "IR_IN", "LCD_DATA18")
MUXCTRL(CV500_iocfg_reg103, 0x112F0098, "GPIO0_4", "reserved", "LCD_DATA21")
MUXCTRL(CV500_iocfg_reg104, 0x112F009C, "GPIO0_5", "reserved", "LCD_DATA22")
MUXCTRL(CV500_iocfg_reg105, 0x112F00A0, "GPIO0_0", "UPDATE_MODE")
MUXCTRL(CV500_iocfg_reg107, 0x112F00A8, "PWR_WAKEUP", "GPIO11_0")
MUXCTRL(CV500_iocfg_reg108, 0x112F00AC, "PWR_SEQ0", "GPIO11_1")
static const muxctrl_reg_t *CV500regs[] = {
&CV500_iocfg_reg0, &CV500_iocfg_reg1, &CV500_iocfg_reg2,
&CV500_iocfg_reg3, &CV500_iocfg_reg4, &CV500_iocfg_reg5,
&CV500_iocfg_reg6, &CV500_iocfg_reg7, &CV500_iocfg_reg8,
&CV500_iocfg_reg9, &CV500_iocfg_reg10, &CV500_iocfg_reg11,
&CV500_iocfg_reg12, &CV500_iocfg_reg13, &CV500_iocfg_reg14,
&CV500_iocfg_reg15, &CV500_iocfg_reg16, &CV500_iocfg_reg17,
&CV500_iocfg_reg22, &CV500_iocfg_reg23, &CV500_iocfg_reg24,
&CV500_iocfg_reg25, &CV500_iocfg_reg26, &CV500_iocfg_reg27,
&CV500_iocfg_reg28, &CV500_iocfg_reg29, &CV500_iocfg_reg30,
&CV500_iocfg_reg31, &CV500_iocfg_reg32, &CV500_iocfg_reg33,
&CV500_iocfg_reg34, &CV500_iocfg_reg35, &CV500_iocfg_reg36,
&CV500_iocfg_reg37, &CV500_iocfg_reg38, &CV500_iocfg_reg39,
&CV500_iocfg_reg40, &CV500_iocfg_reg41, &CV500_iocfg_reg42,
&CV500_iocfg_reg43, &CV500_iocfg_reg44, &CV500_iocfg_reg45,