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Added scripts for back-annotate and git-merge
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‎scripts/ba.tcl

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# Back-annotation script. Version 1.3. Janary 16th, 2012. by Ryan Scoville
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# To run, make sure Quartus II project is closed, and type at command prompt:
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# quartus_cdb -t ba.tcl
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###### User Variables #######
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# Variable project_name is the name of the .qpf without the extension. Also can be "auto_find".
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set project_name "auto_find"
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# Wildcard or list of wild cards that nodes must match in order to be back-annotated. Case sensitive.
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set name_wildcards {*}
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# Wildcard or list of wilcards that node location must match in order to be back-annotated. Examples:
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# set location_wildcards {PIN_*} ;# Locks down all the top-level I/O ports
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# set location_wildcards {M9K* M144K* M20K*} ;# Locks down all the hard memory blocks for Stratix IV/V.
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# set location_wildcards {DSP*} ;# Locks down all the DSP blocks
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# set location_wildcards {PLL*} ;# Locks down all the PLL Locations
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# set location_wildcards {CLKCTRL_*} ;# Locks down all the clock trees
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set location_wildcards {*}
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# The following demotes specific location assignments like FF_X34_Y22_N4 to X34_Y22, i.e. to the LAB. This should not hurt timing and gives
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# flexibility to the router. Currently only demotes location names matching FF_, LABCELL_ and MLABCELL_, which are used in 28nm families. Older
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# families may not work as they have different location naming conventions.
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set demote_logic_location_to_LAB 1
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# Assignment appended with this comment, making it easier to find/sort/delete these assignments in the .qsf and especially the Assignment Editor
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set comment from_ba.tcl
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# If debug set to 1, "puts" the assignments into a file called ba_assignments.tcl, but does not modify the project in any way.
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# The assignments can then be copied into the .qsf, or the ba_assignments.tcl can be sourced from within Quartus. This will append assignments if ba_assignments.tcl already exists.
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set debug 1
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##############################
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##### Usage #######
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# This script back-annotates nodes in a design based on name and location wildcards that the user chooses.
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# Note that Quartus II Assignments -> Back-Annotate from the menu already allows the user to lock down top-level ports in the design, or everything. This
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# script provides a little more control. In general, it is not recommended to lock down a large number of nodes inside the FPGA. Node names often change
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# during synthesis, and locking down portions of the design can limit what the fitter can do. The original intent of this script is to allow the user to
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# lock down all the memories and DSP in a design. Theoretically, after doing a seed sweep and locking down the memories and DSP of the best result,
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# the user can "anchor" the fitter into getting similar results. Of course this is design dependent. (The design I ran it on had less variation and on average gave
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# better results than the un-anchored compiles, but the very best result was from the unanchored seed sweep.)
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# I have also used this script to quickly lock down PLLs and global clock trees. I am sure user's will find their own applications. Incremental Compilation
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# is recommended for locking down hierarchies of the design.
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###################
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proc demote_logic_to_LAB {loc} {
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if {[regexp {^(FF_X)([0-9]+)(_Y)([0-9]+)} $loc a b x_loc d y_loc]} {
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set loc "X$x_loc\_Y$y_loc"
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} elseif {[regexp {^(LABCELL_X)([0-9]+)(_Y)([0-9]+)} $loc a b x_loc d y_loc]} {
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set loc "X$x_loc\_Y$y_loc"
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} elseif {[regexp {^(MLABCELL_X)([0-9]+)(_Y)([0-9]+)} $loc a b x_loc d y_loc]} {
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set loc "X$x_loc\_Y$y_loc"
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}
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return $loc
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}
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############################################
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# Auto find the project name to open, if there is only one project in the directory(which is good practice...)
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if {$project_name == "auto_find"} {
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set qpf [glob *.qpf]
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set num_quartus_projects [llength $qpf]
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if {$num_quartus_projects == 0} {
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puts "There is no .qpf in this directory. No project to open."
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} elseif {$num_quartus_projects == 1} {
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set project_name [file rootname $qpf]
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} else {
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puts "There is more than one *.qpf in this project: $qpf"
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puts "Open remove_qip_from_project.tcl, uncomment line 1, and change project_name from auto_find to .qpf name. For example, if project is called my_top.qpf, set line 1 to:"
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puts "set project_name my_top.qpf"
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exit
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}
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} elseif {![file exists "$project_name\.qpf"]} {
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puts "Variable project_name was set to $project_name, but $project_name\.qpf could not be found in directory."
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exit
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}
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project_open $project_name -current_revision ;# -force ;# In one case I needed to use -force option even though opening with same version of Quartus.
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load_package chip_planner
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read_netlist
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set_batch_mode on
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if {$debug == 1} {
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set outfile [open ba_assignments.tcl a]
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}
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set matched_nodes 0
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set assign_name ""
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set assign_loc ""
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# User name match wildcards often have [] in their name, but that has special meaning when doing a "string match $wildcard name".
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# The following replaces [ with \[ and ] with \] so it works.
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set newname_wildcards ""
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foreach name $name_wildcards {
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regsub -all {]} $name {\]} name
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regsub -all {\[} $name {\[} name
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lappend newname_wildcards $name
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}
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set all_nodes [get_nodes -type all]
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foreach_in_collection node $all_nodes {
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set node_name [get_node_info -node $node -info name]
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set node_loc [get_node_info -node $node -info "Location String"]
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set name_matches 0
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set loc_matches 0
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#puts $outfile "$node_name $node_loc"
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foreach name $newname_wildcards {
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if {[string match $name $node_name]} {
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set name_matches 1
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#puts $outfile " name=$name"
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#puts $outfile "node_name=$node_name"
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break
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}
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}
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foreach loc $location_wildcards {
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if {[string match $loc $node_loc]} {
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set loc_matches 1
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break
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}
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}
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if {($name_matches == 1) && ($loc_matches)} {
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#puts $outfile "MATCH!!!!"
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set assign_name $node_name
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set assign_loc $node_loc
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if {$demote_logic_location_to_LAB} {
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set assign_loc [demote_logic_to_LAB $assign_loc]
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}
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incr matched_nodes
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if {$debug == 1} {
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puts $outfile "set_location_assignment $assign_loc -to $assign_name -comment $comment"
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} elseif {$debug == 0} {
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set_location_assignment $assign_loc -to $assign_name -comment $comment
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} else {
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puts {Errors: Variable debug was not "1" or "0"}
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break
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}
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}
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}
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puts "Found $matched_nodes nodes that match name $name_wildcards and location $location_wildcards."
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if {$debug == 1} {
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puts $outfile "#Found $matched_nodes nodes that match name $name_wildcards and location $location_wildcards."
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close $outfile
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}
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set_batch_mode off
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project_close
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‎scripts/git-merge-fix.sh

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#!/bin/bash
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# automatization script for commiting marge requests
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FIX_BRANCH_NAME=${1}
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fail() {
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echo $1;
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exit 1;
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}
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COMMIT_MESSAGE=${2}
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if [ -z "${COMMIT_MESSAGE}" ]; then
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COMMIT_MESSAGE="${FIX_BRANCH_NAME} Merged fix to master."
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fi
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# Check for uncommitted changes
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if [[ -n $(git status -s) ]]; then
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fail "The current branch has uncommitted changes (run 'git status' to see them)."
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fi
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# Check the current branch
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CURRENT_BRANCH=$(git name-rev HEAD --name-only 2> /dev/null)
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if [ "${CURRENT_BRANCH}" != "master" ]; then
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git checkout master
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[[ $? == 0 ]] || fail "Could not switch to master branch."
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fi
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git merge --no-commit --no-ff ${FIX_BRANCH_NAME} && git commit -m "${COMMIT_MESSAGE}"

‎scripts/jtag_to_axi_master.tcl

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# Use this script to read/write AXI bus through "JTAG to AXI Master" IP-core
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# value should be 8 HEX digits == 32bit
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proc wr {address value} {
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proc jwr {address value} {
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#set address [string range $address 2 [expr {[string length $address]-1}]]
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create_hw_axi_txn -force wr_tx [get_hw_axis hw_axi_1] \
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-address $address -data $value -len 1 -type write
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run_hw_axi -quiet wr_tx
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}
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proc rd {address} {
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proc jrd {address} {
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#set address [string range $address 2 [expr {[string length $address]-1}]]
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create_hw_axi_txn -force rd_tx [get_hw_axis hw_axi_1] \
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-address $address -len 1 -type read

‎scripts/post_flow_vivado.tcl

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# Set this script as a post.tcl for "Generate bitstream" step
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#===============================================================================
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# compuiting elapsed time
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puts "=== COMPILE TIME ================================================="
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puts "=== post_flow_vivado ================================================="
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# compuiting elapsed time
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set hs 0
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set ms 0
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set ss 0
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puts [ join [ list "TOTAL: " [format "%02d:%02d:%02d" $hs_t $ms_t $ss_t]] "" ]
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# cd to project directory
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set work_directory [file dirname [get_property NAME [get_files "*[get_property top [current_fileset]]*.sv" ] ]]
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#set work_directory [get_property DIRECTORY [current_project]]
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cd $work_directory
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puts -nonewline "Changed directory to " ; pwd
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puts ""
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‎scripts/program_all.bat

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echo "Programming first FPGA in the chain"
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C:\intelFPGA_lite\17.0\quartus\bin64\quartus_pgm -c ^
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"USB-Blaster on 192.168.0.182 [USB-1]" -m jtag -o ^
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"P;D:\project1\main.sof@1"
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"P;%~dp0out\main.sof@1"
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echo "Programming second FPGA in the chain"
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C:\intelFPGA_lite\17.0\quartus\bin64\quartus_pgm -c ^
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"USB-Blaster on 192.168.0.182 [USB-1]" -m jtag -o ^
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"P;D:\project2\main.sof@2"
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"P;%~dp0out\main.sof@2"
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pause
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exit

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