cpu: Implement decoupled front-end

This commit comprises most of the changes to add
the decoupled front-end. Here just the most
important bits:
- Creates a new pipeline stage called BAC (Branch and
  Address Calculation).
- The branch predictor is moved to the new stage
  and with it all the functionality related to it.
  (e.g. squashing is done in BAC)
- The BAC stage contains two parts the branch
  predictor part and the next PC calculation. Both
  can be decoupled and connected with the fetch
  target queue.

Note: this commit will not commit as the BPU must
be updated.

Change-Id: Ieb9b6d3cd6cfbdc2408b5e2c341af20650dd1b3c
Signed-off-by: David Schall <david.schall@ed.ac.uk>

Author: dhschall

src/arch/arm/decoder.cc

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2012-2014,2018, 2021 Arm Limited
+ * Copyright (c) 2023 The University of Edinburgh
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall

src/arch/x86/decoder.cc

@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2022-2023 The University of Edinburgh
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2011 Google
  * All rights reserved.
  *

src/cpu/o3/BaseO3CPU.py

@@ -1,4 +1,5 @@
 # Copyright (c) 2016, 2019 ARM Limited
+# Copyright (c) 2022-2023 The University of Edinburgh
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -83,6 +84,8 @@ def support_take_over(cls):
     )
     cacheLoadPorts = Param.Unsigned(200, "Cache Ports. Constrains loads only.")
 
+    # Backward pipeline delays
+    fetchToBacDelay = Param.Cycles(1, "Fetch to Branch address calc. delay")
     decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
     renameToFetchDelay = Param.Cycles(1, "Rename to fetch delay")
     iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch delay")
@@ -98,6 +101,9 @@ def support_take_over(cls):
         1, "Issue/Execute/Writeback to decode delay"
     )
     commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay")
+
+    # Forward pipeline delays
+    bacToFetchDelay = Param.Cycles(1, "Branch address calc. to fetch delay")
     fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay")
     decodeWidth = Param.Unsigned(8, "Decode width")
 
@@ -192,3 +198,18 @@ def support_take_over(cls):
         TournamentBP(numThreads=Parent.numThreads), "Branch Predictor"
     )
     needsTSO = Param.Bool(False, "Enable TSO Memory model")
+
+    numFTQEntries = Param.Unsigned(
+        8, "Number of entries in the Fetch target queue."
+    )
+    fetchTargetWidth = Param.Unsigned(
+        32,
+        "Max width (bytes) of Fetch target. "
+        "Determines the maximum search width per cycle",
+    )
+    minInstSize = Param.Unsigned(
+        1,
+        "Minimum instruction size (bytes). Determines the granularity "
+        "of the instruction minimum search width per cycle",
+    )
+    decoupledFrontEnd = Param.Bool(False, "Enables the decoupled front-end")

src/cpu/o3/SConscript

@@ -1,5 +1,17 @@
 # -*- mode:python -*-
-
+#
+# Copyright (c) 2023 The University of Edinburgh
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -36,6 +48,7 @@ if not env['CONF']['USE_NULL_ISA']:
     SimObject('BaseO3CPU.py', sim_objects=['BaseO3CPU'], enums=[
         'SMTFetchPolicy', 'SMTQueuePolicy', 'CommitPolicy'])
 
+    Source('bac.cc')
     Source('commit.cc')
     Source('cpu.cc')
     Source('decode.cc')
@@ -58,6 +71,7 @@ if not env['CONF']['USE_NULL_ISA']:
     Source('thread_context.cc')
     Source('thread_state.cc')
 
+    DebugFlag('BAC')
     DebugFlag('CommitRate')
     DebugFlag('FTQ')
     DebugFlag('IEW')
@@ -72,7 +86,8 @@ if not env['CONF']['USE_NULL_ISA']:
     DebugFlag('StoreSet')
     DebugFlag('Writeback')
 
-    CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit',
+    CompoundFlag('O3CPUAll', [ 'BAC', 'FTQ', 'Fetch', 'Decode', 'Rename',
+        'IEW', 'Commit',
         'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
         'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ])