From 6bde6cb7d0121276eb613a93965e8d1049eec64d Mon Sep 17 00:00:00 2001 From: xesscorp Date: Tue, 25 May 2021 17:02:19 -0400 Subject: [PATCH] Made preliminary 1.1.0 release for version with generate_pcb feature. --- HISTORY.rst | 2 +- Makefile | 6 +- docs/_site/404/index.html | 66 ++--- docs/_site/about/index.html | 64 ++--- docs/_site/api.html | 261 +++++++++--------- docs/_site/assets/css/style.css | 4 +- docs/_site/blog/Release_0_0_27.html | 72 ++--- docs/_site/blog/Release_0_0_28.html | 72 ++--- docs/_site/blog/Release_0_0_30.html | 72 ++--- docs/_site/blog/a-taste-of-hierarchy.html | 76 ++--- docs/_site/blog/an-arduino-with-skidl.html | 74 ++--- ...g-a-usb-to-jtag-interface-using-skidl.html | 80 +++--- docs/_site/blog/custom-erc.html | 72 ++--- docs/_site/blog/dont-replicate-automate.html | 74 ++--- docs/_site/blog/index.html | 104 +++---- docs/_site/blog/names-not-numbers.html | 82 +++--- docs/_site/blog/one-dot-oh.html | 72 ++--- docs/_site/blog/others-use-it-too.html | 74 ++--- docs/_site/blog/package-decorator.html | 72 ++--- docs/_site/blog/page2/index.html | 104 +++---- docs/_site/blog/reuse-leds.html | 80 +++--- docs/_site/blog/skidl-forum.html | 72 ++--- docs/_site/blog/skidl-kicon-2019.html | 72 ++--- docs/_site/blog/spice-simulation.html | 72 ++--- docs/_site/blog/sweetening-skidl.html | 88 +++--- docs/_site/blog/two-easy-pieces.html | 86 +++--- docs/_site/blog/worst-part-of-skidl.html | 92 +++--- docs/_site/blog/xspice-capability.html | 72 ++--- docs/_site/categories/index.html | 104 +++---- docs/_site/feed.xml | 256 ++++++++--------- docs/_site/index.html | 73 ++--- docs/_site/links.jsonp | 40 +-- docs/_site/search.json | 40 +-- docs/_site/static/documentation_options.js | 2 +- docs/_site/tags/index.html | 64 ++--- docs/api.html | 261 +++++++++--------- docs/index.md | 10 +- docs/static/documentation_options.js | 2 +- setup.py | 2 +- skidl/network.py | 10 +- skidl/part.py | 7 - skidl/pckg_info.py | 2 +- 42 files changed, 1513 insertions(+), 1497 deletions(-) diff --git a/HISTORY.rst b/HISTORY.rst index ff948d3b..45e9e9d8 100644 --- a/HISTORY.rst +++ b/HISTORY.rst @@ -3,7 +3,7 @@ History ------- -1.0.1 (YYYY-MM-DD) +1.1.0 (YYYY-MM-DD) ______________________ - Added `generate_pcb()` function to create a PCB file directly from diff --git a/Makefile b/Makefile index 06464f21..47ef675b 100644 --- a/Makefile +++ b/Makefile @@ -58,8 +58,10 @@ docs: open docs/_build/html/index.html release: clean - python setup.py sdist upload - python setup.py bdist_wheel upload + python setup.py sdist + python setup.py bdist_wheel + cd docs/_api; make singlehtml + cd docs; jekyll build dist: clean python setup.py sdist diff --git a/docs/_site/404/index.html b/docs/_site/404/index.html index 53555da2..05ea652f 100644 --- a/docs/_site/404/index.html +++ b/docs/_site/404/index.html @@ -8,7 +8,7 @@ - + @@ -18,16 +18,16 @@ - + - + - - + + @@ -37,13 +37,13 @@ - + - - - - - + + + + + @@ -51,25 +51,25 @@ - + - + - + - + - + - +
-
@@ -81,12 +81,12 @@
  • - Home + Home
  • - Blog + Blog
    • @@ -96,7 +96,7 @@
  • - API + API
    • @@ -106,11 +106,11 @@
  • - About + About
    • -
  • Feed
    • +
  • Feed
    • @@ -121,7 +121,7 @@

    -

    at SKiDL

    +

    at SKiDL

    Oops...!

    @@ -149,8 +149,8 @@

    Oops...!


    - hacker emblem - + hacker emblem +

    - - - + + + - - - + + +
    -
    @@ -81,12 +81,12 @@
  • - Home + Home
  • - Blog + Blog
    • @@ -96,7 +96,7 @@
  • - API + API
    • @@ -106,11 +106,11 @@
  • - About + About
    • -
  • Feed
    • +
  • Feed
    • @@ -162,8 +162,8 @@

    Contributors


    - hacker emblem - + hacker emblem +

    - - - + + + - - - + + + @@ -19,7 +20,7 @@ @@ -35,27 +36,27 @@

    This is a really, really bad API document. I’m working to make Sphinx generate a better one but, right now, the description on the homepage about how to use SKiDL is much better than this.

    -
    +

    SKiDL API

    -
    +

    Overview of How SKiDL Works

    This is an overview of how SKiDL works.

    -
    -
    +
    +

    skidl

    -
    +

    skidl package

    -
    +

    Subpackages

    -
    +
    skidl.tools package
    -
    +
    Submodules
    -
    -
    +
    +
    skidl.tools.kicad module

    Handler for reading Kicad libraries and generating netlists.

    @@ -625,12 +626,12 @@
    Submodules +
    +
    skidl.tools.skidl module

    Handler for reading SKiDL libraries and generating netlists.

    -
    -
    +
    +
    skidl.tools.spice module

    Handler for reading SPICE libraries.

    @@ -706,18 +707,18 @@
    Submodules +
    +
    Module contents

    This package contains the handler functions for various EDA tools.

    +
    +
    -
    -
    - -
    + +

    Submodules

    -
    -
    + +

    skidl.alias module

    Handles aliases for Circuit, Part, Pin, Net, Bus, Interface objects.

    @@ -738,8 +739,8 @@

    Submodules +

    +

    skidl.arrange module

    Arrange part units for best schematic wiring.

    @@ -835,8 +836,8 @@

    Submodules +

    +

    skidl.bus module

    Handles buses.

    @@ -980,8 +981,8 @@

    Submodules +

    +

    skidl.circuit module

    Handles complete circuits made of parts and nets.

    @@ -1150,6 +1151,25 @@

    Submodules +
    +generate_pcb(**kwargs)
    +

    Create a PCB file from the circuit.

    +
    +
    Parameters
    +
      +

    • file – Either a file object that can be written to, or a string +containing a file name, or None.

      • +

    • tool – The EDA tool the netlist will be generated for.

      • +

    • do_backup – If true, create a library with all the parts in the circuit.

      • +
    +
    +
    Returns
    +

    None.

    +
    +
    +

    +
    generate_xml(file_=None, tool=None)
    @@ -1278,12 +1298,12 @@

    Submodules +

    +

    skidl.common module

    Stuff everyone needs.

    -
    -
    + +

    skidl.coord module

    @@ -1327,12 +1347,12 @@

    Submodules +

    +

    skidl.defines module

    Definitions used everywhere.

    -
    -
    + +

    skidl.erc module

    ERC functions for Circuit, Part, Pin, Net, Bus, Interface objects.

    @@ -1353,8 +1373,8 @@

    Submodules +

    +

    skidl.interface module

    Handles interfaces for subsystems with complicated I/O.

    @@ -1390,8 +1410,8 @@

    Submodules +

    +

    skidl.logger module

    Logging for generic messages and ERC.

    @@ -1446,8 +1466,8 @@

    Submodules +

    +

    skidl.net module

    Handles nets.

    @@ -1721,8 +1741,8 @@

    Submodules +

    +

    skidl.netclass module

    Class for PCBNEW net classes.

    @@ -1731,8 +1751,8 @@

    Submodulesobject

    -
    -
    + +

    skidl.netlist_to_skidl module

    Convert a netlist into an equivalent SKiDL program.

    @@ -1740,8 +1760,8 @@

    Submodulesskidl.netlist_to_skidl.netlist_to_skidl(netlist_src)

    -
    -
    + +

    skidl.netlist_to_skidl_main module

    Command-line program to convert a netlist into an equivalent SKiDL program.

    @@ -1749,8 +1769,8 @@

    Submodulesskidl.netlist_to_skidl_main.main()

    -
    -
    + +

    skidl.netpinlist module

    Specialized list for handling nets, pins, and buses.

    @@ -1776,8 +1796,8 @@

    Submodules +

    +

    skidl.network module

    Object for for handling series and parallel networks of two-pin parts, nets, and pins.

    @@ -1798,19 +1818,21 @@

    Submodulesskidl.network.tee(ntwk)

    Create a network “tee” by returning the first terminal of a Network object. Then you can create tee’ed networks like so: vi & r1 & r2 & tee(r3 & r4 & gnd) & r5 & gnd -which becomes: -vi—r1—r2-+-r5—gnd

    +which becomes:

    -
    +
    +
    vi—r1—r2-+-r5—gnd


    r3—r4—gnd

    +
    +

    -
    -
    + +

    skidl.note module

    Supports user-specified notes that can be attached to other SKiDL objects.

    @@ -1829,8 +1851,8 @@

    Submodules +

    +

    skidl.package module

    Package a subcircuit so it can be used like a Part.

    @@ -1850,8 +1872,8 @@

    Submodules +

    +

    skidl.part module

    Handles parts.

    @@ -1882,39 +1904,9 @@

    Submodules
    -class skidl.part.Part(lib=None, name=None, dest='NETLIST', tool=None, connections=None, part_defn=None, circuit=None, **kwargs)
    +class skidl.part.Part(lib=None, name=None, dest='NETLIST', tool=None, connections=None, part_defn=None, circuit=None, ref_prefix='U', ref=None, tag=None, pin_splitters=None, tool_version=None, **kwargs)

    Bases: skidl.skidlbaseobj.SkidlBaseObject

    A class for storing a definition of a schematic part.

    -
    -
    -ref
    -

    String storing the reference of a part within a schematic (e.g., ‘R5’).

    -
    - -
    -
    -value
    -

    String storing the part value (e.g., ‘3K3’).

    -
    - -
    -
    -footprint
    -

    String storing the PCB footprint associated with a part (e.g., SOIC-8).

    -
    - -
    -
    -pins
    -

    List of Pin objects for this part.

    -
    - -
    -
    -tag
    -

    A tag string to link a part to its footprint in a pcb editor.

    -
    -
    Parameters
    -
    -property ref
    +
    +property ref

    Get, set and delete the part reference.

    When setting the part reference, if another part with the same reference is found, the reference for this part is adjusted to make @@ -2263,8 +2260,8 @@

    Submodules -
    -property value
    +
    +property value

    Get, set and delete the part value.

    @@ -2362,8 +2359,8 @@

    Submodules +

    +

    skidl.part_query module

    Functions for finding/displaying parts and footprints.

    @@ -2480,11 +2477,11 @@

    Submodules +

    +

    skidl.pckg_info module

    -
    -
    + +

    skidl.pin module

    Handles part pins.

    @@ -2781,6 +2778,12 @@

    Submodules +
    +property ref
    +

    Return the reference of the part the pin belongs to.

    +

    +
    BIDIR = 3
    @@ -2881,8 +2884,8 @@

    Submodules +

    +

    skidl.protonet module

    Prototype of a net which can become a Net or a Bus depending upon what is connected to it.

    @@ -2902,12 +2905,12 @@

    Submodules +

    +

    skidl.pyspice module

    Import this file to reconfigure SKiDL for doing SPICE simulations.

    -
    -
    + +

    skidl.schlib module

    Handles schematic libraries for various ECAD tools.

    @@ -3008,8 +3011,8 @@

    Submodules +

    +

    skidl.scriptinfo module

    Routines for getting information about a script.

    @@ -3042,8 +3045,8 @@

    Submodules +

    +

    skidl.skidl module

    @@ -3119,8 +3122,8 @@

    Submodules +

    +

    skidl.skidlbaseobj module

    Base object for Circuit, Interface, Package, Part, Net, Bus, Pin objects.

    @@ -3172,8 +3175,8 @@

    Submodules +

    +

    skidl.utilities module

    Utility functions used by the rest of SKiDL.

    @@ -3472,8 +3475,8 @@

    Submodules +

    +

    Module contents

    SKiDL: A Python-Based Schematic Design Language

    This module extends Python with the ability to design electronic @@ -3489,20 +3492,20 @@

    Submodules +

    +

    Indices and tables

    -
    +
    diff --git a/docs/_site/assets/css/style.css b/docs/_site/assets/css/style.css index 7c96360e..a832f2de 100644 --- a/docs/_site/assets/css/style.css +++ b/docs/_site/assets/css/style.css @@ -210,7 +210,7 @@ main, .notepad-share-icons, .notepad-disqus { text-align: center; background-size: cover; background-color: black; - background-image: url("https://xesscorp.github.io/skidl/docs/_site/images/python-to-pcb.jpg"); + background-image: url("http://localhost:4000/images/python-to-pcb.jpg"); } .notepad-site-head .notepad-site-head-content.with-bg-cover { @@ -1074,7 +1074,7 @@ code { .tooltipContainer a { width: 100%; - background: transparent url("https://xesscorp.github.io/skidl/docs/_site/images/sprites.png") 0px 0px no-repeat; + background: transparent url("http://localhost:4000/images/sprites.png") 0px 0px no-repeat; padding: 0; left: 0; top: 0; diff --git a/docs/_site/blog/Release_0_0_27.html b/docs/_site/blog/Release_0_0_27.html index f87d9e1d..90bb2fe2 100644 --- a/docs/_site/blog/Release_0_0_27.html +++ b/docs/_site/blog/Release_0_0_27.html @@ -8,7 +8,7 @@ - + @@ -18,16 +18,16 @@ - + - + - - + + @@ -37,13 +37,13 @@ - + - - - - - + + + + + @@ -51,17 +51,17 @@ - + - + - + - + - + - + @@ -73,8 +73,8 @@
    -
    @@ -86,12 +86,12 @@
  • - Home + Home
  • - Blog + Blog
    • @@ -101,7 +101,7 @@
  • - API + API
    • @@ -111,11 +111,11 @@
  • - About + About
    • -
  • Feed
    • +
  • Feed
    • @@ -175,15 +175,15 @@

    Version 0.0.27 Released!

    - - - @@ -193,7 +193,7 @@

    Version 0.0.27 Released!

    - Dave Vandenbout's photo + Dave Vandenbout's photo Author:

    Dave Vandenbout

    devb@xess.com @@ -223,8 +223,8 @@

    Dave Vandenbout


    - hacker emblem - + hacker emblem +

    - Blog + Blog
    @@ -164,7 +164,7 @@

    - + Customized ERC!

    @@ -173,7 +173,7 @@

    Everybody wants ERC. Everybody hates ERC. Electrical rules checking (ERC) looks for errors in how your circuit is constructed. It’s like running lint, but for hardware. And as with lint, you get a whole bunch of warnings that don’t matter...

    - Blog + Blog

    @@ -194,7 +194,7 @@

    - + Good Things Come In Packages!

    @@ -203,7 +203,7 @@

    Up to now, SKiDL supported hierarchy by applying the @subcircuit decorator to a Python function: @subcircuit def analog_average(in1, in2, avg): """Output the average of the two inputs.""" # Create two 1K resistors. r1, r2 = 2 * Part('Device', 'R', value='1K',...

    - Blog + Blog

    @@ -224,7 +224,7 @@

    - + New SKiDL Forum!

    @@ -233,7 +233,7 @@

    FYI: The forum has moved. I created a Github Discussions forum for SKiDL. There, you can ask questions about SKiDL and post about projects you’re doing with it. This will probably be a more convenient channel for such things rather...

    - Blog + Blog

    @@ -254,7 +254,7 @@

    - + Version 0.0.30 Released!

    @@ -263,7 +263,7 @@

    I’m releasing version 0.0.30 of SKiDL today! It has some new features I’m excited about: A new @package decorator to make subcircuits act like Parts. A new tee() function for creating T-junctions in networks. Custom ERCs can now be added...

    - Blog + Blog

    @@ -284,7 +284,7 @@

    - + xspice capability

    @@ -293,7 +293,7 @@

    Somebody asked about using XSPICE components in SPICE simulations with SKiDL. That wasn’t possible since PySpice didn’t really support these when I built the interface. So I added XSPICE parts to the SKiDL SPICE interface and released it as SKiDL...

    - Blog + Blog

    @@ -314,7 +314,7 @@

    - + Version 0.0.28 Released!

    @@ -323,7 +323,7 @@

    Well, that didn’t last long. I released version 0.0.27 of SKiDL yesterday, but I didn’t like having the zyc utility bundled in there because that pulls in wxpython as a requirement. That’s likely to cause problems for some people when...

    - Blog + Blog

    @@ -344,7 +344,7 @@

    - + Version 0.0.27 Released!

    @@ -353,7 +353,7 @@

    It’s been almost eleven months since I released a new version of SKiDL (not counting updates to the Github repo). So here’s a new one: version 0.0.27. You can install it using pip just like all the other releases. Check...

    - Blog + Blog

    @@ -374,7 +374,7 @@

    - + The Worst Part of SKiDL

    @@ -383,7 +383,7 @@

    I created SKiDL to replace the manual tedium of drawing schematics with the advantages of modern programming languages: iteration, abstraction, hierarchy, and modularization. But one thing always stood out as a problem: Parts. Here’s a snippet of SKiDL code to...

    - Blog + Blog

    @@ -404,7 +404,7 @@

    - + SKiDL at KiCon 2019

    @@ -413,7 +413,7 @@

    At the recent KiCon 2019, I gave a talk about SKiDL that’s a good introduction to the language and why I created it. It’s about 27 minutes in length if you can stand it. I got a lot of great...

    - Blog + Blog

    @@ -425,7 +425,7 @@

    Page 1 of 2 - Older + Older @@ -451,8 +451,8 @@


    - hacker emblem - + hacker emblem +

    -
    + +

    Submodules

    -
    -
    + +

    skidl.alias module

    Handles aliases for Circuit, Part, Pin, Net, Bus, Interface objects.

    @@ -738,8 +739,8 @@

    Submodules +

    +

    skidl.arrange module

    Arrange part units for best schematic wiring.

    @@ -835,8 +836,8 @@

    Submodules +

    +

    skidl.bus module

    Handles buses.

    @@ -980,8 +981,8 @@

    Submodules +

    +

    skidl.circuit module

    Handles complete circuits made of parts and nets.

    @@ -1150,6 +1151,25 @@

    Submodules +
    +generate_pcb(**kwargs)
    +

    Create a PCB file from the circuit.

    +
    +
    Parameters
    +
      +

    • file – Either a file object that can be written to, or a string +containing a file name, or None.

      • +

    • tool – The EDA tool the netlist will be generated for.

      • +

    • do_backup – If true, create a library with all the parts in the circuit.

      • +
    +
    +
    Returns
    +

    None.

    +
    +
    +

    +
    generate_xml(file_=None, tool=None)
    @@ -1278,12 +1298,12 @@

    Submodules +

    +

    skidl.common module

    Stuff everyone needs.

    -
    -
    + +

    skidl.coord module

    @@ -1327,12 +1347,12 @@

    Submodules +

    +

    skidl.defines module

    Definitions used everywhere.

    -
    -
    + +

    skidl.erc module

    ERC functions for Circuit, Part, Pin, Net, Bus, Interface objects.

    @@ -1353,8 +1373,8 @@

    Submodules +

    +

    skidl.interface module

    Handles interfaces for subsystems with complicated I/O.

    @@ -1390,8 +1410,8 @@

    Submodules +

    +

    skidl.logger module

    Logging for generic messages and ERC.

    @@ -1446,8 +1466,8 @@

    Submodules +

    +

    skidl.net module

    Handles nets.

    @@ -1721,8 +1741,8 @@

    Submodules +

    +

    skidl.netclass module

    Class for PCBNEW net classes.

    @@ -1731,8 +1751,8 @@

    Submodulesobject

    -
    -
    + +

    skidl.netlist_to_skidl module

    Convert a netlist into an equivalent SKiDL program.

    @@ -1740,8 +1760,8 @@

    Submodulesskidl.netlist_to_skidl.netlist_to_skidl(netlist_src)

    -
    -
    + +

    skidl.netlist_to_skidl_main module

    Command-line program to convert a netlist into an equivalent SKiDL program.

    @@ -1749,8 +1769,8 @@

    Submodulesskidl.netlist_to_skidl_main.main()

    -
    -
    + +

    skidl.netpinlist module

    Specialized list for handling nets, pins, and buses.

    @@ -1776,8 +1796,8 @@

    Submodules +

    +

    skidl.network module

    Object for for handling series and parallel networks of two-pin parts, nets, and pins.

    @@ -1798,19 +1818,21 @@

    Submodulesskidl.network.tee(ntwk)

    Create a network “tee” by returning the first terminal of a Network object. Then you can create tee’ed networks like so: vi & r1 & r2 & tee(r3 & r4 & gnd) & r5 & gnd -which becomes: -vi—r1—r2-+-r5—gnd

    +which becomes:

    -
    +
    +
    vi—r1—r2-+-r5—gnd


    r3—r4—gnd

    +
    +

    -
    -
    + +

    skidl.note module

    Supports user-specified notes that can be attached to other SKiDL objects.

    @@ -1829,8 +1851,8 @@

    Submodules +

    +

    skidl.package module

    Package a subcircuit so it can be used like a Part.

    @@ -1850,8 +1872,8 @@

    Submodules +

    +

    skidl.part module

    Handles parts.

    @@ -1882,39 +1904,9 @@

    Submodules
    -class skidl.part.Part(lib=None, name=None, dest='NETLIST', tool=None, connections=None, part_defn=None, circuit=None, **kwargs)
    +class skidl.part.Part(lib=None, name=None, dest='NETLIST', tool=None, connections=None, part_defn=None, circuit=None, ref_prefix='U', ref=None, tag=None, pin_splitters=None, tool_version=None, **kwargs)

    Bases: skidl.skidlbaseobj.SkidlBaseObject

    A class for storing a definition of a schematic part.

    -
    -
    -ref
    -

    String storing the reference of a part within a schematic (e.g., ‘R5’).

    -
    - -
    -
    -value
    -

    String storing the part value (e.g., ‘3K3’).

    -
    - -
    -
    -footprint
    -

    String storing the PCB footprint associated with a part (e.g., SOIC-8).

    -
    - -
    -
    -pins
    -

    List of Pin objects for this part.

    -
    - -
    -
    -tag
    -

    A tag string to link a part to its footprint in a pcb editor.

    -
    -
    Parameters
    -
    -property ref
    +
    +property ref

    Get, set and delete the part reference.

    When setting the part reference, if another part with the same reference is found, the reference for this part is adjusted to make @@ -2263,8 +2260,8 @@

    Submodules -
    -property value
    +
    +property value

    Get, set and delete the part value.

    @@ -2362,8 +2359,8 @@

    Submodules +

    +

    skidl.part_query module

    Functions for finding/displaying parts and footprints.

    @@ -2480,11 +2477,11 @@

    Submodules +

    +

    skidl.pckg_info module

    -
    -
    + +

    skidl.pin module

    Handles part pins.

    @@ -2781,6 +2778,12 @@

    Submodules +
    +property ref
    +

    Return the reference of the part the pin belongs to.

    +

    +
    BIDIR = 3
    @@ -2881,8 +2884,8 @@

    Submodules +

    +

    skidl.protonet module

    Prototype of a net which can become a Net or a Bus depending upon what is connected to it.

    @@ -2902,12 +2905,12 @@

    Submodules +

    +

    skidl.pyspice module

    Import this file to reconfigure SKiDL for doing SPICE simulations.

    -
    -
    + +

    skidl.schlib module

    Handles schematic libraries for various ECAD tools.

    @@ -3008,8 +3011,8 @@

    Submodules +

    +

    skidl.scriptinfo module

    Routines for getting information about a script.

    @@ -3042,8 +3045,8 @@

    Submodules +

    +

    skidl.skidl module

    @@ -3119,8 +3122,8 @@

    Submodules +

    +

    skidl.skidlbaseobj module

    Base object for Circuit, Interface, Package, Part, Net, Bus, Pin objects.

    @@ -3172,8 +3175,8 @@

    Submodules +

    +

    skidl.utilities module

    Utility functions used by the rest of SKiDL.

    @@ -3472,8 +3475,8 @@

    Submodules +

    +

    Module contents

    SKiDL: A Python-Based Schematic Design Language

    This module extends Python with the ability to design electronic @@ -3489,20 +3492,20 @@

    Submodules +

    +

    Indices and tables

    -
    +
    diff --git a/docs/index.md b/docs/index.md index 19c5e4a9..9679710e 100644 --- a/docs/index.md +++ b/docs/index.md @@ -27,7 +27,7 @@ create a finished circuit board. - [Instantiating Parts](#instantiating-parts) - [Connecting Pins](#connecting-pins) - [Checking for Errors](#checking-for-errors) - - [Generating a Netlist](#generating-a-netlist) + - [Generating a Netlist or PCB](#generating-a-netlist-or-pcb) - [Going Deeper](#going-deeper) - [Basic SKiDL Objects: Parts, Pins, Nets, Buses](#basic-skidl-objects-parts-pins-nets-buses) - [Creating SKiDL Objects](#creating-skidl-objects) @@ -550,7 +550,7 @@ No ERC errors or warnings found. ``` -## Generating a Netlist +## Generating a Netlist or PCB The end goal of using SKiDL is to generate a netlist that can be used with a layout tool to generate a PCB. The netlist is output as follows: @@ -606,6 +606,12 @@ You can also generate the netlist in XML format: This is useful in a KiCad environment where the XML file is used as the input to BOM-generation tools. +If you're designing with KiCad and want to skip some steps, you can go from +SKiDL directly to a PCB using the `generate_pcb()` function. +This will output a `.kicad_pcb` file that you can open in PCBNEW without +having to import the netlist. +But you will need to have KiCad installed since this option uses its +`pcbnew` Python library when building the PCB. # Going Deeper diff --git a/docs/static/documentation_options.js b/docs/static/documentation_options.js index 1dabe1d8..04dc5f70 100644 --- a/docs/static/documentation_options.js +++ b/docs/static/documentation_options.js @@ -1,6 +1,6 @@ var DOCUMENTATION_OPTIONS = { URL_ROOT: document.getElementById("documentation_options").getAttribute('data-url_root'), - VERSION: '1.0.0', + VERSION: '1.1.0', LANGUAGE: 'None', COLLAPSE_INDEX: false, BUILDER: 'singlehtml', diff --git a/setup.py b/setup.py index 11162758..9af3b447 100644 --- a/setup.py +++ b/setup.py @@ -5,7 +5,7 @@ import setuptools -__version__ = "1.0.0" +__version__ = "1.1.0" __author__ = "XESS Corp." __email__ = "info@xess.com" diff --git a/skidl/network.py b/skidl/network.py index c96a46d6..e1ed8055 100644 --- a/skidl/network.py +++ b/skidl/network.py @@ -129,10 +129,12 @@ def tee(ntwk): Create a network "tee" by returning the first terminal of a Network object. Then you can create tee'ed networks like so: vi & r1 & r2 & tee(r3 & r4 & gnd) & r5 & gnd which becomes: - vi---r1---r2-+-r5---gnd - | - | - r3---r4---gnd + + vi---r1---r2-+-r5---gnd + | + | + r3---r4---gnd + """ if not isinstance(ntwk, Network): # Convert an object into a Network if it isn't already. diff --git a/skidl/part.py b/skidl/part.py index f72779a3..047f2734 100644 --- a/skidl/part.py +++ b/skidl/part.py @@ -104,13 +104,6 @@ class Part(SkidlBaseObject): """ A class for storing a definition of a schematic part. - Attributes: - ref: String storing the reference of a part within a schematic (e.g., 'R5'). - value: String storing the part value (e.g., '3K3'). - footprint: String storing the PCB footprint associated with a part (e.g., SOIC-8). - pins: List of Pin objects for this part. - tag: A tag string to link a part to its footprint in a pcb editor. - Args: lib: Either a SchLib object or a schematic part library file name. name: A string with name of the part to find in the library, or to assign to diff --git a/skidl/pckg_info.py b/skidl/pckg_info.py index be31ef78..42447e90 100644 --- a/skidl/pckg_info.py +++ b/skidl/pckg_info.py @@ -1,3 +1,3 @@ -__version__ = "1.0.0" +__version__ = "1.1.0" __author__ = "XESS Corp." __email__ = "info@xess.com"