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etantilovmehmetb0
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idpf: add read memory barrier when checking descriptor done bit
BugLink: https://bugs.launchpad.net/bugs/2111953 [ Upstream commit 396f0165672c6a74d7379027d344b83b5f05948c ] Add read memory barrier to ensure the order of operations when accessing control queue descriptors. Specifically, we want to avoid cases where loads can be reordered: 1. Load #1 is dispatched to read descriptor flags. 2. Load #2 is dispatched to read some other field from the descriptor. 3. Load #2 completes, accessing memory/cache at a point in time when the DD flag is zero. 4. NIC DMA overwrites the descriptor, now the DD flag is one. 5. Any fields loaded before step 4 are now inconsistent with the actual descriptor state. Add read memory barrier between steps 1 and 2, so that load #2 is not executed until load #1 has completed. Fixes: 8077c72 ("idpf: add controlq init and reset checks") Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> Reviewed-by: Sridhar Samudrala <sridhar.samudrala@intel.com> Suggested-by: Lance Richardson <rlance@google.com> Signed-off-by: Emil Tantilov <emil.s.tantilov@intel.com> Tested-by: Krishneil Singh <krishneil.k.singh@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> Signed-off-by: Sasha Levin <sashal@kernel.org> Signed-off-by: Manuel Diewald <manuel.diewald@canonical.com> Signed-off-by: Mehmet Basaran <mehmet.basaran@canonical.com>
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drivers/net/ethernet/intel/idpf/idpf_controlq.c

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@@ -376,6 +376,9 @@ int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count,
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if (!(le16_to_cpu(desc->flags) & IDPF_CTLQ_FLAG_DD))
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break;
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/* Ensure no other fields are read until DD flag is checked */
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dma_rmb();
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/* strip off FW internal code */
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desc_err = le16_to_cpu(desc->ret_val) & 0xff;
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@@ -566,6 +569,9 @@ int idpf_ctlq_recv(struct idpf_ctlq_info *cq, u16 *num_q_msg,
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if (!(flags & IDPF_CTLQ_FLAG_DD))
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break;
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/* Ensure no other fields are read until DD flag is checked */
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dma_rmb();
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q_msg[i].vmvf_type = (flags &
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(IDPF_CTLQ_FLAG_FTYPE_VM |
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IDPF_CTLQ_FLAG_FTYPE_PF)) >>

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