@@ -318,6 +318,15 @@ ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
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return 0 ;
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}
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+ /* no mrr support for cards older than 5212 */
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+ static int
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+ ath5k_hw_setup_no_mrr (struct ath5k_hw * ah , struct ath5k_desc * desc ,
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+ unsigned int tx_rate1 , u_int tx_tries1 , u_int tx_rate2 ,
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+ u_int tx_tries2 , unsigned int tx_rate3 , u_int tx_tries3 )
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+ {
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+ return 0 ;
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+ }
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+
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/*
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* Proccess the tx status descriptor on 5210/5211
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*/
@@ -352,8 +361,10 @@ static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
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AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH );
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ts -> ts_antenna = 1 ;
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ts -> ts_status = 0 ;
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- ts -> ts_rate = AR5K_REG_MS (tx_ctl -> tx_control_0 ,
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+ ts -> ts_rate [ 0 ] = AR5K_REG_MS (tx_ctl -> tx_control_0 ,
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AR5K_2W_TX_DESC_CTL0_XMIT_RATE );
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+ ts -> ts_retry [0 ] = ts -> ts_longretry ;
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+ ts -> ts_final_idx = 0 ;
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if (!(tx_status -> tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK )) {
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if (tx_status -> tx_status_0 &
@@ -405,29 +416,43 @@ static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
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AR5K_DESC_TX_STATUS1_XMIT_ANTENNA ) ? 2 : 1 ;
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ts -> ts_status = 0 ;
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- switch (AR5K_REG_MS (tx_status -> tx_status_1 ,
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- AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX )) {
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- case 0 :
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- ts -> ts_rate = tx_ctl -> tx_control_3 &
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- AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 ;
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- break ;
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+ ts -> ts_final_idx = AR5K_REG_MS (tx_status -> tx_status_1 ,
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+ AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX );
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+
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+ /* The longretry counter has the number of un-acked retries
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+ * for the final rate. To get the total number of retries
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+ * we have to add the retry counters for the other rates
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+ * as well
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+ */
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+ ts -> ts_retry [ts -> ts_final_idx ] = ts -> ts_longretry ;
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+ switch (ts -> ts_final_idx ) {
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+ case 3 :
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+ ts -> ts_rate [3 ] = AR5K_REG_MS (tx_ctl -> tx_control_3 ,
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+ AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 );
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+
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+ ts -> ts_retry [2 ] = AR5K_REG_MS (tx_ctl -> tx_control_2 ,
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+ AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 );
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+ ts -> ts_longretry += ts -> ts_retry [2 ];
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+ /* fall through */
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+ case 2 :
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+ ts -> ts_rate [2 ] = AR5K_REG_MS (tx_ctl -> tx_control_3 ,
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+ AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 );
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+
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+ ts -> ts_retry [1 ] = AR5K_REG_MS (tx_ctl -> tx_control_2 ,
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+ AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 );
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+ ts -> ts_longretry += ts -> ts_retry [1 ];
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+ /* fall through */
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case 1 :
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- ts -> ts_rate = AR5K_REG_MS (tx_ctl -> tx_control_3 ,
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+ ts -> ts_rate [ 1 ] = AR5K_REG_MS (tx_ctl -> tx_control_3 ,
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AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 );
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- ts -> ts_longretry += AR5K_REG_MS (tx_ctl -> tx_control_2 ,
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+
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+ ts -> ts_retry [0 ] = AR5K_REG_MS (tx_ctl -> tx_control_2 ,
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AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 );
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- break ;
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- case 2 :
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- ts -> ts_rate = AR5K_REG_MS (tx_ctl -> tx_control_3 ,
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- AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 );
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- ts -> ts_longretry += AR5K_REG_MS (tx_ctl -> tx_control_2 ,
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- AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 );
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- break ;
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- case 3 :
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- ts -> ts_rate = AR5K_REG_MS (tx_ctl -> tx_control_3 ,
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- AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 );
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- ts -> ts_longretry += AR5K_REG_MS (tx_ctl -> tx_control_2 ,
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- AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 );
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+ ts -> ts_longretry += ts -> ts_retry [0 ];
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+ /* fall through */
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+ case 0 :
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+ ts -> ts_rate [0 ] = tx_ctl -> tx_control_3 &
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+ AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 ;
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break ;
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}
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@@ -653,7 +678,7 @@ int ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
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} else {
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ah -> ah_setup_rx_desc = ath5k_hw_setup_rx_desc ;
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ah -> ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc ;
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- ah -> ah_setup_mrr_tx_desc = ath5k_hw_setup_mrr_tx_desc ;
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+ ah -> ah_setup_mrr_tx_desc = ath5k_hw_setup_no_mrr ;
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ah -> ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status ;
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}
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