Performance: BlockTile 256x128 optimizations enable 1500+ TF FP8

[sazczmh]

By resuing the Accumulator registers of Tensor Cores to implement a 256x128 BlockTile structure, this approach significantly increases data reuse, reduces the demand for L2 Cache and HBM memory accesses, and enhances the SM's computational frequency, ultimately achieving FP8 performance exceeding 1,500+ TFLOPS.

M	N	K	Base BMxBN	Computation	Opti BMxBN	Computation	Speedup
4096	24576	1536	128x160	1162 TF	256x128	1204 TF	3.61%
4096	32768	512	128x160	801 TF	256x128	777 TF	-3.00%
4096	7168	16384	128x160	1451 TF	256x128	1500 TF	3.38%
4096	4096	7168	128x160	1304 TF	256x128	1377 TF	5.60%
4096	7168	2048	128x160	1185 TF	256x128	1159 TF	-2.19%

Test on “H800”-SXM && CUDA 12.8.1