PCM_MLC_example.config

; Memory configuration file examples 
; This configuration file is based on Samsung's 2012 ISSCC paper:
;     A 20nm 1.8V 8Gb PRAM with 40MB/s Program Bandwidth
; 
; Phase Change Memory has a very high resistance ratio, allowing for 
; global sense amplifiers. This configuration assumes global sense
; amplifiers, which decrease area at the cost of increased tRCD.
; 
; We assume 256-bit row buffer based on up to 256-bit program width
; in each half, and that each half is an independent bank.
; 
; We also assume each chip acts as a single x8 device with an LPDDR
; interface (not LPDDR-N).
;
 
;================================================================================
; Interface specifications

; 400 MHz clock (800 MT/s LPDDR). Clock period = 1.5 ns
CLK 400

; Data Rate. 1 for SDR, 2 for DDR
RATE 2

; Bus width in bits. JEDEC standard is 64-bits
BusWidth 64

; Number of bits provided by each device in a rank
; Number of devices is calculated using BusWidth / DeviceWidth.
DeviceWidth 8

; NVMain use CLK and CPUFreq to do the synchronization. The ratio CLK/CPUFreq
; is actually used. So a simple CLK=1 and CPUFreq=4 still works for simulation. 
; However, it is straightforward to make it informative.
CPUFreq 2000
;================================================================================

;********************************************************************************
; General memory system configuration

; Number of banks per rank (used to be 2.Hugo Zhang)
BANKS 1

; Number of ranks per channel
RANKS 1

; Number of channels in the system
CHANNELS 1

; Number of rows in one bank
ROWS 65536 ; 8 partitions * 2 vertical tiles per partition * 4096 WL per tile

; Number of VISIBLE columns in one LOGIC bank 
COLS 1024 ; 32 horizontal tiles * 2048 bitlines / (8 device width * 8 burst cycles)

; Assume one large mat (no local sense amplifiers)
MATHeight 65536

; RBsize
RBsize 256

; No refresh needed in PCM
UseRefresh false

; Not used in PCM, but we'll assign valid numbers anyway.
BanksPerRefresh 2
RefreshRows 4
DelayedRefreshThreshold 1

;********************************************************************************

;================================================================================
; Memory device timing parameters (in memory cycle) 

tBURST 4 ; length of data burst

tCMD 1   ; Commands are 1 address bus cycle
tRAS 0   ; No row restoration needed
tRCD 48  ; 120ns @ 400 MHz = 48 cycles
tWP0 40  ; RESET pulse time. 100ns @ 400 MHz = 40 cycles
tWP1 60  ; SET pulse time. 150ns @ 400 MHz = 60 cycles
tRP 1    ; Precharge isn't needed. Writes occur only if needed
         ; and take tWP time during a precharge (write-back)
         ; or immediately (write-through)
tCAS 1   ; Assumes data is ready at the global sense amps after tRCD
tAL 0    ; 0 or 1
tCCD 2   ; usually 2 or 4, no more than tBURST

; The next set of timings is mainly based on control circuits, and the times
; are taken from normal LPDDR2 datasheets.
tCWD 4   ; 10ns
tWTR 3   ; 7.5ns
tWR 0    ; i.e., write-to-precharge, not needed here
tRTRS 1  ; for DDR-1, tRTRS can be 0
tRTP 3   ; No precharge, but still need to wait for data to leave internal
         ; FIFO buffers
tOST 0   ; No ODT circuitry in LPDDR

; These are mostly unknown at this point, but will likely
; be similar as they are meant to preserve power integrity
tRRDR 4 
tRRDW 4
RAW 4
tRAW 20

; Powerdown entry and exit timings
tRDPDEN 5     ; Wait for read to complete - tCAS + tBURST
tWRPDEN 68    ; Wait for write to complete ... tAL + tCWD + tBURST + tWP 
tWRAPDEN 68   ; No precharge, so same as tWRPDEN
tPD 1         ; Time from powerdown command to actually in powerdown mode
tXP 3         ; Time to power-up from power-down mode - 7.5ns
tXPDLL 200000 ; No DLL in LPDDR, will be used for deep power-down (tDPD) - 500us

; Refresh timings - not used in PCM, but we'll assign valid numbers anyway.
tRFC 100
tREFW 42666667
;================================================================================

;================================================================================
; MLC Parameters

MLCLevels 2
UniformWrites false

Ereset 0.054331 ; NVSIM estimate across CELL
Eset 0.101581   ; NVSIM estimate across CELL

WPVariance 1
nWP00 0
nWP01 7
nWP10 5
nWP11 1

;================================================================================

;********************************************************************************
; Memory device energy and power parameters
 
; Read/write values are in nano Joules
; NOTES:
;   NVSIM energy is per word
;   Erd is the read energy from a single mat
;   Ewr is the write energy (SET or RESET, they are the same)
;   These values are the energys required to read a page into a row buffer.
;
;   Other energy values are taken from CACTI
;
EnergyModel energy
Erd 0.081200 
Eopenrd 0.001616
Ewr 1.684811

; Subarray write energy per bit
Ewrpb = 0.000202

; Energy leaked in 1 sec (or just the wattage) in milli Joules 
Eleak 3120.202

Epdpf 0
Epdps 0
Epda 0
Eref 0

; DRAM style power calculation. All values below in mA, taken from datasheet.

Voltage 1.5
;********************************************************************************

;================================================================================
; Memory controller parameters

; Specify which memory controller to use
; options: PerfectMemory, FCFS, FRFCFS, FRFCFS-WQF, DRC (for 3D DRAM Cache)
MEM_CTL FRFCFS

; whether use close-page row buffer management policy?
; options: 
;   0--Open-Page, the row will be closed until a row buffer miss occurs
;   1--Relaxed Close-Page, the row will be closed if no other row buffer hit exists
;   2--Restricted Close-Page, the row will be closed immediately, no row
;      buffer hit can be exploited
ClosePage 0

; command scheduling scheme
; options: 0--fixed priority, 1--rank first round-robin, 2--bank first round-robin
ScheduleScheme 2

; address mapping scheme
; options: R:RK:BK:CH:C (R-row, C:column, BK:bank, RK:rank, CH:channel)
AddressMappingScheme R:RK:BK:CH:C

; interconnect between controller and memory chips
; options: OffChipBus (for 2D), OnChipBus (for 3D)
INTERCONNECT OffChipBus

; FRFCFS-WQF specific parameters
ReadQueueSize 32 ; read queue size
WriteQueueSize 32 ; write queue size
HighWaterMark 32 ; write drain high watermark. write drain is triggerred if it is reached
LowWaterMark 16 ; write drain low watermark. write drain is stopped if it is reached
;================================================================================

;********************************************************************************
; Simulation control parameters
;
PrintGraphs false
PrintPreTrace false
PreTraceFile pcm.trace
EchoPreTrace false
PeriodicStatsInterval 100000000
FlipNWriteGranularity 16
aFPCGranularity 2

TraceReader NVMainTrace
;********************************************************************************

;================================================================================
; Endurance model parameters
; This is used for Non-volatile memory

EnduranceModel NullModel
EnduranceDist Normal
EnduranceDistMean 1000000 
EnduranceDistVariance  100000

; Everything below this can be overridden for heterogeneous channels
;CONFIG_CHANNEL0 pcm_channel0.config
;CONFIG_CHANNEL1 pcm_channel1.config

; Set the memory is in powerdown mode at the beginning?
InitPD false
;================================================================================

; AddHook RequestTracer
DataEncoder aFNW

; AddGranularity (added in Endurance model parameter by Hugo)