[vm] Remove deprecated (and untested) ARMv5 support from the VM

Since we have no CQ/CI test coverage of ARMv5 and none of our customers
uses it, a breaking change request was made (see issue further down).

The breaking change has been approved and a corresponding email has been
sent out:

https://groups.google.com/a/dartlang.org/forum/?nomobile=true#!topic/announce/vRQja7di3FQ

This CL removes any armv5 related code from our codebase.

Closes #36666

Change-Id: I9abf32f1980ca19a9cf882b43c9966b2127f89e3
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/122540
Reviewed-by: Ryan Macnak <rmacnak@google.com>
Commit-Queue: Martin Kustermann <kustermann@google.com>

Author: mkustermann

pkg/dev_compiler/tool/ddc

@@ -30,8 +30,7 @@ then
   DIRS=$( ls "$OUT_DIR" )
   # list of possible configurations in decreasing desirability
   CONFIGS=("ReleaseX64" "ReleaseIA32" "DebugX64" "DebugIA32"
-    "ReleaseARM"    "ReleaseARM64"    "ReleaseARMV5TE"
-    "DebugARM"      "DebugARM64"      "DebugARMV5TE")
+    "ReleaseARM" "ReleaseARM64" "DebugARM" "DebugARM64")
   DART_CONFIGURATION="None"
   for CONFIG in ${CONFIGS[*]}
   do

pkg/pkg.status

@@ -210,7 +210,7 @@ analyzer/test/src/task/strong/front_end_inference_test: Slow
 
 # Timeout. These tests do not run efficiently on our simulator or low-end
 # devices.
-[ $runtime == vm && ($arch == armv5te || $arch == armv6 || $arch == simarm || $arch == simarm64 || $arch == simarmv5te || $arch == simarmv6 || $arch == simdbc64) ]
+[ $runtime == vm && ($arch == armv6 || $arch == simarm || $arch == simarm64 || $arch == simarmv6 || $arch == simdbc64) ]
 *: Skip
 
 [ $arch != x64 || $compiler != none || $mode != release || $runtime != vm ]

pkg/smith/lib/configuration.dart

@@ -553,11 +553,9 @@ class Architecture extends NamedEnum {
   static const arm = Architecture._('arm');
   static const arm_x64 = Architecture._('arm_x64');
   static const armv6 = Architecture._('armv6');
-  static const armv5te = Architecture._('armv5te');
   static const arm64 = Architecture._('arm64');
   static const simarm = Architecture._('simarm');
   static const simarmv6 = Architecture._('simarmv6');
-  static const simarmv5te = Architecture._('simarmv5te');
   static const simarm64 = Architecture._('simarm64');
   static const simdbc = Architecture._('simdbc');
   static const simdbc64 = Architecture._('simdbc64');
@@ -569,12 +567,10 @@ class Architecture extends NamedEnum {
     x64,
     arm,
     armv6,
-    armv5te,
     arm_x64,
     arm64,
     simarm,
     simarmv6,
-    simarmv5te,
     simarm64,
     simdbc,
     simdbc64

pkg/status_file/test/data/vm.status

@@ -51,7 +51,7 @@ cc/Read: Fail  # TODO(zra): Investigate, ../../dart/runtime/bin/file_test.cc: 34
 # On the simluator stack traces produced by the Profiler do not match
 # up with the real Dart stack trace and hence we don't get correct
 # symbol names.
-[ $arch == simarm || $arch == simarmv6 || $arch == simarmv5te || $arch == simarm64 || $arch == simdbc  || $arch == simdbc64 ]
+[ $arch == simarm || $arch == simarmv6 || $arch == simarm64 || $arch == simdbc  || $arch == simdbc64 ]
 cc/Service_Profile: Skip
 cc/Profiler_AllocationSampleTest: Skip
 cc/Profiler_ArrayAllocation: Skip

pkg/test_runner/lib/src/options.dart

@@ -141,8 +141,8 @@ none:             No runtime, compile only.''',
 Allowed values are:
 all
 ia32, x64
-arm, armv6, armv5te, arm64,
-simarm, simarmv6, simarmv5te, simarm64,
+arm, armv6, arm64,
+simarm, simarmv6, simarm64,
 simdbc, simdbc64, arm_x64''',
         abbr: 'a',
         values: ['all']..addAll(Architecture.names),

pkg/test_runner/lib/src/runtime_configuration.dart

@@ -233,8 +233,6 @@ class DartVmRuntimeConfiguration extends RuntimeConfiguration {
       case Architecture.arm64:
       case Architecture.simarmv6:
       case Architecture.armv6:
-      case Architecture.simarmv5te:
-      case Architecture.armv5te:
       case Architecture.simarm64:
       case Architecture.simdbc:
       case Architecture.simdbc64:

runtime/BUILD.gn

@@ -100,9 +100,6 @@ config("dart_arch_config") {
   } else if (dart_target_arch == "armv6") {
     defines += [ "TARGET_ARCH_ARM" ]
     defines += [ "TARGET_ARCH_ARM_6" ]
-  } else if (dart_target_arch == "armv5te") {
-    defines += [ "TARGET_ARCH_ARM" ]
-    defines += [ "TARGET_ARCH_ARM_5TE" ]
   } else if (dart_target_arch == "arm64") {
     defines += [ "TARGET_ARCH_ARM64" ]
   } else if (dart_target_arch == "x64") {

runtime/platform/globals.h

@@ -419,12 +419,6 @@ typedef simd128_value_t fpu_register_t;
 #define DUAL_MAPPING_SUPPORTED 1
 #endif
 
-// Disable background threads by default on armv5te. The relevant
-// implementations are uniprocessors.
-#if !defined(TARGET_ARCH_ARM_5TE)
-#define ARCH_IS_MULTI_CORE 1
-#endif
-
 // Short form printf format specifiers
 #define Pd PRIdPTR
 #define Pu PRIuPTR

runtime/tests/vm/vm.status

@@ -192,7 +192,7 @@ cc/GenKernelKernelReadAllBytecode: SkipByDesign # No interpreter support.
 # On the simluator stack traces produced by the Profiler do not match
 # up with the real Dart stack trace and hence we don't get correct
 # symbol names.
-[ $arch == simarm || $arch == simarm64 || $arch == simarmv5te || $arch == simarmv6 || $arch == simdbc || $arch == simdbc64 ]
+[ $arch == simarm || $arch == simarm64 || $arch == simarmv6 || $arch == simdbc || $arch == simdbc64 ]
 cc/LargeMap: SkipByDesign
 cc/Profiler_AllocationSampleTest: SkipByDesign
 cc/Profiler_ArrayAllocation: SkipByDesign

runtime/vm/compiler/assembler/assembler_arm.cc

@@ -418,15 +418,8 @@ void Assembler::umaal(Register rd_lo,
   ASSERT(rd_hi != IP);
   ASSERT(rn != IP);
   ASSERT(rm != IP);
-  if (TargetCPUFeatures::arm_version() != ARMv5TE) {
-    // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
-    EmitMulOp(AL, B22, rd_lo, rd_hi, rn, rm);
-  } else {
-    mov(IP, Operand(0));
-    umlal(rd_lo, IP, rn, rm);
-    adds(rd_lo, rd_lo, Operand(rd_hi));
-    adc(rd_hi, IP, Operand(0));
-  }
+  // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
+  EmitMulOp(AL, B22, rd_lo, rd_hi, rn, rm);
 }
 
 void Assembler::EmitDivOp(Condition cond,
@@ -493,12 +486,7 @@ void Assembler::ldrd(Register rd,
                      Condition cond) {
   ASSERT((rd % 2) == 0);
   ASSERT(rd2 == rd + 1);
-  if (TargetCPUFeatures::arm_version() == ARMv5TE) {
-    ldr(rd, Address(rn, offset), cond);
-    ldr(rd2, Address(rn, offset + target::kWordSize), cond);
-  } else {
-    EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, Address(rn, offset));
-  }
+  EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, Address(rn, offset));
 }
 
 void Assembler::strd(Register rd,
@@ -508,12 +496,7 @@ void Assembler::strd(Register rd,
                      Condition cond) {
   ASSERT((rd % 2) == 0);
   ASSERT(rd2 == rd + 1);
-  if (TargetCPUFeatures::arm_version() == ARMv5TE) {
-    str(rd, Address(rn, offset), cond);
-    str(rd2, Address(rn, offset + target::kWordSize), cond);
-  } else {
-    EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, Address(rn, offset));
-  }
+  EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, Address(rn, offset));
 }
 
 void Assembler::ldm(BlockAddressMode am,
@@ -533,7 +516,6 @@ void Assembler::stm(BlockAddressMode am,
 }
 
 void Assembler::ldrex(Register rt, Register rn, Condition cond) {
-  ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE);
   ASSERT(rn != kNoRegister);
   ASSERT(rt != kNoRegister);
   ASSERT(cond != kNoCondition);
@@ -545,7 +527,6 @@ void Assembler::ldrex(Register rt, Register rn, Condition cond) {
 }
 
 void Assembler::strex(Register rd, Register rt, Register rn, Condition cond) {
-  ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE);
   ASSERT(rn != kNoRegister);
   ASSERT(rd != kNoRegister);
   ASSERT(rt != kNoRegister);
@@ -562,7 +543,7 @@ void Assembler::EnterSafepoint(Register addr, Register state) {
   // We generate the same number of instructions whether or not the slow-path is
   // forced. This simplifies GenerateJitCallbackTrampolines.
   Label slow_path, done, retry;
-  if (FLAG_use_slow_path || TargetCPUFeatures::arm_version() == ARMv5TE) {
+  if (FLAG_use_slow_path) {
     b(&slow_path);
   }
 
@@ -578,7 +559,7 @@ void Assembler::EnterSafepoint(Register addr, Register state) {
   cmp(TMP, Operand(0));  // 0 means strex was successful.
   b(&done, EQ);
 
-  if (!FLAG_use_slow_path && TargetCPUFeatures::arm_version() != ARMv5TE) {
+  if (!FLAG_use_slow_path) {
     b(&retry);
   }
 
@@ -614,7 +595,7 @@ void Assembler::ExitSafepoint(Register addr, Register state) {
   // We generate the same number of instructions whether or not the slow-path is
   // forced, for consistency with EnterSafepoint.
   Label slow_path, done, retry;
-  if (FLAG_use_slow_path || TargetCPUFeatures::arm_version() == ARMv5TE) {
+  if (FLAG_use_slow_path) {
     b(&slow_path);
   }
 
@@ -630,7 +611,7 @@ void Assembler::ExitSafepoint(Register addr, Register state) {
   cmp(TMP, Operand(0));  // 0 means strex was successful.
   b(&done, EQ);
 
-  if (!FLAG_use_slow_path && TargetCPUFeatures::arm_version() != ARMv5TE) {
+  if (!FLAG_use_slow_path) {
     b(&retry);
   }
 
@@ -673,7 +654,6 @@ void Assembler::TransitionNativeToGenerated(Register addr,
 }
 
 void Assembler::clrex() {
-  ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE);
   int32_t encoding = (kSpecialCondition << kConditionShift) | B26 | B24 | B22 |
                      B21 | B20 | (0xff << 12) | B4 | 0xf;
   Emit(encoding);
@@ -894,13 +874,13 @@ void Assembler::EmitMultiVDMemOp(Condition cond,
   ASSERT(cond != kNoCondition);
   ASSERT(start != kNoDRegister);
   ASSERT(static_cast<int32_t>(start) + count <= kNumberOfDRegisters);
-  const int armv5te = TargetCPUFeatures::arm_version() == ARMv5TE ? 1 : 0;
+  const int notArmv5te = 0;
 
   int32_t encoding =
       (static_cast<int32_t>(cond) << kConditionShift) | B27 | B26 | B11 | B9 |
       B8 | am | (load ? L : 0) | ArmEncode::Rn(base) |
       ((static_cast<int32_t>(start) & 0x10) ? D : 0) |
-      ((static_cast<int32_t>(start) & 0xf) << 12) | (count << 1) | armv5te;
+      ((static_cast<int32_t>(start) & 0xf) << 12) | (count << 1) | notArmv5te;
   Emit(encoding);
 }
 
@@ -2075,7 +2055,7 @@ class PatchFarBranch : public AssemblerFixup {
 
   void Process(const MemoryRegion& region, intptr_t position) {
     const ARMVersion version = TargetCPUFeatures::arm_version();
-    if ((version == ARMv5TE) || (version == ARMv6)) {
+    if (version == ARMv6) {
       ProcessARMv6(region, position);
     } else {
       ASSERT(version == ARMv7);
@@ -2329,7 +2309,7 @@ void Assembler::BindARMv7(Label* label) {
 
 void Assembler::Bind(Label* label) {
   const ARMVersion version = TargetCPUFeatures::arm_version();
-  if ((version == ARMv5TE) || (version == ARMv6)) {
+  if (version == ARMv6) {
     BindARMv6(label);
   } else {
     ASSERT(version == ARMv7);
@@ -2788,7 +2768,7 @@ void Assembler::LoadPatchableImmediate(Register rd,
                                        int32_t value,
                                        Condition cond) {
   const ARMVersion version = TargetCPUFeatures::arm_version();
-  if ((version == ARMv5TE) || (version == ARMv6)) {
+  if (version == ARMv6) {
     // This sequence is patched in a few places, and should remain fixed.
     const uint32_t byte0 = (value & 0x000000ff);
     const uint32_t byte1 = (value & 0x0000ff00) >> 8;
@@ -2811,7 +2791,7 @@ void Assembler::LoadDecodableImmediate(Register rd,
                                        int32_t value,
                                        Condition cond) {
   const ARMVersion version = TargetCPUFeatures::arm_version();
-  if ((version == ARMv5TE) || (version == ARMv6)) {
+  if (version == ARMv6) {
     if (constant_pool_allowed()) {
       const int32_t offset =
           target::ObjectPool::element_offset(FindImmediate(value));