diff --git a/hardware/vdp/vdp_sprite_core.v b/hardware/vdp/vdp_sprite_core.v
index 7947d37..8ce6774 100644
--- a/hardware/vdp/vdp_sprite_core.v
+++ b/hardware/vdp/vdp_sprite_core.v
@@ -187,7 +187,7 @@ module vdp_sprite_core #(
     // off: offscreen - being rendered to
 
     wire [9:0] line_buffer_write_address;
-    wire [11:0] line_buffer_data_in;
+    wire [9:0] line_buffer_write_data;
     wire line_buffer_write_en;
 
     wire [9:0] line_buffer_clear_write_address;
@@ -195,22 +195,22 @@ module vdp_sprite_core #(
 
     // --- Line buffers ---
 
-    wire [23:0] line_buffer_data_out;
-    wire [11:0] line_buffer_data_out_0 = line_buffer_data_out[11:0];
-    wire [11:0] line_buffer_data_out_1 = line_buffer_data_out[23:12];
+    wire [19:0] line_buffer_data_out;
+    wire [9:0] line_buffer_data_out_0 = line_buffer_data_out[9:0];
+    wire [9:0] line_buffer_data_out_1 = line_buffer_data_out[19:10];
 
     generate
         for (i = 0; i < 2; i = i + 1) begin : line_buffer_gen
             wire select = line_buffer_select ^ i;
 
             wire [9:0] write_address = select ? line_buffer_write_address : line_buffer_clear_write_address;
-            wire [11:0] write_data = select ? line_buffer_data_in : line_buffer_clear_data_in;
+            wire [9:0] write_data = select ? line_buffer_write_data : line_buffer_clear_data_in;
             wire write_en = select ? line_buffer_write_en : line_buffer_clear_en;
 
-            reg [11:0] line_buffer [0:1023];
-            reg [11:0] read_data;
+            reg [9:0] line_buffer [0:1023];
+            reg [9:0] read_data;
 
-            assign line_buffer_data_out[i * 12 + 11 : i * 12] = read_data;
+            assign line_buffer_data_out[i * 10+:10] = read_data;
 
             always @(posedge clk) begin
                 if (write_en) begin
@@ -226,7 +226,7 @@ module vdp_sprite_core #(
 
     reg [9:0] line_buffer_previous_read_address;
     assign line_buffer_clear_write_address = line_buffer_previous_read_address;
-    wire [12:0] line_buffer_clear_data_in = 12'h000;
+    wire [9:0] line_buffer_clear_data_in = 10'b0;
 
     assign line_buffer_clear_en = 1;
 
@@ -317,7 +317,7 @@ module vdp_sprite_core #(
         .flip_x(x_block_data_out[10]),
 
         .line_buffer_write_address(line_buffer_write_address),
-        .line_buffer_write_data(line_buffer_data_in),
+        .line_buffer_write_data(line_buffer_write_data),
         .line_buffer_write_en(line_buffer_write_en),
         
         .hit_list_read_address(hit_list_blitter_read_address),
diff --git a/hardware/vdp/vdp_sprite_render.v b/hardware/vdp/vdp_sprite_render.v
index ae82cf2..ddaf787 100644
--- a/hardware/vdp/vdp_sprite_render.v
+++ b/hardware/vdp/vdp_sprite_render.v
@@ -14,7 +14,7 @@ module vdp_sprite_render(
 
     // line buffer writing
     output reg [9:0] line_buffer_write_address,
-    output reg [12:0] line_buffer_write_data,
+    output reg [9:0] line_buffer_write_data,
     output reg line_buffer_write_en,
 
     // prefetch reading
diff --git a/hardware/vdp/vdp_vram_bus_arbiter_standard.v b/hardware/vdp/vdp_vram_bus_arbiter_standard.v
index 9e0e916..7d45fac 100644
--- a/hardware/vdp/vdp_vram_bus_arbiter_standard.v
+++ b/hardware/vdp/vdp_vram_bus_arbiter_standard.v
@@ -158,7 +158,6 @@ module vdp_vram_bus_arbiter_standard(
     reg [15:0] scroll_map_data_hold [0:3];
 
     wire [3:0] palette_selected = map_selected_word[15:12];
-    wire x_flip_selected = map_selected_word[9];
 
     // A delay is needed on the VRAM word select since the fetches are pipelined