@@ -297,68 +297,6 @@ static u32 twenty_five_base_hpt36x[] = {
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/* XFER_PIO_0 */ 0xc0d08585
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};
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- #if 0
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- /* These are the timing tables from the HighPoint open source drivers... */
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- static u32 thirty_three_base_hpt37x [] = {
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- /* XFER_UDMA_6 */ 0x12446231 , /* 0x12646231 ?? */
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- /* XFER_UDMA_5 */ 0x12446231 ,
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- /* XFER_UDMA_4 */ 0x12446231 ,
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- /* XFER_UDMA_3 */ 0x126c6231 ,
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- /* XFER_UDMA_2 */ 0x12486231 ,
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- /* XFER_UDMA_1 */ 0x124c6233 ,
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- /* XFER_UDMA_0 */ 0x12506297 ,
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-
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- /* XFER_MW_DMA_2 */ 0x22406c31 ,
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- /* XFER_MW_DMA_1 */ 0x22406c33 ,
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- /* XFER_MW_DMA_0 */ 0x22406c97 ,
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-
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- /* XFER_PIO_4 */ 0x06414e31 ,
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- /* XFER_PIO_3 */ 0x06414e42 ,
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- /* XFER_PIO_2 */ 0x06414e53 ,
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- /* XFER_PIO_1 */ 0x06814e93 ,
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- /* XFER_PIO_0 */ 0x06814ea7
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- };
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-
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- static u32 fifty_base_hpt37x [] = {
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- /* XFER_UDMA_6 */ 0x12848242 ,
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- /* XFER_UDMA_5 */ 0x12848242 ,
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- /* XFER_UDMA_4 */ 0x12ac8242 ,
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- /* XFER_UDMA_3 */ 0x128c8242 ,
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- /* XFER_UDMA_2 */ 0x120c8242 ,
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- /* XFER_UDMA_1 */ 0x12148254 ,
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- /* XFER_UDMA_0 */ 0x121882ea ,
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-
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- /* XFER_MW_DMA_2 */ 0x22808242 ,
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- /* XFER_MW_DMA_1 */ 0x22808254 ,
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- /* XFER_MW_DMA_0 */ 0x228082ea ,
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-
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- /* XFER_PIO_4 */ 0x0a81f442 ,
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- /* XFER_PIO_3 */ 0x0a81f443 ,
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- /* XFER_PIO_2 */ 0x0a81f454 ,
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- /* XFER_PIO_1 */ 0x0ac1f465 ,
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- /* XFER_PIO_0 */ 0x0ac1f48a
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- };
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-
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- static u32 sixty_six_base_hpt37x [] = {
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- /* XFER_UDMA_6 */ 0x1c869c62 ,
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- /* XFER_UDMA_5 */ 0x1cae9c62 , /* 0x1c8a9c62 */
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- /* XFER_UDMA_4 */ 0x1c8a9c62 ,
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- /* XFER_UDMA_3 */ 0x1c8e9c62 ,
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- /* XFER_UDMA_2 */ 0x1c929c62 ,
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- /* XFER_UDMA_1 */ 0x1c9a9c62 ,
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- /* XFER_UDMA_0 */ 0x1c829c62 ,
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-
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- /* XFER_MW_DMA_2 */ 0x2c829c62 ,
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- /* XFER_MW_DMA_1 */ 0x2c829c66 ,
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- /* XFER_MW_DMA_0 */ 0x2c829d2e ,
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-
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- /* XFER_PIO_4 */ 0x0c829c62 ,
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- /* XFER_PIO_3 */ 0x0c829c84 ,
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- /* XFER_PIO_2 */ 0x0c829ca6 ,
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- /* XFER_PIO_1 */ 0x0d029d26 ,
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- /* XFER_PIO_0 */ 0x0d029d5e
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- };
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- #else
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/*
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* The following are the new timing tables with PIO mode data/taskfile transfer
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* overclocking fixed...
@@ -424,7 +362,6 @@ static u32 sixty_six_base_hpt37x[] = {
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/* XFER_PIO_1 */ 0x0d02ff26 ,
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/* XFER_PIO_0 */ 0x0d42ff7f
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};
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- #endif
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#define HPT371_ALLOW_ATA133_6 1
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#define HPT302_ALLOW_ATA133_6 1
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