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[Intel] Added method CLOCK_FLEX_MAX with Xeon's Nehalem & Core 2
* Grants full `MSR_FLEX_RATIO` access to tested architectures: - Alder Lake/S - Tiger Lake/U - Westmere/Gulftown
1 parent db15a83 commit f622261

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7 files changed

+136
-111
lines changed

7 files changed

+136
-111
lines changed

‎x86_64/corefreq-cli-rsc-en.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -855,6 +855,7 @@
855855
#define RSC_RATIO_CODE_EN "Ratio"
856856
#define RSC_FACTORY_CODE_EN "Factory"
857857
#define RSC_OVERCLOCK_CODE_EN "Overclock"
858+
#define RSC_OC_BINS_COMM_CODE_EN " OC_BINS [0:disabled ... 7:unlimited] "
858859
#define RSC_PERFORMANCE_CODE_EN "Performance"
859860
#define RSC_TARGET_CODE_EN "Target"
860861
#define RSC_LEVEL_CODE_EN "Level"
@@ -1261,6 +1262,7 @@
12611262
#define RSC_TECH_INTEL_VTD_COMM_CODE_EN " I/O MMU virtualization (Intel VT-d) "
12621263
#define RSC_TECH_AMD_V_COMM_CODE_EN " I/O MMU virtualization (AMD-Vi) "
12631264
#define RSC_TECH_HDCP_COMM_CODE_EN " High-Bandwidth Digital Content Protection "
1265+
#define RSC_TECH_OC_COMM_CODE_EN " If OC_ENABLED then MSR FLEX_RATIO.OC_BINS "
12641266

12651267
#define RSC_PERF_MON_TITLE_CODE_EN " Performance Monitoring "
12661268
#define RSC_PERF_CAPS_TITLE_CODE_EN " Performance Capabilities "

‎x86_64/corefreq-cli-rsc-fr.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -358,6 +358,9 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
358358
#define RSC_RATIO_CODE_FR "Ratio"
359359
#define RSC_FACTORY_CODE_FR "Usine"
360360
#define RSC_OVERCLOCK_CODE_FR "Overclock"
361+
#define RSC_OC_BINS_COMM_CODE_FR \
362+
" OC_BINS [0:d""\xa9""sactiv""\xa9"" ... 7:illimit""\xa9""] "
363+
361364
#define RSC_PERFORMANCE_CODE_FR "Performance"
362365
#define RSC_TARGET_CODE_FR "Cible"
363366
#define RSC_LEVEL_CODE_FR "Niveau"
@@ -741,6 +744,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
741744
#define RSC_TECH_INTEL_VTD_COMM_CODE_FR RSC_TECH_INTEL_VTD_COMM_CODE_EN
742745
#define RSC_TECH_AMD_V_COMM_CODE_FR RSC_TECH_AMD_V_COMM_CODE_EN
743746
#define RSC_TECH_HDCP_COMM_CODE_FR RSC_TECH_HDCP_COMM_CODE_EN
747+
#define RSC_TECH_OC_COMM_CODE_FR " Si OC_ENABLED alors MSR FLEX_RATIO.OC_BINS "
744748

745749
#define RSC_PERF_MON_TITLE_CODE_FR " Gestion de la performance "
746750
#define RSC_PERF_CAPS_TITLE_CODE_FR " Capacit""\xa9""s de performances "

‎x86_64/corefreq-cli-rsc.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -554,6 +554,7 @@ RESOURCE_ST Resource[] = {
554554
LDT(RSC_RATIO),
555555
LDT(RSC_FACTORY),
556556
LDT(RSC_OVERCLOCK),
557+
LDT(RSC_OC_BINS_COMM),
557558
LDT(RSC_PERFORMANCE),
558559
LDT(RSC_TARGET),
559560
LDT(RSC_LEVEL),
@@ -1160,6 +1161,7 @@ RESOURCE_ST Resource[] = {
11601161
LDT(RSC_TECHNOLOGIES_IPU),
11611162
LDT(RSC_TECHNOLOGIES_VPU),
11621163
LDT(RSC_TECHNOLOGIES_OC),
1164+
LDT(RSC_TECH_OC_COMM),
11631165
LDT(RSC_PERF_MON_TITLE),
11641166
LDT(RSC_PERF_CAPS_TITLE),
11651167
LDT(RSC_VERSION),

‎x86_64/corefreq-cli-rsc.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -357,6 +357,7 @@ enum {
357357
RSC_RATIO,
358358
RSC_FACTORY,
359359
RSC_OVERCLOCK,
360+
RSC_OC_BINS_COMM,
360361
RSC_PERFORMANCE,
361362
RSC_TARGET,
362363
RSC_LEVEL,
@@ -963,6 +964,7 @@ enum {
963964
RSC_TECHNOLOGIES_IPU,
964965
RSC_TECHNOLOGIES_VPU,
965966
RSC_TECHNOLOGIES_OC,
967+
RSC_TECH_OC_COMM,
966968
RSC_PERF_MON_TITLE,
967969
RSC_PERF_CAPS_TITLE,
968970
RSC_VERSION,

‎x86_64/corefreq-cli.c‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1357,11 +1357,12 @@ REASON_CODE SysInfoProc(Window *win,
13571357
RO(Shm)->Proc.Features.OC_Lock ?
13581358
RSC(LOCK).CODE() : RSC(UNLOCK).CODE() );
13591359

1360-
PUT( SCANKEY_NULL, attrib[3], width, 0,
1361-
"%.*s""%s""%.*s""%+5d""%.*s""[%+4d ]",
1362-
17, hSpace, RSC(BIN).CODE(),
1363-
2, hSpace, RO(Shm)->Proc.Features.Factory.Overclock,
1364-
23, hSpace, RO(Shm)->Proc.Features.Factory.Bins );
1360+
GridHover( PUT( SCANKEY_NULL, attrib[3], width, 0,
1361+
"%.*s""%s""%.*s""%+5d""%.*s""[%+4d ]",
1362+
17, hSpace, RSC(BIN).CODE(),
1363+
2, hSpace, RO(Shm)->Proc.Features.Factory.Overclock,
1364+
23, hSpace, RO(Shm)->Proc.Features.Factory.Bins ),
1365+
(char *) RSC(OC_BINS_COMM).CODE() );
13651366
}
13661367
PUT(SCANKEY_NULL, attrib[0], width, 2, "%s", RSC(PERFORMANCE).CODE());
13671368

@@ -4458,7 +4459,7 @@ REASON_CODE SysInfoTech(Window *win,
44584459
(unsigned int[]) { CRC_INTEL, 0 },
44594460
RO(Shm)->Proc.Technology.OC == 1,
44604461
2, "%s%.*sOC [%3s]",
4461-
RSC(TECHNOLOGIES_OC).CODE(), NULL,
4462+
RSC(TECHNOLOGIES_OC).CODE(), RSC(TECH_OC_COMM).CODE(),
44624463
width - 13 - RSZ(TECHNOLOGIES_OC),
44634464
NULL,
44644465
SCANKEY_NULL,

‎x86_64/corefreqk.c‎

Lines changed: 117 additions & 104 deletions
Original file line numberDiff line numberDiff line change
@@ -2687,104 +2687,105 @@ static void Intel_FlexRatio(bool OC_ENABLED)
26872687
struct SIGNATURE Arch;
26882688
unsigned short grantFlex : 1-0,
26892689
experimental : 2-1,
2690-
freeToUse : 16-2;
2690+
freeToUse : 8-2,
2691+
bitsLayout : 16-8;
26912692
} list[] = {
2692-
{_Core_Yonah, 0, 1, 0},
2693-
{_Core_Conroe, 0, 1, 0},
2694-
{_Core_Kentsfield, 0, 1, 0},
2695-
{_Core_Conroe_616, 0, 1, 0},
2696-
{_Core_Penryn, 0, 1, 0},
2697-
{_Core_Dunnington, 0, 1, 0},
2698-
2699-
{_Atom_Bonnell, 0, 1, 0}, /* 06_1C */
2700-
{_Atom_Silvermont, 0, 1, 0}, /* 06_26 */
2701-
{_Atom_Lincroft, 0, 1, 0}, /* 06_27 */
2702-
{_Atom_Clover_Trail, 0, 1, 0}, /* 06_35 */
2703-
{_Atom_Saltwell, 0, 1, 0}, /* 06_36 */
2704-
2705-
{_Silvermont_Bay_Trail, 0, 1, 0}, /* 06_37 */
2706-
2707-
{_Atom_Avoton, 0, 1, 0}, /* 06_4D */
2708-
{_Atom_Airmont, 0, 1, 0}, /* 06_4C */
2709-
{_Atom_Goldmont, 1, 1, 0}, /* 06_5C */
2710-
{_Atom_Sofia, 1, 1, 0}, /* 06_5D */
2711-
{_Atom_Merrifield, 1, 1, 0}, /* 06_4A */
2712-
{_Atom_Moorefield, 1, 1, 0}, /* 06_5A */
2713-
2714-
{_Nehalem_Bloomfield, 1, 1, 0}, /* 06_1A */
2715-
{_Nehalem_Lynnfield, 1, 1, 0}, /* 06_1E */
2716-
{_Nehalem_MB, 1, 1, 0}, /* 06_1F */
2717-
{_Nehalem_EX, 1, 1, 0}, /* 06_2E */
2718-
2719-
{_Westmere, 1, 1, 0}, /* 06_25 */
2720-
{_Westmere_EP, 1, 1, 0}, /* 06_2C */
2721-
{_Westmere_EX, 1, 1, 0}, /* 06_2F */
2722-
2723-
{_SandyBridge, 1, 1, 0}, /* 06_2A */
2724-
{_SandyBridge_EP, 1, 1, 0}, /* 06_2D */
2725-
2726-
{_IvyBridge, 1, 0, 0}, /* 06_3A */
2727-
{_IvyBridge_EP, 1, 1, 0}, /* 06_3E */
2728-
2729-
{_Haswell_DT, 1, 1, 0}, /* 06_3C */
2730-
{_Haswell_EP, 1, 1, 0}, /* 06_3F */
2731-
{_Haswell_ULT, 1, 1, 0}, /* 06_45 */
2732-
{_Haswell_ULX, 1, 1, 0}, /* 06_46 */
2733-
2734-
{_Broadwell, 1, 1, 0}, /* 06_3D */
2735-
{_Broadwell_D, 1, 1, 0}, /* 06_56 */
2736-
{_Broadwell_H, 1, 1, 0}, /* 06_47 */
2737-
{_Broadwell_EP, 1, 1, 0}, /* 06_4F */
2738-
2739-
{_Skylake_UY, 1, 1, 0}, /* 06_4E */
2740-
{_Skylake_S, 1, 1, 0}, /* 06_5E */
2741-
{_Skylake_X, 1, 1, 0}, /* 06_55 */
2742-
2743-
{_Xeon_Phi, 0, 1, 0}, /* 06_57 */
2744-
2745-
{_Kabylake, 1, 1, 0}, /* 06_9E */
2746-
{_Kabylake_UY, 1, 1, 0}, /* 06_8E */
2747-
2748-
{_Cannonlake_U, 1, 1, 0}, /* 06_66 */
2749-
{_Cannonlake_H, 1, 1, 0},
2750-
{_Geminilake, 1, 1, 0}, /* 06_7A */
2751-
{_Icelake_UY, 1, 1, 0}, /* 06_7E */
2752-
2753-
{_Icelake_X, 1, 1, 0},
2754-
{_Icelake_D, 1, 1, 0},
2755-
{_Sunny_Cove, 1, 1, 0},
2756-
{_Tigerlake, 1, 1, 0},
2757-
{_Tigerlake_U, 1, 1, 0}, /* 06_8C */
2758-
{_Cometlake, 1, 1, 0},
2759-
{_Cometlake_UY, 1, 1, 0},
2760-
{_Atom_Denverton, 1, 1, 0},
2761-
{_Tremont_Jacobsville, 1, 1, 0},
2762-
{_Tremont_Lakefield, 1, 1, 0},
2763-
{_Tremont_Elkhartlake, 1, 1, 0},
2764-
{_Tremont_Jasperlake, 1, 1, 0},
2765-
{_Sapphire_Rapids, 1, 1, 0},
2766-
{_Emerald_Rapids, 1, 1, 0},
2767-
{_Granite_Rapids_X, 1, 1, 0},
2768-
{_Granite_Rapids_D, 1, 1, 0},
2769-
{_Sierra_Forest, 1, 1, 0},
2770-
{_Grand_Ridge, 1, 1, 0},
2771-
{_Rocketlake, 1, 1, 0},
2772-
{_Rocketlake_U, 1, 1, 0},
2773-
{_Alderlake_S, 1, 1, 0}, /* 06_97 */
2774-
{_Alderlake_H, 1, 1, 0},
2775-
{_Alderlake_N, 1, 1, 0},
2776-
{_Meteorlake_M, 1, 1, 0},
2777-
{_Meteorlake_N, 1, 1, 0},
2778-
{_Meteorlake_S, 1, 1, 0},
2779-
{_Raptorlake, 1, 1, 0}, /* 06_B7 */
2780-
{_Raptorlake_P, 1, 1, 0},
2781-
{_Raptorlake_S, 1, 1, 0},
2782-
{_Lunarlake, 1, 1, 0}, /* 06_BD */
2783-
{_Arrowlake, 1, 1, 0}, /* 06_C6 */
2784-
{_Arrowlake_H, 1, 1, 0}, /* 06_C5 */
2785-
{_Arrowlake_U, 1, 1, 0}, /* 06_B5 */
2786-
{_Pantherlake, 1, 1, 0}, /* 06_CC */
2787-
{_Clearwater_Forest, 1, 1, 0} /* 06_DD */
2693+
{_Core_Yonah, 0, 1, 0, 1},
2694+
{_Core_Conroe, 0, 1, 0, 1},
2695+
{_Core_Kentsfield, 0, 1, 0, 1},
2696+
{_Core_Conroe_616, 0, 1, 0, 1},
2697+
{_Core_Penryn, 1, 1, 0, 1}, /* 06_17 */
2698+
{_Core_Dunnington, 0, 1, 0, 1},
2699+
2700+
{_Atom_Bonnell, 0, 1, 0, 0}, /* 06_1C */
2701+
{_Atom_Silvermont, 0, 1, 0, 0}, /* 06_26 */
2702+
{_Atom_Lincroft, 0, 1, 0, 0}, /* 06_27 */
2703+
{_Atom_Clover_Trail, 0, 1, 0, 0}, /* 06_35 */
2704+
{_Atom_Saltwell, 0, 1, 0, 0}, /* 06_36 */
2705+
2706+
{_Silvermont_Bay_Trail, 0, 1, 0, 0}, /* 06_37 */
2707+
2708+
{_Atom_Avoton, 0, 1, 0, 0}, /* 06_4D */
2709+
{_Atom_Airmont, 0, 1, 0, 0}, /* 06_4C */
2710+
{_Atom_Goldmont, 1, 1, 0, 0}, /* 06_5C */
2711+
{_Atom_Sofia, 1, 1, 0, 0}, /* 06_5D */
2712+
{_Atom_Merrifield, 1, 1, 0, 0}, /* 06_4A */
2713+
{_Atom_Moorefield, 1, 1, 0, 0}, /* 06_5A */
2714+
2715+
{_Nehalem_Bloomfield, 1, 1, 0, 1}, /* 06_1A */
2716+
{_Nehalem_Lynnfield, 1, 1, 0, 1}, /* 06_1E */
2717+
{_Nehalem_MB, 1, 1, 0, 1}, /* 06_1F */
2718+
{_Nehalem_EX, 1, 1, 0, 1}, /* 06_2E */
2719+
2720+
{_Westmere, 1, 1, 0, 1}, /* 06_25 */
2721+
{_Westmere_EP, 1, 0, 0, 1}, /* 06_2C */
2722+
{_Westmere_EX, 1, 1, 0, 1}, /* 06_2F */
2723+
2724+
{_SandyBridge, 1, 1, 0, 0}, /* 06_2A */
2725+
{_SandyBridge_EP, 1, 1, 0, 0}, /* 06_2D */
2726+
2727+
{_IvyBridge, 1, 0, 0, 0}, /* 06_3A */
2728+
{_IvyBridge_EP, 1, 1, 0, 0}, /* 06_3E */
2729+
2730+
{_Haswell_DT, 1, 1, 0, 0}, /* 06_3C */
2731+
{_Haswell_EP, 1, 1, 0, 0}, /* 06_3F */
2732+
{_Haswell_ULT, 1, 1, 0, 0}, /* 06_45 */
2733+
{_Haswell_ULX, 1, 1, 0, 0}, /* 06_46 */
2734+
2735+
{_Broadwell, 1, 1, 0, 0}, /* 06_3D */
2736+
{_Broadwell_D, 1, 1, 0, 0}, /* 06_56 */
2737+
{_Broadwell_H, 1, 1, 0, 0}, /* 06_47 */
2738+
{_Broadwell_EP, 1, 1, 0, 0}, /* 06_4F */
2739+
2740+
{_Skylake_UY, 1, 1, 0, 0}, /* 06_4E */
2741+
{_Skylake_S, 1, 1, 0, 0}, /* 06_5E */
2742+
{_Skylake_X, 1, 1, 0, 0}, /* 06_55 */
2743+
2744+
{_Xeon_Phi, 0, 1, 0, 0}, /* 06_57 */
2745+
2746+
{_Kabylake, 1, 1, 0, 0}, /* 06_9E */
2747+
{_Kabylake_UY, 1, 1, 0, 0}, /* 06_8E */
2748+
2749+
{_Cannonlake_U, 1, 1, 0, 0}, /* 06_66 */
2750+
{_Cannonlake_H, 1, 1, 0, 0},
2751+
{_Geminilake, 1, 1, 0, 0}, /* 06_7A */
2752+
{_Icelake_UY, 1, 1, 0, 0}, /* 06_7E */
2753+
2754+
{_Icelake_X, 1, 1, 0, 0},
2755+
{_Icelake_D, 1, 1, 0, 0},
2756+
{_Sunny_Cove, 1, 1, 0, 0},
2757+
{_Tigerlake, 1, 1, 0, 0},
2758+
{_Tigerlake_U, 1, 0, 0, 0}, /* 06_8C */
2759+
{_Cometlake, 1, 1, 0, 0},
2760+
{_Cometlake_UY, 1, 1, 0, 0},
2761+
{_Atom_Denverton, 1, 1, 0, 0},
2762+
{_Tremont_Jacobsville, 1, 1, 0, 0},
2763+
{_Tremont_Lakefield, 1, 1, 0, 0},
2764+
{_Tremont_Elkhartlake, 1, 1, 0, 0},
2765+
{_Tremont_Jasperlake, 1, 1, 0, 0},
2766+
{_Sapphire_Rapids, 1, 1, 0, 0},
2767+
{_Emerald_Rapids, 1, 1, 0, 0},
2768+
{_Granite_Rapids_X, 1, 1, 0, 0},
2769+
{_Granite_Rapids_D, 1, 1, 0, 0},
2770+
{_Sierra_Forest, 1, 1, 0, 0},
2771+
{_Grand_Ridge, 1, 1, 0, 0},
2772+
{_Rocketlake, 1, 1, 0, 0},
2773+
{_Rocketlake_U, 1, 1, 0, 0},
2774+
{_Alderlake_S, 1, 0, 0, 0}, /* 06_97 */
2775+
{_Alderlake_H, 1, 1, 0, 0},
2776+
{_Alderlake_N, 1, 1, 0, 0},
2777+
{_Meteorlake_M, 1, 1, 0, 0},
2778+
{_Meteorlake_N, 1, 1, 0, 0},
2779+
{_Meteorlake_S, 1, 1, 0, 0},
2780+
{_Raptorlake, 1, 1, 0, 0}, /* 06_B7 */
2781+
{_Raptorlake_P, 1, 1, 0, 0},
2782+
{_Raptorlake_S, 1, 1, 0, 0},
2783+
{_Lunarlake, 1, 1, 0, 0}, /* 06_BD */
2784+
{_Arrowlake, 1, 1, 0, 0}, /* 06_C6 */
2785+
{_Arrowlake_H, 1, 1, 0, 0}, /* 06_C5 */
2786+
{_Arrowlake_U, 1, 1, 0, 0}, /* 06_B5 */
2787+
{_Pantherlake, 1, 1, 0, 0}, /* 06_CC */
2788+
{_Clearwater_Forest, 1, 1, 0, 0} /* 06_DD */
27882789
};
27892790
const unsigned int ids = sizeof(list) / sizeof(list[0]);
27902791
unsigned int id;
@@ -2798,17 +2799,27 @@ static void Intel_FlexRatio(bool OC_ENABLED)
27982799
if (!list[id].experimental
27992800
|| (list[id].experimental
28002801
&& PUBLIC(RO(Proc))->Registration.Experimental))
2801-
{
2802-
FLEX_RATIO flexRegister = {.value = 0};
2803-
RDMSR(flexRegister, MSR_FLEX_RATIO);
2804-
PUBLIC(RO(Proc))->Features.OC_Enable = flexRegister.OC_ENABLED;
2805-
PUBLIC(RO(Proc))->Features.Factory.Bins = flexRegister.OC_BINS;
2806-
PUBLIC(RO(Proc))->Features.OC_Lock = flexRegister.OC_LOCK;
2802+
{
2803+
FLEX_RATIO flexReg = {.value = 0};
2804+
RDMSR(flexReg, MSR_FLEX_RATIO);
2805+
2806+
switch (list[id].bitsLayout) {
2807+
default:
2808+
case 0:
2809+
PUBLIC(RO(Proc))->Features.OC_Enable = flexReg.OC_ENABLED;
2810+
PUBLIC(RO(Proc))->Features.Factory.Bins = flexReg.OC_BINS;
2811+
PUBLIC(RO(Proc))->Features.OC_Lock = flexReg.OC_LOCK;
2812+
break;
2813+
case 1:
2814+
PUBLIC(RO(Proc))->Features.OC_Enable = flexReg.OC_ENABLED;
2815+
PUBLIC(RO(Proc))->Features.Factory.Bins=flexReg.CLOCK_FLEX_MAX;
2816+
break;
2817+
}
28072818
PUBLIC(RO(Proc))->Features.Factory.Overclock = \
28082819
ABS_FREQ_MHz( signed int,
28092820
PUBLIC(RO(Proc))->Features.Factory.Bins,
28102821
PUBLIC(RO(Proc))->Features.Factory.Clock );
2811-
}
2822+
}
28122823
}
28132824
break;
28142825
}
@@ -5993,6 +6004,8 @@ static PCI_CALLBACK X58_QPI(struct pci_dev *dev)
59936004
pci_read_config_dword(dev, 0xd0,
59946005
&PUBLIC(RO(Proc))->Uncore.Bus.QuickPath.value);
59956006

6007+
Intel_FlexRatio(true);
6008+
59966009
return (PCI_CALLBACK) 0;
59976010
}
59986011

‎x86_64/intel_reg.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -672,7 +672,8 @@ typedef union
672672
{ /* OC Ratio = BCLK ratio + OC_BINS */
673673
unsigned long long
674674
OC_VID : 8-0,
675-
UnknownBits1 : 16-8,
675+
CLOCK_FLEX_MAX : 12-8, /* R/W: Westmere/Gulftown; Wolfdale */
676+
UnknownBits1 : 16-12,
676677
OC_ENABLED : 17-16,
677678
OC_BINS : 20-17, /* 0:Disabled ... 7:Unlimited */
678679
OC_LOCK : 21-20,

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