[CPPC] Provides the ACPI _CPC object state.

Author: cyring

corefreq-cli-rsc-en.h

@@ -1171,6 +1171,7 @@
 #define RSC_PERF_MON_VID_CODE_EN	"Legacy Voltage ID control"
 #define RSC_PERF_MON_HWCF_CODE_EN	"P-State Hardware Coordination Feedback"
 #define RSC_PERF_MON_CPPC_CODE_EN  "Collaborative Processor Performance Control"
+#define RSC_PERF_MON_CPC_CODE_EN	"Continuous Performance Control"
 #define RSC_PERF_MON_HWP_CODE_EN	"Hardware-Controlled Performance States"
 #define RSC_PERF_MON_HDC_CODE_EN	"Hardware Duty Cycling"
 #define RSC_PERF_MON_PKG_CSTATE_CODE_EN "Package C-States"
@@ -2237,6 +2238,7 @@
 #define RSC_PERF_LABEL_VID_CODE 	"VID"
 #define RSC_PERF_LABEL_HWCF_CODE	"MPERF/APERF"
 #define RSC_PERF_LABEL_CPPC_CODE	"CPPC"
+#define RSC_PERF_LABEL_CPC_CODE 	"_CPC"
 #define RSC_PERF_LABEL_HWP_CODE 	"HWP"
 #define RSC_PERF_LABEL_HDC_CODE 	"HDC"
 #define RSC_PERF_LABEL_CFG_CTRL_CODE	"CONFIG"

corefreq-cli-rsc-fr.h

@@ -650,6 +650,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
 #define RSC_PERF_MON_VID_CODE_FR	"Legacy Voltage ID control"
 #define RSC_PERF_MON_HWCF_CODE_FR	"P-State Hardware Coordination Feedback"
 #define RSC_PERF_MON_CPPC_CODE_FR  "Collaborative Processor Performance Control"
+#define RSC_PERF_MON_CPC_CODE_FR	RSC_PERF_MON_CPC_CODE_EN
 #define RSC_PERF_MON_HWP_CODE_FR	"Hardware-Controlled Performance States"
 #define RSC_PERF_MON_HDC_CODE_FR	"Hardware Duty Cycling"
 #define RSC_PERF_MON_PKG_CSTATE_CODE_FR "Package C-States"

corefreq-cli-rsc.c

@@ -1008,6 +1008,7 @@ RESOURCE_ST Resource[] = {
 	LDT(RSC_PERF_MON_VID),
 	LDT(RSC_PERF_MON_HWCF),
 	LDT(RSC_PERF_MON_CPPC),
+	LDT(RSC_PERF_MON_CPC),
 	LDT(RSC_PERF_MON_HWP),
 	LDT(RSC_PERF_MON_HDC),
 	LDT(RSC_PERF_MON_PKG_CSTATE),
@@ -1047,6 +1048,7 @@ RESOURCE_ST Resource[] = {
 	LDQ(RSC_PERF_LABEL_VID),
 	LDQ(RSC_PERF_LABEL_HWCF),
 	LDQ(RSC_PERF_LABEL_CPPC),
+	LDQ(RSC_PERF_LABEL_CPC),
 	LDQ(RSC_PERF_LABEL_HWP),
 	LDQ(RSC_PERF_LABEL_HDC),
 	LDQ(RSC_PERF_LABEL_CFG_CTRL),

corefreq-cli-rsc.h

@@ -811,6 +811,7 @@ enum {
 	RSC_PERF_MON_VID,
 	RSC_PERF_MON_HWCF,
 	RSC_PERF_MON_CPPC,
+	RSC_PERF_MON_CPC,
 	RSC_PERF_MON_HWP,
 	RSC_PERF_MON_HDC,
 	RSC_PERF_MON_PKG_CSTATE,
@@ -850,6 +851,7 @@ enum {
 	RSC_PERF_LABEL_VID,
 	RSC_PERF_LABEL_HWCF,
 	RSC_PERF_LABEL_CPPC,
+	RSC_PERF_LABEL_CPC,
 	RSC_PERF_LABEL_HWP,
 	RSC_PERF_LABEL_HDC,
 	RSC_PERF_LABEL_CFG_CTRL,

corefreq-cli.c

@@ -4080,6 +4080,15 @@ REASON_CODE SysInfoPerfMon(Window *win, CUINT width, CELL_FUNC OutFunc)
 		width - 26 - RSZ(PERF_MON_HWCF), hSpace,
 		RSC(PERF_LABEL_HWCF).CODE(), ENABLED(bix) );
 /* Section Mark */
+    if   ( (RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_AMD)
+	|| (RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_HYGON) )
+    {
+	PUT(SCANKEY_NULL, attrib[RO(Shm)->Proc.Features.OSPM_CPC], width, 2,
+		"%s%.*s%s       <%3s>", RSC(PERF_MON_CPC).CODE(),
+		width - 19 - RSZ(PERF_MON_CPC), hSpace,
+		RSC(PERF_LABEL_CPC).CODE(),
+		ENABLED(RO(Shm)->Proc.Features.OSPM_CPC));
+    }
 	bix = (RO(Shm)->Proc.Features.Power.EAX.HWP_Reg == 1)	/* Intel:HWP */
 	|| (RO(Shm)->Proc.Features.leaf80000008.EBX.CPPC == 1)	/* AMD:CPPC  */
 	|| (RO(Shm)->Proc.Features.ACPI_CPPC == 1);		/* ACPI:CPPC */

corefreqk.c

@@ -3877,8 +3877,10 @@ void For_All_ACPI_CPPC(signed int(*CPPC_Func)(unsigned int, void*), void *arg)
 	#else
 	signed int rc = acpi_disabled;
 	#endif
-
 	unsigned int cpu;
+
+	PUBLIC(RO(Proc))->Features.OSPM_CPC = !rc;
+
 	for (cpu = 0; (cpu < PUBLIC(RO(Proc))->CPU.Count) && (rc == 0); cpu++)
 	{
 		rc = CPPC_Func(cpu, arg);

coretypes.h

@@ -1950,7 +1950,8 @@ typedef struct	/* BSP CPUID features.					*/
 			HSMP_Enable	: 38-37,
 			XtraCOF 	: 40-38, /* 1:CPB ; 2:{CPB and XFR} */
 			ACPI_CPPC	: 41-40,
-			_pad64		: 64-41;
+			OSPM_CPC	: 42-41,
+			_pad64		: 64-42;
 	};
 } FEATURES;