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[Intel][HSW & BDW][SKL] Make use of same function DimmWidthToRows 
1 parent 975baec commit c2aa1cc

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+57
-52
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1 file changed

+57
-52
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‎corefreqd.c‎

Lines changed: 57 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -3853,6 +3853,23 @@ void IVB_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
38533853
RO(Shm)->Proc.Technology.IOMMU = !RO(Proc)->Uncore.Bus.SNB_Cap.VT_d;
38543854
}
38553855

3856+
unsigned int DimmWidthToRows(unsigned int width)
3857+
{
3858+
unsigned int rows = 0;
3859+
switch (width) {
3860+
case 0b00:
3861+
rows = 8;
3862+
break;
3863+
case 0b01:
3864+
rows = 16;
3865+
break;
3866+
case 0b10:
3867+
rows = 32;
3868+
break;
3869+
}
3870+
return (8 * 1024 * rows);
3871+
}
3872+
38563873
void HSW_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
38573874
{
38583875
unsigned short mc, cha, slot;
@@ -3970,43 +3987,48 @@ void HSW_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
39703987
TIMING(mc, cha).PDM_AGGR = \
39713988
RO(Proc)->Uncore.MC[mc].Channel[cha].HSW.PDWN.PDWN_Mode;
39723989

3973-
for (slot = 0; slot < RO(Shm)->Uncore.MC[mc].SlotCount; slot++)
3974-
{
3975-
unsigned int width, DIMM_Banks;
3976-
3977-
if (slot % 2 == 0) {
3978-
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = \
3979-
RO(Proc)->Uncore.MC[mc].SNB.MAD0.DANOR;
3990+
for (slot = 0; slot < RO(Shm)->Uncore.MC[mc].SlotCount; slot++)
3991+
{
3992+
unsigned int DIMM_Banks;
3993+
const unsigned short
3994+
Dimm_A_Map = cha & 1 ? RO(Proc)->Uncore.MC[mc].SNB.MAD1.DAS
3995+
: RO(Proc)->Uncore.MC[mc].SNB.MAD0.DAS;
39803996

3981-
width = RO(Proc)->Uncore.MC[mc].SNB.MAD0.DAW;
3982-
} else {
3983-
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = \
3984-
RO(Proc)->Uncore.MC[mc].SNB.MAD0.DBNOR;
3997+
if (slot == Dimm_A_Map)
3998+
{
3999+
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = \
4000+
cha & 1 ? RO(Proc)->Uncore.MC[mc].SNB.MAD1.DANOR
4001+
: RO(Proc)->Uncore.MC[mc].SNB.MAD0.DANOR;
39854002

3986-
width = RO(Proc)->Uncore.MC[mc].SNB.MAD0.DBW;
3987-
}
3988-
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks++;
4003+
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = \
4004+
DimmWidthToRows(cha & 1 ? RO(Proc)->Uncore.MC[mc].SNB.MAD1.DAW
4005+
: RO(Proc)->Uncore.MC[mc].SNB.MAD0.DAW);
4006+
}
4007+
else
4008+
{
4009+
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = \
4010+
cha & 1 ? RO(Proc)->Uncore.MC[mc].SNB.MAD1.DBNOR
4011+
: RO(Proc)->Uncore.MC[mc].SNB.MAD0.DBNOR;
39894012

3990-
if (width == 0) {
3991-
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 1 << 14;
3992-
} else {
3993-
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 1 << 15;
3994-
}
4013+
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = \
4014+
DimmWidthToRows(cha & 1 ? RO(Proc)->Uncore.MC[mc].SNB.MAD1.DBW
4015+
: RO(Proc)->Uncore.MC[mc].SNB.MAD0.DBW);
4016+
}
4017+
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks++;
39954018

39964019
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols = 1 << 10;
39974020

39984021
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Size = \
3999-
dimmSize[cha][slot] * 256;
4000-
4001-
DIMM_Banks = 8 * dimmSize[cha][slot] * 1024 * 1024;
4022+
dimmSize[cha][slot ^ Dimm_A_Map] * 256;
40024023

4024+
DIMM_Banks = 8 * dimmSize[cha][slot ^ Dimm_A_Map] * 1024 * 1024;
40034025
DIMM_Banks = DIMM_Banks
40044026
/ (RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows
40054027
* RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols
40064028
* RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks);
40074029

40084030
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = DIMM_Banks;
4009-
}
4031+
}
40104032
TIMING(mc, cha).ECC = (cha == 0) ?
40114033
RO(Proc)->Uncore.MC[mc].SNB.MAD0.ECC
40124034
: RO(Proc)->Uncore.MC[mc].SNB.MAD1.ECC;
@@ -4093,23 +4115,6 @@ void HSW_EP_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
40934115
RO(Shm)->Proc.Technology.IOMMU_Ver_Minor = 0;
40944116
}
40954117

4096-
unsigned int SKL_DimmWidthToRows(unsigned int width)
4097-
{
4098-
unsigned int rows = 0;
4099-
switch (width) {
4100-
case 0b00:
4101-
rows = 8;
4102-
break;
4103-
case 0b01:
4104-
rows = 16;
4105-
break;
4106-
case 0b10:
4107-
rows = 32;
4108-
break;
4109-
}
4110-
return (8 * 1024 * rows);
4111-
}
4112-
41134118
void SKL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
41144119
{
41154120
unsigned short mc, cha;
@@ -4283,19 +4288,19 @@ void SKL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
42834288

42844289
RO(Shm)->Uncore.MC[mc].Channel[0].DIMM[
42854290
RO(Proc)->Uncore.MC[mc].SKL.MADC0.Dimm_L_Map
4286-
].Rows = SKL_DimmWidthToRows(RO(Proc)->Uncore.MC[mc].SKL.MADD0.DLW);
4291+
].Rows = DimmWidthToRows(RO(Proc)->Uncore.MC[mc].SKL.MADD0.DLW);
42874292

42884293
RO(Shm)->Uncore.MC[mc].Channel[0].DIMM[
42894294
!RO(Proc)->Uncore.MC[mc].SKL.MADC0.Dimm_L_Map
4290-
].Rows = SKL_DimmWidthToRows(RO(Proc)->Uncore.MC[mc].SKL.MADD0.DSW);
4295+
].Rows = DimmWidthToRows(RO(Proc)->Uncore.MC[mc].SKL.MADD0.DSW);
42914296

42924297
RO(Shm)->Uncore.MC[mc].Channel[1].DIMM[
42934298
RO(Proc)->Uncore.MC[mc].SKL.MADC1.Dimm_L_Map
4294-
].Rows = SKL_DimmWidthToRows(RO(Proc)->Uncore.MC[mc].SKL.MADD1.DLW);
4299+
].Rows = DimmWidthToRows(RO(Proc)->Uncore.MC[mc].SKL.MADD1.DLW);
42954300

42964301
RO(Shm)->Uncore.MC[mc].Channel[1].DIMM[
42974302
!RO(Proc)->Uncore.MC[mc].SKL.MADC1.Dimm_L_Map
4298-
].Rows = SKL_DimmWidthToRows(RO(Proc)->Uncore.MC[mc].SKL.MADD1.DSW);
4303+
].Rows = DimmWidthToRows(RO(Proc)->Uncore.MC[mc].SKL.MADD1.DSW);
42994304

43004305
switch (RO(Proc)->Uncore.MC[mc].SKL.MADCH.DDR_TYPE) {
43014306
case 0b00:
@@ -5068,19 +5073,19 @@ void ADL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
50685073
case 1 ... 4:
50695074
RO(Shm)->Uncore.MC[mc].Channel[0].DIMM[
50705075
RO(Proc)->Uncore.MC[mc].ADL.MADC0.Dimm_L_Map
5071-
].Rows = SKL_DimmWidthToRows(RO(Proc)->Uncore.MC[mc].ADL.MADD0.DLW);
5076+
].Rows = DimmWidthToRows(RO(Proc)->Uncore.MC[mc].ADL.MADD0.DLW);
50725077

50735078
RO(Shm)->Uncore.MC[mc].Channel[0].DIMM[
50745079
!RO(Proc)->Uncore.MC[mc].ADL.MADC0.Dimm_L_Map
5075-
].Rows = SKL_DimmWidthToRows(RO(Proc)->Uncore.MC[mc].ADL.MADD0.DSW);
5080+
].Rows = DimmWidthToRows(RO(Proc)->Uncore.MC[mc].ADL.MADD0.DSW);
50765081

50775082
RO(Shm)->Uncore.MC[mc].Channel[1].DIMM[
50785083
RO(Proc)->Uncore.MC[mc].ADL.MADC1.Dimm_L_Map
5079-
].Rows = SKL_DimmWidthToRows(RO(Proc)->Uncore.MC[mc].ADL.MADD1.DLW);
5084+
].Rows = DimmWidthToRows(RO(Proc)->Uncore.MC[mc].ADL.MADD1.DLW);
50805085

50815086
RO(Shm)->Uncore.MC[mc].Channel[1].DIMM[
50825087
!RO(Proc)->Uncore.MC[mc].ADL.MADC1.Dimm_L_Map
5083-
].Rows = SKL_DimmWidthToRows(RO(Proc)->Uncore.MC[mc].ADL.MADD1.DSW);
5088+
].Rows = DimmWidthToRows(RO(Proc)->Uncore.MC[mc].ADL.MADD1.DSW);
50845089
break;
50855090
case 5:
50865091
default:
@@ -5964,12 +5969,12 @@ void PCI_Intel(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core),
59645969
SET_CHIPSET(IC_LYNXPOINT_M);
59655970
break;
59665971
case DID_INTEL_HASWELL_UY_IMC_HA0: /* HSW Mobile U/Y */
5967-
IVB_CAP(RO(Shm), RO(Proc), RO(Core));
5972+
HSW_CAP(RO(Shm), RO(Proc), RO(Core));
59685973
HSW_IMC(RO(Shm), RO(Proc));
59695974
SET_CHIPSET(IC_LYNXPOINT_M);
59705975
break;
59715976
case DID_INTEL_HASWELL_IMC_HA0: /* Haswell */
5972-
IVB_CAP(RO(Shm), RO(Proc), RO(Core));
5977+
HSW_CAP(RO(Shm), RO(Proc), RO(Core));
59735978
HSW_IMC(RO(Shm), RO(Proc));
59745979
SET_CHIPSET(IC_LYNXPOINT);
59755980
break;
@@ -5979,14 +5984,14 @@ void PCI_Intel(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core),
59795984
SET_CHIPSET(IC_WELLSBURG);
59805985
break;
59815986
case DID_INTEL_BROADWELL_IMC_HA0: /* Broadwell/Y/U Core m */
5982-
IVB_CAP(RO(Shm), RO(Proc), RO(Core));
5987+
HSW_CAP(RO(Shm), RO(Proc), RO(Core));
59835988
HSW_IMC(RO(Shm), RO(Proc));
59845989
SET_CHIPSET(IC_WILDCATPOINT_M);
59855990
break;
59865991
case DID_INTEL_BROADWELL_D_IMC_HA0: /* BDW/Desktop */
59875992
case DID_INTEL_BROADWELL_H_IMC_HA0: /* Broadwell/H */
59885993
case DID_INTEL_BROADWELL_U_IMC_HA0: /* Broadwell/U */
5989-
IVB_CAP(RO(Shm), RO(Proc), RO(Core));
5994+
HSW_CAP(RO(Shm), RO(Proc), RO(Core));
59905995
HSW_IMC(RO(Shm), RO(Proc));
59915996
SET_CHIPSET(IC_WELLSBURG);
59925997
break;

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