Skip to content

Commit 80d6e11

Browse files
cyringCyrIng
cyring
authored and
CyrIng
committed
[CLI] Refactoring HWP/CPPC to print all capabilities per CPU
1 parent bd64f98 commit 80d6e11

8 files changed

+157
-116
lines changed

‎corefreq-cli-rsc-en.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1164,7 +1164,6 @@
11641164
#define RSC_GENERAL_CTRS_CODE_EN "General"
11651165
#define RSC_FIXED_CTRS_CODE_EN "Fixed"
11661166
#define RSC_PERF_MON_UNIT_BIT_CODE_EN "bits"
1167-
#define RSC_PERF_MON_UNIT_HWP_CODE_EN "(MHz)"
11681167
#define RSC_PERF_MON_C1E_CODE_EN "Enhanced Halt State"
11691168
#define RSC_PERF_MON_C1A_CODE_EN "C1 Auto Demotion"
11701169
#define RSC_PERF_MON_C3A_CODE_EN "C3 Auto Demotion"

‎corefreq-cli-rsc-fr.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -642,7 +642,6 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
642642
#define RSC_GENERAL_CTRS_CODE_FR "G""\xa9""n""\xa9""raux"
643643
#define RSC_FIXED_CTRS_CODE_FR "Fixes"
644644
#define RSC_PERF_MON_UNIT_BIT_CODE_FR "bits"
645-
#define RSC_PERF_MON_UNIT_HWP_CODE_FR "(MHz)"
646645
#define RSC_PERF_MON_C1E_CODE_FR "Enhanced Halt State"
647646
#define RSC_PERF_MON_C1A_CODE_FR "C1 Auto Demotion"
648647
#define RSC_PERF_MON_C3A_CODE_FR "C3 Auto Demotion"

‎corefreq-cli-rsc-theme-dflt.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1586,7 +1586,7 @@
15861586
HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\
15871587
HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\
15881588
HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\
1589-
HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \
1589+
HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \
15901590
}
15911591

15921592
#define RSC_SYSINFO_PERFMON_HWP_CAP_COND1_THM_DFLT_ATTR \
@@ -1595,7 +1595,7 @@
15951595
LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\
15961596
LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\
15971597
LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\
1598-
LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \
1598+
LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \
15991599
}
16001600

16011601
#define RSC_SYSINFO_PWR_THERMAL_COND0_THM_DFLT_ATTR \

‎corefreq-cli-rsc-theme-usr1.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1586,7 +1586,7 @@
15861586
HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\
15871587
HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\
15881588
HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\
1589-
HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \
1589+
HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \
15901590
}
15911591

15921592
#define RSC_SYSINFO_PERFMON_HWP_CAP_COND1_THM_USR1_ATTR \
@@ -1595,7 +1595,7 @@
15951595
LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\
15961596
LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\
15971597
LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\
1598-
LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \
1598+
LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \
15991599
}
16001600

16011601
#define RSC_SYSINFO_PWR_THERMAL_COND0_THM_USR1_ATTR \

‎corefreq-cli-rsc-theme-usr2.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1586,7 +1586,7 @@
15861586
HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\
15871587
HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\
15881588
HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,\
1589-
HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \
1589+
HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK,HDK \
15901590
}
15911591

15921592
#define RSC_SYSINFO_PERFMON_HWP_CAP_COND1_THM_USR2_ATTR \
@@ -1595,7 +1595,7 @@
15951595
LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\
15961596
LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\
15971597
LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,\
1598-
LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \
1598+
LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \
15991599
}
16001600

16011601
#define RSC_SYSINFO_PWR_THERMAL_COND0_THM_USR2_ATTR \

‎corefreq-cli-rsc.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1005,7 +1005,6 @@ RESOURCE_ST Resource[] = {
10051005
LDT(RSC_GENERAL_CTRS),
10061006
LDT(RSC_FIXED_CTRS),
10071007
LDT(RSC_PERF_MON_UNIT_BIT),
1008-
LDT(RSC_PERF_MON_UNIT_HWP),
10091008
LDT(RSC_PERF_MON_C1E),
10101009
LDT(RSC_PERF_MON_C1A),
10111010
LDT(RSC_PERF_MON_C3A),

‎corefreq-cli-rsc.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -808,7 +808,6 @@ enum {
808808
RSC_GENERAL_CTRS,
809809
RSC_FIXED_CTRS,
810810
RSC_PERF_MON_UNIT_BIT,
811-
RSC_PERF_MON_UNIT_HWP,
812811
RSC_PERF_MON_C1E,
813812
RSC_PERF_MON_C1A,
814813
RSC_PERF_MON_C3A,

‎corefreq-cli.c‎

Lines changed: 151 additions & 106 deletions
Original file line numberDiff line numberDiff line change
@@ -3829,6 +3829,7 @@ void HWP_Update(TGrid *grid, DATA_TYPE data[])
38293829

38303830
void Refresh_HWP_Cap_Freq(TGrid *grid, DATA_TYPE data[])
38313831
{
3832+
char *item;
38323833
ATTRIBUTE *HWP_Cap_Attr[2] = {
38333834
RSC(SYSINFO_PERFMON_HWP_CAP_COND0).ATTR(),
38343835
RSC(SYSINFO_PERFMON_HWP_CAP_COND1).ATTR()
@@ -3838,7 +3839,46 @@ void Refresh_HWP_Cap_Freq(TGrid *grid, DATA_TYPE data[])
38383839

38393840
memcpy(grid->cell.attr, HWP_Cap_Attr[bix], grid->cell.length);
38403841

3841-
RefreshRatioFreq(grid, data);
3842+
if ((item = malloc(grid->cell.length + 1)) != NULL)
3843+
{
3844+
const unsigned int cpu = data[0].uint[0];
3845+
CPU_STRUCT *SProc = &RO(Shm)->Cpu[cpu];
3846+
struct FLIP_FLOP *CFlop = &SProc->FlipFlop[!RO(Shm)->Cpu[cpu].Toggle];
3847+
3848+
double Lowest_MHz = ABS_FREQ_MHz(double,
3849+
SProc->PowerThermal.HWP.Capabilities.Lowest,
3850+
CFlop->Clock
3851+
),
3852+
Efficient_MHz = ABS_FREQ_MHz(double,
3853+
SProc->PowerThermal.HWP.Capabilities.Most_Efficient,
3854+
CFlop->Clock
3855+
),
3856+
Guaranteed_MHz = ABS_FREQ_MHz(double,
3857+
SProc->PowerThermal.HWP.Capabilities.Guaranteed,
3858+
CFlop->Clock
3859+
),
3860+
Highest_MHz = ABS_FREQ_MHz(double,
3861+
SProc->PowerThermal.HWP.Capabilities.Highest,
3862+
CFlop->Clock
3863+
);
3864+
3865+
size_t length;
3866+
if (StrLenFormat(length, item, grid->cell.length + 1,
3867+
"CPU #%-3u %7.2f (%3u) %7.2f (%3u) %7.2f (%3u) %7.2f (%3u)",
3868+
cpu,
3869+
Lowest_MHz,
3870+
SProc->PowerThermal.HWP.Capabilities.Lowest,
3871+
Efficient_MHz,
3872+
SProc->PowerThermal.HWP.Capabilities.Most_Efficient,
3873+
Guaranteed_MHz,
3874+
SProc->PowerThermal.HWP.Capabilities.Guaranteed,
3875+
Highest_MHz,
3876+
SProc->PowerThermal.HWP.Capabilities.Highest) > 0)
3877+
{
3878+
memcpy(&grid->cell.item[3], item, length);
3879+
}
3880+
free(item);
3881+
}
38423882
}
38433883

38443884
void HDC_Update(TGrid *grid, DATA_TYPE data[])
@@ -4098,111 +4138,6 @@ REASON_CODE SysInfoPerfMon(Window *win, CUINT width, CELL_FUNC OutFunc)
40984138
"%s%.*s%s [%3s]", RSC(PERF_MON_HWCF).CODE(),
40994139
width - 26 - RSZ(PERF_MON_HWCF), hSpace,
41004140
RSC(PERF_LABEL_HWCF).CODE(), ENABLED(bix) );
4101-
/* Section Mark */
4102-
if ( (RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_AMD)
4103-
|| (RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_HYGON) )
4104-
{
4105-
PUT(SCANKEY_NULL, attrib[RO(Shm)->Proc.Features.OSPM_CPC], width, 2,
4106-
"%s%.*s%s [%3s]", RSC(PERF_MON_CPC).CODE(),
4107-
width - 19 - RSZ(PERF_MON_CPC), hSpace,
4108-
RSC(PERF_LABEL_CPC).CODE(),
4109-
ENABLED(RO(Shm)->Proc.Features.OSPM_CPC));
4110-
}
4111-
bix = (RO(Shm)->Proc.Features.Power.EAX.HWP_Reg == 1) /* Intel:HWP */
4112-
|| (RO(Shm)->Proc.Features.leaf80000008.EBX.CPPC == 1) /* AMD:CPPC */
4113-
|| (RO(Shm)->Proc.Features.ACPI_CPPC == 1); /* ACPI:CPPC */
4114-
if (bix)
4115-
{
4116-
CPU_STRUCT *SProc = &RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core];
4117-
struct FLIP_FLOP *CFlop = &SProc->FlipFlop[
4118-
!RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Toggle
4119-
];
4120-
ATTRIBUTE *HWP_Cap_Attr[2] = {
4121-
RSC(SYSINFO_PERFMON_HWP_CAP_COND0).ATTR(),
4122-
RSC(SYSINFO_PERFMON_HWP_CAP_COND1).ATTR()
4123-
};
4124-
bix = RO(Shm)->Proc.Features.HWP_Enable == 1;
4125-
4126-
if ( (RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_AMD)
4127-
|| (RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_HYGON) )
4128-
{
4129-
if (RO(Shm)->Proc.Features.ACPI_CPPC == 1)
4130-
{
4131-
GridHover( PUT( BOXKEY_FMW_CPPC,
4132-
attrib[RO(Shm)->Proc.Features.ACPI_CPPC], width, 2,
4133-
"%s%.*s%s <%3s>", RSC(PERF_MON_CPPC).CODE(),
4134-
width - 19 - RSZ(PERF_MON_CPPC), hSpace,
4135-
RSC(PERF_LABEL_CPPC).CODE(), RSC(FMW).CODE() ),
4136-
(char *) RSC(PERF_MON_CPPC_COMM).CODE() );
4137-
}
4138-
else
4139-
{
4140-
GridCall( PUT( BOXKEY_HWP, attrib[bix], width, 2,
4141-
"%s%.*s%s <%3s>", RSC(PERF_MON_CPPC).CODE(),
4142-
width - 19 - RSZ(PERF_MON_CPPC), hSpace,
4143-
RSC(PERF_LABEL_CPPC).CODE(), ENABLED(bix) ),
4144-
HWP_Update);
4145-
}
4146-
} else {
4147-
GridCall( PUT( BOXKEY_HWP, attrib[bix], width, 2,
4148-
"%s%.*s%s <%3s>", RSC(PERF_MON_HWP).CODE(),
4149-
width - 18 - RSZ(PERF_MON_HWP), hSpace,
4150-
RSC(PERF_LABEL_HWP).CODE(), ENABLED(bix) ),
4151-
HWP_Update);
4152-
}
4153-
PUT( SCANKEY_NULL, RSC(SYSINFO_PERFMON_HWP_CAP_COND1).ATTR(),
4154-
width, 3, "%s""%.*s""%s""%.*s""%s", RSC(CAPABILITIES).CODE(),
4155-
21 - 3 * (OutFunc == NULL) - RSZ(CAPABILITIES), hSpace,
4156-
RSC(PERF_MON_UNIT_HWP).CODE(), 22, hSpace, RSC(RATIO).CODE() );
4157-
4158-
GridCall(PrintRatioFreq(win, CFlop,
4159-
1, (char*) RSC(LOWEST).CODE(),
4160-
&SProc->PowerThermal.HWP.Capabilities.Lowest,
4161-
0, SCANKEY_NULL, width, OutFunc,
4162-
HWP_Cap_Attr[bix]),
4163-
Refresh_HWP_Cap_Freq,
4164-
&SProc->PowerThermal.HWP.Capabilities.Lowest);
4165-
4166-
GridCall(PrintRatioFreq(win, CFlop,
4167-
1, (char*) RSC(EFFICIENT).CODE(),
4168-
&SProc->PowerThermal.HWP.Capabilities.Most_Efficient,
4169-
0, SCANKEY_NULL, width, OutFunc,
4170-
HWP_Cap_Attr[bix]),
4171-
Refresh_HWP_Cap_Freq,
4172-
&SProc->PowerThermal.HWP.Capabilities.Most_Efficient);
4173-
4174-
GridCall(PrintRatioFreq(win, CFlop,
4175-
1, (char*) RSC(GUARANTEED).CODE(),
4176-
&SProc->PowerThermal.HWP.Capabilities.Guaranteed,
4177-
0, SCANKEY_NULL, width, OutFunc,
4178-
HWP_Cap_Attr[bix]),
4179-
Refresh_HWP_Cap_Freq,
4180-
&SProc->PowerThermal.HWP.Capabilities.Guaranteed);
4181-
4182-
GridCall(PrintRatioFreq(win, CFlop,
4183-
1, (char*) RSC(HIGHEST).CODE(),
4184-
&SProc->PowerThermal.HWP.Capabilities.Highest,
4185-
0, SCANKEY_NULL, width, OutFunc,
4186-
HWP_Cap_Attr[bix]),
4187-
Refresh_HWP_Cap_Freq,
4188-
&SProc->PowerThermal.HWP.Capabilities.Highest);
4189-
}
4190-
else if ( (RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_AMD)
4191-
|| (RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_HYGON) )
4192-
{
4193-
PUT( SCANKEY_NULL, attrib[4], width, 2,
4194-
"%s%.*s%s [%3s]", RSC(PERF_MON_CPPC).CODE(),
4195-
width - 19 - RSZ(PERF_MON_CPPC), hSpace,
4196-
RSC(PERF_LABEL_CPPC).CODE(), RSC(NOT_AVAILABLE).CODE() );
4197-
} else {
4198-
const unsigned int cix = ((RO(Shm)->Proc.Features.HWP_Enable == 1)
4199-
|| (RO(Shm)->Proc.Features.ACPI_CPPC == 1));
4200-
4201-
PUT( SCANKEY_NULL, attrib[bix], width, 2,
4202-
"%s%.*s%s [%3s]", RSC(PERF_MON_HWP).CODE(),
4203-
width - 18 - RSZ(PERF_MON_HWP), hSpace,
4204-
RSC(PERF_LABEL_HWP).CODE(), ENABLED(cix) );
4205-
}
42064141
/* Section Mark */
42074142
if (RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_INTEL)
42084143
{
@@ -4392,6 +4327,116 @@ REASON_CODE SysInfoPerfMon(Window *win, CUINT width, CELL_FUNC OutFunc)
43924327
"%s%.*s[%7s]", RSC(PERF_MON_CORE).CODE(),
43934328
width - 12 - RSZ(PERF_MON_CORE), hSpace, POWERED(bix) );
43944329
}
4330+
/* Section Mark */
4331+
if ( (RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_AMD)
4332+
|| (RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_HYGON) )
4333+
{
4334+
PUT(SCANKEY_NULL, attrib[RO(Shm)->Proc.Features.OSPM_CPC], width, 2,
4335+
"%s%.*s%s [%3s]", RSC(PERF_MON_CPC).CODE(),
4336+
width - 19 - RSZ(PERF_MON_CPC), hSpace,
4337+
RSC(PERF_LABEL_CPC).CODE(),
4338+
ENABLED(RO(Shm)->Proc.Features.OSPM_CPC));
4339+
}
4340+
bix = (RO(Shm)->Proc.Features.Power.EAX.HWP_Reg == 1) /* Intel:HWP */
4341+
|| (RO(Shm)->Proc.Features.leaf80000008.EBX.CPPC == 1) /* AMD:CPPC */
4342+
|| (RO(Shm)->Proc.Features.ACPI_CPPC == 1); /* ACPI:CPPC */
4343+
if (bix)
4344+
{
4345+
ATTRIBUTE *HWP_Cap_Attr[2] = {
4346+
RSC(SYSINFO_PERFMON_HWP_CAP_COND0).ATTR(),
4347+
RSC(SYSINFO_PERFMON_HWP_CAP_COND1).ATTR()
4348+
};
4349+
unsigned int cpu;
4350+
4351+
bix = RO(Shm)->Proc.Features.HWP_Enable == 1;
4352+
4353+
if ( (RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_AMD)
4354+
|| (RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_HYGON) )
4355+
{
4356+
if (RO(Shm)->Proc.Features.ACPI_CPPC == 1)
4357+
{
4358+
GridHover( PUT( BOXKEY_FMW_CPPC,
4359+
attrib[RO(Shm)->Proc.Features.ACPI_CPPC], width, 2,
4360+
"%s%.*s%s <%3s>", RSC(PERF_MON_CPPC).CODE(),
4361+
width - 19 - RSZ(PERF_MON_CPPC), hSpace,
4362+
RSC(PERF_LABEL_CPPC).CODE(), RSC(FMW).CODE() ),
4363+
(char *) RSC(PERF_MON_CPPC_COMM).CODE() );
4364+
}
4365+
else
4366+
{
4367+
GridCall( PUT( BOXKEY_HWP, attrib[bix], width, 2,
4368+
"%s%.*s%s <%3s>", RSC(PERF_MON_CPPC).CODE(),
4369+
width - 19 - RSZ(PERF_MON_CPPC), hSpace,
4370+
RSC(PERF_LABEL_CPPC).CODE(), ENABLED(bix) ),
4371+
HWP_Update);
4372+
}
4373+
} else {
4374+
GridCall( PUT( BOXKEY_HWP, attrib[bix], width, 2,
4375+
"%s%.*s%s <%3s>", RSC(PERF_MON_HWP).CODE(),
4376+
width - 18 - RSZ(PERF_MON_HWP), hSpace,
4377+
RSC(PERF_LABEL_HWP).CODE(), ENABLED(bix) ),
4378+
HWP_Update);
4379+
}
4380+
4381+
PUT( SCANKEY_NULL, RSC(SYSINFO_PERFMON_HWP_CAP_COND1).ATTR(),
4382+
width, 3, "%s %s %s %s %s",
4383+
RSC(CAPABILITIES).CODE(),
4384+
RSC(LOWEST).CODE(), RSC(EFFICIENT).CODE(),
4385+
RSC(GUARANTEED).CODE(), RSC(HIGHEST).CODE());
4386+
4387+
for (cpu = 0; cpu < RO(Shm)->Proc.CPU.Count; cpu++)
4388+
{
4389+
CPU_STRUCT *SProc = &RO(Shm)->Cpu[cpu];
4390+
struct FLIP_FLOP *CFlop = &SProc->FlipFlop[!RO(Shm)->Cpu[cpu].Toggle];
4391+
4392+
double Lowest_MHz = ABS_FREQ_MHz(double,
4393+
SProc->PowerThermal.HWP.Capabilities.Lowest,
4394+
CFlop->Clock
4395+
),
4396+
Efficient_MHz = ABS_FREQ_MHz(double,
4397+
SProc->PowerThermal.HWP.Capabilities.Most_Efficient,
4398+
CFlop->Clock
4399+
),
4400+
Guaranteed_MHz = ABS_FREQ_MHz(double,
4401+
SProc->PowerThermal.HWP.Capabilities.Guaranteed,
4402+
CFlop->Clock
4403+
),
4404+
Highest_MHz = ABS_FREQ_MHz(double,
4405+
SProc->PowerThermal.HWP.Capabilities.Highest,
4406+
CFlop->Clock
4407+
);
4408+
4409+
GridCall(
4410+
PUT(SCANKEY_NULL, HWP_Cap_Attr[bix], width, 3,
4411+
"CPU #%-3u %7.2f (%3u) %7.2f (%3u) %7.2f (%3u) %7.2f (%3u)",
4412+
cpu,
4413+
Lowest_MHz,
4414+
SProc->PowerThermal.HWP.Capabilities.Lowest,
4415+
Efficient_MHz,
4416+
SProc->PowerThermal.HWP.Capabilities.Most_Efficient,
4417+
Guaranteed_MHz,
4418+
SProc->PowerThermal.HWP.Capabilities.Guaranteed,
4419+
Highest_MHz,
4420+
SProc->PowerThermal.HWP.Capabilities.Highest),
4421+
Refresh_HWP_Cap_Freq, cpu);
4422+
}
4423+
}
4424+
else if ( (RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_AMD)
4425+
|| (RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_HYGON) )
4426+
{
4427+
PUT( SCANKEY_NULL, attrib[4], width, 2,
4428+
"%s%.*s%s [%3s]", RSC(PERF_MON_CPPC).CODE(),
4429+
width - 19 - RSZ(PERF_MON_CPPC), hSpace,
4430+
RSC(PERF_LABEL_CPPC).CODE(), RSC(NOT_AVAILABLE).CODE() );
4431+
} else {
4432+
const unsigned int cix = ((RO(Shm)->Proc.Features.HWP_Enable == 1)
4433+
|| (RO(Shm)->Proc.Features.ACPI_CPPC == 1));
4434+
4435+
PUT( SCANKEY_NULL, attrib[bix], width, 2,
4436+
"%s%.*s%s [%3s]", RSC(PERF_MON_HWP).CODE(),
4437+
width - 18 - RSZ(PERF_MON_HWP), hSpace,
4438+
RSC(PERF_LABEL_HWP).CODE(), ENABLED(cix) );
4439+
}
43954440
return reason;
43964441
}
43974442

0 commit comments

Comments
 (0)