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cyringCyrIng
cyring
authored and
CyrIng
committed
[UI] Show the DDR5 RCDw timing of Intel IMC
1 parent a0c7935 commit 5ec0498

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5 files changed

+36
-44
lines changed

5 files changed

+36
-44
lines changed

‎corefreq-cli-rsc-en.h‎

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1421,6 +1421,8 @@
14211421
#define RSC_DDR3_CKE_COMM_CODE_EN " tCKE ( ClocK Enable ) "
14221422
#define RSC_DDR3_ECC_COMM_CODE_EN " ECC ( Error Correcting Code ) "
14231423

1424+
#define RSC_DDR4_RCD_R_COMM_CODE_EN " tRCD_R ( Activate to Read CAS ) "
1425+
#define RSC_DDR4_RCD_W_COMM_CODE_EN " tRCD_W ( Activate to Write CAS ) "
14241426
#define RSC_DDR4_RDRD_SCL_COMM_CODE_EN " tRDRD ( Read to Read, Same Bank ) "
14251427
#define RSC_DDR4_RDRD_SC_COMM_CODE_EN " tRDRD ( Read to Read, Different Bank ) "
14261428
#define RSC_DDR4_RDRD_SD_COMM_CODE_EN " tRDRD ( Read to Read, Different Rank ) "
@@ -1467,8 +1469,6 @@
14671469
#define RSC_DDR4_CPDED_COMM_CODE_EN " tCPDED ( Command Pass Disable Delay ) "
14681470
#define RSC_DDR4_GEAR_COMM_CODE_EN " GEAR ( Clock Gear Mode ) "
14691471

1470-
#define RSC_DDR4_ZEN_RCD_R_COMM_CODE_EN " tRCD_R ( Activate to Read CAS ) "
1471-
#define RSC_DDR4_ZEN_RCD_W_COMM_CODE_EN " tRCD_W ( Activate to Write CAS ) "
14721472
#define RSC_DDR4_ZEN_RC_COMM_CODE_EN " tRC ( Activate to Activate ) "
14731473

14741474
#define RSC_DDR4_ZEN_WTR_S_COMM_CODE_EN \
@@ -2399,7 +2399,8 @@
23992399
#define RSC_DDR3_ECC_CODE " ECC"
24002400

24012401
#define RSC_DDR4_CL_CODE " CL"
2402-
#define RSC_DDR4_RCD_CODE " RCD"
2402+
#define RSC_DDR4_RCD_R_CODE " RCDr"
2403+
#define RSC_DDR4_RCD_W_CODE " RCDw"
24032404
#define RSC_DDR4_RP_CODE " RP"
24042405
#define RSC_DDR4_RAS_CODE " RAS"
24052406
#define RSC_DDR4_RRD_CODE " RRD"
@@ -2410,7 +2411,7 @@
24102411
#define RSC_DDR4_FAW_CODE " FAW"
24112412
#define RSC_DDR4_GEAR_CODE " GEAR"
24122413
#define RSC_DDR4_CWL_CODE " CWL"
2413-
#define RSC_DDR4_CMD_CODE " CMD "
2414+
#define RSC_DDR4_CMD_CODE " CMD"
24142415
#define RSC_DDR4_REFI_CODE " REFI"
24152416
#define RSC_DDR4_RDRD_SCL_CODE " sgRR"
24162417
#define RSC_DDR4_RDRD_SC_CODE " dgRR"
@@ -2430,13 +2431,11 @@
24302431
#define RSC_DDR4_WRWR_DD_CODE " ddWW"
24312432
#define RSC_DDR4_RRD_S_CODE " RRDs"
24322433
#define RSC_DDR4_RRD_L_CODE " RRDl"
2433-
#define RSC_DDR4_CKE_CODE " CKE "
2434+
#define RSC_DDR4_CKE_CODE " CKE"
24342435
#define RSC_DDR4_CPDED_CODE "CPDED"
24352436
#define RSC_DDR4_ECC_CODE " ECC"
24362437

24372438
#define RSC_DDR4_ZEN_CL_CODE " CL "
2438-
#define RSC_DDR4_ZEN_RCD_R_CODE " RCDr"
2439-
#define RSC_DDR4_ZEN_RCD_W_CODE " RCDw"
24402439
#define RSC_DDR4_ZEN_RP_CODE " RP "
24412440
#define RSC_DDR4_ZEN_RAS_CODE " RAS "
24422441
#define RSC_DDR4_ZEN_RC_CODE " RC "
@@ -2470,8 +2469,6 @@
24702469
#define RSC_DDR4_ZEN_BGS_ALT_CODE ":Alt "
24712470
#define RSC_DDR4_ZEN_BAN_CODE " Ban "
24722471
#define RSC_DDR4_ZEN_RCPAGE_CODE " Page"
2473-
#define RSC_DDR4_ZEN_CKE_CODE " CKE"
2474-
#define RSC_DDR4_ZEN_CMD_CODE " CMD"
24752472
#define RSC_DDR4_ZEN_GDM_CODE " GDM"
24762473
#define RSC_DDR4_ZEN_ECC_CODE " ECC"
24772474
#define RSC_DDR4_ZEN_MRD_CODE " MRD:"

‎corefreq-cli-rsc-fr.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -879,6 +879,8 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
879879
#define RSC_DDR3_CKE_COMM_CODE_FR RSC_DDR3_CKE_COMM_CODE_EN
880880
#define RSC_DDR3_ECC_COMM_CODE_FR RSC_DDR3_ECC_COMM_CODE_EN
881881

882+
#define RSC_DDR4_RCD_R_COMM_CODE_FR RSC_DDR4_RCD_R_COMM_CODE_EN
883+
#define RSC_DDR4_RCD_W_COMM_CODE_FR RSC_DDR4_RCD_W_COMM_CODE_EN
882884
#define RSC_DDR4_RDRD_SCL_COMM_CODE_FR RSC_DDR4_RDRD_SCL_COMM_CODE_EN
883885
#define RSC_DDR4_RDRD_SC_COMM_CODE_FR RSC_DDR4_RDRD_SC_COMM_CODE_EN
884886
#define RSC_DDR4_RDRD_SD_COMM_CODE_FR RSC_DDR4_RDRD_SD_COMM_CODE_EN
@@ -900,8 +902,6 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
900902
#define RSC_DDR4_CPDED_COMM_CODE_FR RSC_DDR4_CPDED_COMM_CODE_EN
901903
#define RSC_DDR4_GEAR_COMM_CODE_FR RSC_DDR4_GEAR_COMM_CODE_EN
902904

903-
#define RSC_DDR4_ZEN_RCD_R_COMM_CODE_FR RSC_DDR4_ZEN_RCD_R_COMM_CODE_EN
904-
#define RSC_DDR4_ZEN_RCD_W_COMM_CODE_FR RSC_DDR4_ZEN_RCD_W_COMM_CODE_EN
905905
#define RSC_DDR4_ZEN_RC_COMM_CODE_FR RSC_DDR4_ZEN_RC_COMM_CODE_EN
906906
#define RSC_DDR4_ZEN_WTR_S_COMM_CODE_FR RSC_DDR4_ZEN_WTR_S_COMM_CODE_EN
907907
#define RSC_DDR4_ZEN_WTR_L_COMM_CODE_FR RSC_DDR4_ZEN_WTR_L_COMM_CODE_EN

‎corefreq-cli-rsc.c‎

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1330,7 +1330,8 @@ RESOURCE_ST Resource[] = {
13301330
LDQ(RSC_DDR3_CKE),
13311331
LDQ(RSC_DDR3_ECC),
13321332
LDQ(RSC_DDR4_CL),
1333-
LDQ(RSC_DDR4_RCD),
1333+
LDQ(RSC_DDR4_RCD_R),
1334+
LDQ(RSC_DDR4_RCD_W),
13341335
LDQ(RSC_DDR4_RP),
13351336
LDQ(RSC_DDR4_RAS),
13361337
LDQ(RSC_DDR4_RRD),
@@ -1365,8 +1366,6 @@ RESOURCE_ST Resource[] = {
13651366
LDQ(RSC_DDR4_CPDED),
13661367
LDQ(RSC_DDR4_ECC),
13671368
LDQ(RSC_DDR4_ZEN_CL),
1368-
LDQ(RSC_DDR4_ZEN_RCD_R),
1369-
LDQ(RSC_DDR4_ZEN_RCD_W),
13701369
LDQ(RSC_DDR4_ZEN_RP),
13711370
LDQ(RSC_DDR4_ZEN_RAS),
13721371
LDQ(RSC_DDR4_ZEN_RC),
@@ -1400,8 +1399,6 @@ RESOURCE_ST Resource[] = {
14001399
LDQ(RSC_DDR4_ZEN_BGS_ALT),
14011400
LDQ(RSC_DDR4_ZEN_BAN),
14021401
LDQ(RSC_DDR4_ZEN_RCPAGE),
1403-
LDQ(RSC_DDR4_ZEN_CKE),
1404-
LDQ(RSC_DDR4_ZEN_CMD),
14051402
LDQ(RSC_DDR4_ZEN_GDM),
14061403
LDQ(RSC_DDR4_ZEN_ECC),
14071404
LDQ(RSC_DDR4_ZEN_MRD),
@@ -1449,6 +1446,8 @@ RESOURCE_ST Resource[] = {
14491446
LDT(RSC_DDR3_XP_COMM),
14501447
LDT(RSC_DDR3_CKE_COMM),
14511448
LDT(RSC_DDR3_ECC_COMM),
1449+
LDT(RSC_DDR4_RCD_R_COMM),
1450+
LDT(RSC_DDR4_RCD_W_COMM),
14521451
LDT(RSC_DDR4_RDRD_SCL_COMM),
14531452
LDT(RSC_DDR4_RDRD_SC_COMM),
14541453
LDT(RSC_DDR4_RDRD_SD_COMM),
@@ -1469,8 +1468,6 @@ RESOURCE_ST Resource[] = {
14691468
LDT(RSC_DDR4_RRD_L_COMM),
14701469
LDT(RSC_DDR4_CPDED_COMM),
14711470
LDT(RSC_DDR4_GEAR_COMM),
1472-
LDT(RSC_DDR4_ZEN_RCD_R_COMM),
1473-
LDT(RSC_DDR4_ZEN_RCD_W_COMM),
14741471
LDT(RSC_DDR4_ZEN_RC_COMM),
14751472
LDT(RSC_DDR4_ZEN_WTR_S_COMM),
14761473
LDT(RSC_DDR4_ZEN_WTR_L_COMM),

‎corefreq-cli-rsc.h‎

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1133,7 +1133,8 @@ enum {
11331133
RSC_DDR3_CKE,
11341134
RSC_DDR3_ECC,
11351135
RSC_DDR4_CL,
1136-
RSC_DDR4_RCD,
1136+
RSC_DDR4_RCD_R,
1137+
RSC_DDR4_RCD_W,
11371138
RSC_DDR4_RP,
11381139
RSC_DDR4_RAS,
11391140
RSC_DDR4_RRD,
@@ -1168,8 +1169,6 @@ enum {
11681169
RSC_DDR4_CPDED,
11691170
RSC_DDR4_ECC,
11701171
RSC_DDR4_ZEN_CL,
1171-
RSC_DDR4_ZEN_RCD_R,
1172-
RSC_DDR4_ZEN_RCD_W,
11731172
RSC_DDR4_ZEN_RP,
11741173
RSC_DDR4_ZEN_RAS,
11751174
RSC_DDR4_ZEN_RC,
@@ -1203,8 +1202,6 @@ enum {
12031202
RSC_DDR4_ZEN_BGS_ALT,
12041203
RSC_DDR4_ZEN_BAN,
12051204
RSC_DDR4_ZEN_RCPAGE,
1206-
RSC_DDR4_ZEN_CKE,
1207-
RSC_DDR4_ZEN_CMD,
12081205
RSC_DDR4_ZEN_GDM,
12091206
RSC_DDR4_ZEN_ECC,
12101207
RSC_DDR4_ZEN_MRD,
@@ -1252,6 +1249,8 @@ enum {
12521249
RSC_DDR3_XP_COMM,
12531250
RSC_DDR3_CKE_COMM,
12541251
RSC_DDR3_ECC_COMM,
1252+
RSC_DDR4_RCD_R_COMM,
1253+
RSC_DDR4_RCD_W_COMM,
12551254
RSC_DDR4_RDRD_SCL_COMM,
12561255
RSC_DDR4_RDRD_SC_COMM,
12571256
RSC_DDR4_RDRD_SD_COMM,
@@ -1272,8 +1271,6 @@ enum {
12721271
RSC_DDR4_RRD_L_COMM,
12731272
RSC_DDR4_CPDED_COMM,
12741273
RSC_DDR4_GEAR_COMM,
1275-
RSC_DDR4_ZEN_RCD_R_COMM,
1276-
RSC_DDR4_ZEN_RCD_W_COMM,
12771274
RSC_DDR4_ZEN_RC_COMM,
12781275
RSC_DDR4_ZEN_WTR_S_COMM,
12791276
RSC_DDR4_ZEN_WTR_L_COMM,

‎corefreq-cli.c‎

Lines changed: 20 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -7035,7 +7035,8 @@ void Timing_DDR4(Window *win,
70357035
{
70367036
RSC(MEM_CTRL_CHANNEL).CODE(),
70377037
RSC(DDR4_CL).CODE(),
7038-
RSC(DDR4_RCD).CODE(),
7038+
RSC(DDR4_RCD_R).CODE(),
7039+
RSC(DDR4_RCD_W).CODE(),
70397040
RSC(DDR4_RP).CODE(),
70407041
RSC(DDR4_RAS).CODE(),
70417042
RSC(DDR4_RRD_S).CODE(),
@@ -7046,8 +7047,7 @@ void Timing_DDR4(Window *win,
70467047
RSC(DDR4_WTP).CODE(),
70477048
RSC(DDR4_CWL).CODE(),
70487049
RSC(DDR4_CKE).CODE(),
7049-
RSC(DDR4_CMD).CODE(),
7050-
RSC(DDR4_GEAR).CODE()
7050+
RSC(DDR4_CMD).CODE()
70517051
},
70527052
{
70537053
RSC(MEM_CTRL_MTY_CELL).CODE(),
@@ -7075,20 +7075,21 @@ void Timing_DDR4(Window *win,
70757075
RSC(MEM_CTRL_MTY_CELL).CODE(),
70767076
RSC(MEM_CTRL_MTY_CELL).CODE(),
70777077
RSC(MEM_CTRL_MTY_CELL).CODE(),
7078-
RSC(MEM_CTRL_MTY_CELL).CODE(),
70797078
RSC(DDR4_REFI).CODE(),
70807079
RSC(DDR4_RFC).CODE(),
70817080
RSC(DDR3_XS).CODE(),
70827081
RSC(DDR3_XP).CODE(),
70837082
RSC(DDR4_CPDED).CODE(),
7083+
RSC(DDR4_GEAR).CODE(),
70847084
RSC(DDR4_ECC).CODE()
70857085
}
70867086
};
70877087
const ASCII *Footer_DDR4[3][MC_MATX] = {
70887088
{
70897089
NULL,
70907090
RSC(DDR3_CL_COMM).CODE(),
7091-
RSC(DDR3_RCD_COMM).CODE(),
7091+
RSC(DDR4_RCD_R_COMM).CODE(),
7092+
RSC(DDR4_RCD_W_COMM).CODE(),
70927093
RSC(DDR3_RP_COMM).CODE(),
70937094
RSC(DDR3_RAS_COMM).CODE(),
70947095
RSC(DDR4_RRD_S_COMM).CODE(),
@@ -7099,8 +7100,7 @@ void Timing_DDR4(Window *win,
70997100
RSC(DDR3_WTP_COMM).CODE(),
71007101
RSC(DDR3_CWL_COMM).CODE(),
71017102
RSC(DDR3_CKE_COMM).CODE(),
7102-
RSC(DDR3_CMD_COMM).CODE(),
7103-
RSC(DDR4_GEAR_COMM).CODE()
7103+
RSC(DDR3_CMD_COMM).CODE()
71047104
},
71057105
{
71067106
NULL,
@@ -7128,12 +7128,12 @@ void Timing_DDR4(Window *win,
71287128
NULL,
71297129
NULL,
71307130
NULL,
7131-
NULL,
71327131
RSC(DDR3_REFI_COMM).CODE(),
71337132
RSC(DDR3_RFC_COMM).CODE(),
71347133
RSC(DDR3_XS_COMM).CODE(),
71357134
RSC(DDR3_XP_COMM).CODE(),
71367135
RSC(DDR4_CPDED_COMM).CODE(),
7136+
RSC(DDR4_GEAR_COMM).CODE(),
71377137
RSC(DDR3_ECC_COMM).CODE()
71387138
}
71397139
};
@@ -7153,7 +7153,8 @@ void Timing_DDR4(Window *win,
71537153
PRT(IMC, attrib[0], "\x20\x20#%-2u", cha);
71547154

71557155
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tCL);
7156-
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRCD);
7156+
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRCD_RD);
7157+
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRCD_WR);
71577158
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRP);
71587159
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRAS);
71597160
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRRDS);
@@ -7163,9 +7164,8 @@ void Timing_DDR4(Window *win,
71637164
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRTPr);
71647165
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tWTPr);
71657166
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tCWL);
7166-
PRT(IMC, attrib[1], "%4u\x20", TIMING(mc, cha).tCKE);
7167-
PRT(IMC, attrib[1], "%3uT\x20", TIMING(mc, cha).CMD_Rate);
7168-
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).GEAR);
7167+
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tCKE);
7168+
PRT(IMC, attrib[1], "\x20%3uT", TIMING(mc, cha).CMD_Rate);
71697169
}
71707170
for (nc = 0; nc < MC_MATX; nc++) {
71717171
GridHover( PRT(IMC, attrib[0], Header_DDR4[1][nc]),
@@ -7209,7 +7209,7 @@ void Timing_DDR4(Window *win,
72097209
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tWRWR_DR);
72107210
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tWRWR_DD);
72117211

7212-
for (nc = 0; nc < (MC_MATX - 12); nc++) {
7212+
for (nc = 0; nc < (MC_MATX - 13); nc++) {
72137213
PRT(IMC, attrib[0], MEM_CTRL_FMT, MC_MATY, HSPACE);
72147214
}
72157215

@@ -7221,6 +7221,7 @@ void Timing_DDR4(Window *win,
72217221
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tXS);
72227222
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tXP);
72237223
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tCPDED);
7224+
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).GEAR);
72247225
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).ECC);
72257226
}
72267227
}
@@ -7235,8 +7236,8 @@ void Timing_DRAM_Zen( Window *win,
72357236
{
72367237
RSC(MEM_CTRL_CHANNEL).CODE(),
72377238
RSC(DDR4_ZEN_CL).CODE(),
7238-
RSC(DDR4_ZEN_RCD_R).CODE(),
7239-
RSC(DDR4_ZEN_RCD_W).CODE(),
7239+
RSC(DDR4_RCD_R).CODE(),
7240+
RSC(DDR4_RCD_W).CODE(),
72407241
RSC(DDR4_ZEN_RP).CODE(),
72417242
RSC(DDR4_ZEN_RAS).CODE(),
72427243
RSC(DDR4_ZEN_RC).CODE(),
@@ -7286,8 +7287,8 @@ void Timing_DRAM_Zen( Window *win,
72867287
RSC(DDR4_ZEN_BGS_ALT).CODE(),
72877288
RSC(DDR4_ZEN_BAN).CODE(),
72887289
RSC(DDR4_ZEN_RCPAGE).CODE(),
7289-
RSC(DDR4_ZEN_CKE).CODE(),
7290-
RSC(DDR4_ZEN_CMD).CODE(),
7290+
RSC(DDR4_CKE).CODE(),
7291+
RSC(DDR4_CMD).CODE(),
72917292
RSC(DDR4_ZEN_GDM).CODE(),
72927293
RSC(DDR4_ZEN_ECC).CODE()
72937294
},
@@ -7313,8 +7314,8 @@ void Timing_DRAM_Zen( Window *win,
73137314
{
73147315
NULL,
73157316
RSC(DDR3_CL_COMM).CODE(),
7316-
RSC(DDR4_ZEN_RCD_R_COMM).CODE(),
7317-
RSC(DDR4_ZEN_RCD_W_COMM).CODE(),
7317+
RSC(DDR4_RCD_R_COMM).CODE(),
7318+
RSC(DDR4_RCD_W_COMM).CODE(),
73187319
RSC(DDR3_RP_COMM).CODE(),
73197320
RSC(DDR3_RAS_COMM).CODE(),
73207321
RSC(DDR4_ZEN_RC_COMM).CODE(),

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