[riscv64] mvendorid & marchid based architecture qualification

Author: cyring

riscv64/corefreqk.c

@@ -8,6 +8,7 @@
 #include <linux/module.h>
 #include <linux/cpu.h>
 #include <linux/pci.h>
+#include <asm/sbi.h>
 #ifdef CONFIG_DMI
 #include <linux/dmi.h>
 #endif /* CONFIG_DMI */
@@ -507,6 +508,9 @@ static void Query_Features(void *pArg)
 {
 	INIT_ARG *iArg = (INIT_ARG *) pArg;
 	volatile unsigned long long timectr, instret, perfctr;
+	const unsigned long
+		mvendorid = riscv_cached_mvendorid(iArg->localProcessor),
+		marchid = riscv_cached_marchid(iArg->localProcessor);
 
 	iArg->Features->Info.Vendor.CRC = CRC_RESERVED;
 	iArg->SMT_Count = 1;
@@ -527,10 +531,10 @@ static void Query_Features(void *pArg)
 	iArg->Features->PerfMon.InstrRetired  = instret != 0 ? 0b1 : 0b0;
 
 	iArg->Features->Info.Signature.Stepping = 0;
-	iArg->Features->Info.Signature.Family = 0 & 0x00f;
-	iArg->Features->Info.Signature.ExtFamily = (0 & 0xff0) >> 4;
-	iArg->Features->Info.Signature.Model = 0 & 0x0f;
-	iArg->Features->Info.Signature.ExtModel = (0 & 0xf0) >> 4;
+	iArg->Features->Info.Signature.Family = mvendorid & 0x00f;
+	iArg->Features->Info.Signature.ExtFamily = (mvendorid & 0xff0) >> 4;
+	iArg->Features->Info.Signature.Model = marchid & 0x0f;
+	iArg->Features->Info.Signature.ExtModel = (marchid & 0xf0) >> 4;
 /*
 	VendorFromMainID(midr, iArg->Features->Info.Vendor.ID,
 			&iArg->Features->Info.Vendor.CRC, &iArg->HypervisorID);
@@ -887,7 +891,7 @@ static void OverrideCodeNameString(PROCESSOR_SPECIFIC *pSpecific)
 	StrCopy(PUBLIC(RO(Proc))->Architecture,
 		Arch[
 			PUBLIC(RO(Proc))->ArchID
-		].Architecture.Brand[pSpecific->CodeNameIdx], CODENAME_LEN);
+		].Architecture[pSpecific->CodeNameIdx], CODENAME_LEN);
 }
 
 static void OverrideUnlockCapability(PROCESSOR_SPECIFIC *pSpecific)
@@ -4491,9 +4495,6 @@ static int CoreFreqK_Scale_And_Compute_Level_Up(INIT_ARG *pArg)
 
 	memcpy(&PUBLIC(RO(Proc))->Features, pArg->Features, sizeof(FEATURES));
 
-	/* Initialize default uArch's codename with the CPUID brand.	*/
-	Arch[GenuineArch].Architecture.Brand[0] = \
-				PUBLIC(RO(Proc))->Features.Info.Vendor.ID;
 	/* Initialize with any hypervisor found so far.			*/
 	PUBLIC(RO(Proc))->HypervisorID = pArg->HypervisorID;
 	return 0;
@@ -4658,12 +4659,13 @@ static int CoreFreqK_Ignition_Level_Up(INIT_ARG *pArg)
 	}
 	/*	Set the uArch's name with the first found codename	*/
 	StrCopy(PUBLIC(RO(Proc))->Architecture,
-		CodeName[Arch[PUBLIC(RO(Proc))->ArchID].Architecture.CN],
+		Arch[PUBLIC(RO(Proc))->ArchID].Architecture[0],
 		CODENAME_LEN);
 
-	StrCopy(PUBLIC(RO(Proc))->Features.Info.Brand,
-		Arch[PUBLIC(RO(Proc))->ArchID].Architecture.Brand[0],
-		BRAND_SIZE);
+	StrCopy(PUBLIC(RO(Proc))->Features.Info.Vendor.ID,
+		PUBLIC(RO(Proc))->Architecture,
+		12 + 4);
+
 	/*	Check if the Processor is actually virtualized ?	*/
 	#ifdef CONFIG_XEN
 	if (xen_pv_domain() || xen_hvm_domain())

riscv64/corefreqk.h

@@ -257,11 +257,6 @@ typedef struct {
 	void			(*SetTarget)(void *arg);
 } SYSTEM_DRIVER;
 
-typedef struct {
-	char			**Brand;
-	enum CODENAME		CN;
-} ARCH_ST;
-
 typedef struct
 {
 	struct	SIGNATURE	Signature;
@@ -285,7 +280,7 @@ typedef struct
 	} Uncore;
 	PROCESSOR_SPECIFIC	*Specific;
 	SYSTEM_DRIVER		SystemDriver;
-	ARCH_ST			Architecture;
+	char			**Architecture;
 } ARCH;
 
 static CLOCK BaseClock_GenericMachine(unsigned int ratio) ;
@@ -296,19 +291,27 @@ static void Stop_GenericMachine(void *arg) ;
 static void InitTimer_GenericMachine(unsigned int cpu) ;
 
 /*	[Void]								*/
-#define _Void_Signature {.ExtFamily=0x00, .Family=0x0, .ExtModel=0x0, .Model=0x0}
+#define _Void_Signature {.ExtFamily=0x00,.Family=0x0, .ExtModel=0x0,.Model=0x0}
+#define _Andes {.ExtFamily=0x31, .Family=0xE, .ExtModel=0x0, .Model=0x0}
+#define _SiFive {.ExtFamily=0x48, .Family=0x9, .ExtModel=0x0, .Model=0x0}
+#define _T_Head {.ExtFamily=0x5B, .Family=0x7, .ExtModel=0x0, .Model=0x0}
+#define _Veyron {.ExtFamily=0x61, .Family=0xF, .ExtModel=0x0, .Model=0x0}
+#define _SpacemiT {.ExtFamily=0x71, .Family=0x0, .ExtModel=0x0, .Model=0x0}
 
 typedef kernel_ulong_t (*PCI_CALLBACK)(struct pci_dev *);
 
 static struct pci_device_id PCI_Void_ids[] = {
 	{0, }
 };
 
-static char *CodeName[CODENAMES] = {
-	[    RV64]	= "RV64"
-};
+static char *Arch_Generic[]	=	ZLIST("RV64");
+static char *Arch_Andes[]	=	ZLIST("Andes");
+static char *Arch_SiFive[]	=	ZLIST("SiFive");
+static char *Arch_T_Head[]	=	ZLIST("T-Head");
+static char *Arch_Veyron[]	=	ZLIST("Veyron");
+static char *Arch_SpacemiT[]	=	ZLIST("SpacemiT");
 
-#define Arch_Misc_Processor {.Brand = ZLIST(NULL), .CN = RV64}
+static PROCESSOR_SPECIFIC Void_Specific[] = { {0} };
 
 static PROCESSOR_SPECIFIC Misc_Specific_Processor[] = {
 	{0}
@@ -373,6 +376,146 @@ static ARCH Arch[ARCHITECTURES] = {
 		},
 	.Specific = Misc_Specific_Processor,
 	.SystemDriver = VOID_Driver,
-	.Architecture = Arch_Misc_Processor
+	.Architecture = Arch_Generic
+	},
+[Andes] = {
+	.Signature = _Andes,
+	.Query = Query_GenericMachine,
+	.Update = PerCore_GenericMachine,
+	.Start = Start_GenericMachine,
+	.Stop = Stop_GenericMachine,
+	.Exit = NULL,
+	.Timer = InitTimer_GenericMachine,
+	.BaseClock = BaseClock_GenericMachine,
+	.ClockMod = NULL,
+	.TurboClock = NULL,
+	.thermalFormula = THERMAL_FORMULA_NONE,
+#ifdef CONFIG_PM_OPP
+	.voltageFormula = VOLTAGE_FORMULA_OPP,
+#else
+	.voltageFormula = VOLTAGE_FORMULA_NONE,
+#endif
+	.powerFormula   = POWER_FORMULA_NONE,
+	.PCI_ids = PCI_Void_ids,
+	.Uncore = {
+		.Start = NULL,
+		.Stop = NULL,
+		.ClockMod = NULL
+		},
+	.Specific = Void_Specific,
+	.SystemDriver = VOID_Driver,
+	.Architecture = Arch_Andes
+	},
+[SiFive] = {
+	.Signature = _SiFive,
+	.Query = Query_GenericMachine,
+	.Update = PerCore_GenericMachine,
+	.Start = Start_GenericMachine,
+	.Stop = Stop_GenericMachine,
+	.Exit = NULL,
+	.Timer = InitTimer_GenericMachine,
+	.BaseClock = BaseClock_GenericMachine,
+	.ClockMod = NULL,
+	.TurboClock = NULL,
+	.thermalFormula = THERMAL_FORMULA_NONE,
+#ifdef CONFIG_PM_OPP
+	.voltageFormula = VOLTAGE_FORMULA_OPP,
+#else
+	.voltageFormula = VOLTAGE_FORMULA_NONE,
+#endif
+	.powerFormula   = POWER_FORMULA_NONE,
+	.PCI_ids = PCI_Void_ids,
+	.Uncore = {
+		.Start = NULL,
+		.Stop = NULL,
+		.ClockMod = NULL
+		},
+	.Specific = Void_Specific,
+	.SystemDriver = VOID_Driver,
+	.Architecture = Arch_SiFive
 	},
+[T_Head] = {
+	.Signature = _T_Head,
+	.Query = Query_GenericMachine,
+	.Update = PerCore_GenericMachine,
+	.Start = Start_GenericMachine,
+	.Stop = Stop_GenericMachine,
+	.Exit = NULL,
+	.Timer = InitTimer_GenericMachine,
+	.BaseClock = BaseClock_GenericMachine,
+	.ClockMod = NULL,
+	.TurboClock = NULL,
+	.thermalFormula = THERMAL_FORMULA_NONE,
+#ifdef CONFIG_PM_OPP
+	.voltageFormula = VOLTAGE_FORMULA_OPP,
+#else
+	.voltageFormula = VOLTAGE_FORMULA_NONE,
+#endif
+	.powerFormula   = POWER_FORMULA_NONE,
+	.PCI_ids = PCI_Void_ids,
+	.Uncore = {
+		.Start = NULL,
+		.Stop = NULL,
+		.ClockMod = NULL
+		},
+	.Specific = Void_Specific,
+	.SystemDriver = VOID_Driver,
+	.Architecture = Arch_T_Head
+	},
+[Veyron] = {
+	.Signature = _Veyron,
+	.Query = Query_GenericMachine,
+	.Update = PerCore_GenericMachine,
+	.Start = Start_GenericMachine,
+	.Stop = Stop_GenericMachine,
+	.Exit = NULL,
+	.Timer = InitTimer_GenericMachine,
+	.BaseClock = BaseClock_GenericMachine,
+	.ClockMod = NULL,
+	.TurboClock = NULL,
+	.thermalFormula = THERMAL_FORMULA_NONE,
+#ifdef CONFIG_PM_OPP
+	.voltageFormula = VOLTAGE_FORMULA_OPP,
+#else
+	.voltageFormula = VOLTAGE_FORMULA_NONE,
+#endif
+	.powerFormula   = POWER_FORMULA_NONE,
+	.PCI_ids = PCI_Void_ids,
+	.Uncore = {
+		.Start = NULL,
+		.Stop = NULL,
+		.ClockMod = NULL
+		},
+	.Specific = Void_Specific,
+	.SystemDriver = VOID_Driver,
+	.Architecture = Arch_Veyron
+	},
+[SpacemiT] = {
+	.Signature = _SpacemiT,
+	.Query = Query_GenericMachine,
+	.Update = PerCore_GenericMachine,
+	.Start = Start_GenericMachine,
+	.Stop = Stop_GenericMachine,
+	.Exit = NULL,
+	.Timer = InitTimer_GenericMachine,
+	.BaseClock = BaseClock_GenericMachine,
+	.ClockMod = NULL,
+	.TurboClock = NULL,
+	.thermalFormula = THERMAL_FORMULA_NONE,
+#ifdef CONFIG_PM_OPP
+	.voltageFormula = VOLTAGE_FORMULA_OPP,
+#else
+	.voltageFormula = VOLTAGE_FORMULA_NONE,
+#endif
+	.powerFormula   = POWER_FORMULA_NONE,
+	.PCI_ids = PCI_Void_ids,
+	.Uncore = {
+		.Start = NULL,
+		.Stop = NULL,
+		.ClockMod = NULL
+		},
+	.Specific = Void_Specific,
+	.SystemDriver = VOID_Driver,
+	.Architecture = Arch_SpacemiT
+	}
 };

riscv64/coretypes.h

@@ -35,13 +35,12 @@ enum CRC_MANUFACTURER
 	CRC_HYPERV	= 0x543a585e
 };
 
-enum CODENAME
-{
-	RV64,
-	CODENAMES
-};
-
 enum {	GenuineArch = 0,
+	Andes,
+	SiFive,
+	T_Head,
+	Veyron,
+	SpacemiT,
 	ARCHITECTURES
 };
 

riscv64/risc_reg.h

@@ -53,21 +53,21 @@ typedef union
 	{
 		unsigned long long
 		WPRI0		:  1-0,
-		SIE		:  2-1, /* Enables all interrupts	*/
+		SIE		:  2-1, /* Supervisor all Interrupts Enable */
 		WPRI2		:  5-2,
-		SPIE		:  6-5,
-		UBE		:  7-6,
+		SPIE		:  6-5, /* Supervisor Prior Interrupt Enable */
+		UBE		:  7-6, /* Endianness Control. 0:Little; 1:Big*/
 		WPRI7		:  8-7,
-		SPP		:  9-8,
-		VS		: 11-9,
+		SPP		:  9-8, /* Supervisor Previous Privilege mode */
+		VS		: 11-9, /* Vector Extension State	*/
 		WPRI11		: 13-11,
-		FS		: 15-13,
-		XS		: 17-15,
+		FS		: 15-13, /* Floating-point Unit State	*/
+		XS		: 17-15, /* User-mode eXtensions State	*/
 		WPRI17		: 18-17,
-		SUM		: 19-18,
-		MXR		: 20-19,
+		SUM		: 19-18, /* Supervisor User Memory access */
+		MXR		: 20-19, /* Make eXecutable Readable	*/
 		WPRI20		: 32-20,
-		UXL		: 34-32,
+		UXL		: 34-32, /* U-mode UXLEN		*/
 		WPRI34		: 63-34,
 		SD		: 64-63;
 	};