[Intel][BDW][HSW] Query the IMC Power Down Mode

Author: cyring

corefreq-api.h

@@ -520,6 +520,7 @@ typedef struct
 	/* 4C0Ch */		HSW_DDR_RANK_TIMING_B	Rank_B; /* 32 bits    */
 	/* 4C14h */		HSW_DDR_RANK_TIMING	Rank;	/* 32 bits    */
 	/* 4E98h */		HSW_TC_REFRESH_TIMING	Refresh; /*32 bits    */
+	/* 4CB0h */		HSW_PM_POWER_DOWN	PDWN;	/* 32 bits    */
 			} HSW;
 			struct {
 	/* 4000h */		SKL_IMC_CR_TC_PRE	Timing; /* 32 bits    */

corefreqd.c

@@ -3834,9 +3834,6 @@ void HSW_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
 
 	TIMING(mc, cha).tFAW = \
 		RO(Proc)->Uncore.MC[mc].Channel[cha].HSW._.tFAW;
-
-	TIMING(mc, cha).B2B = \
-		RO(Proc)->Uncore.MC[mc].Channel[cha].HSW._.B2B;
 */
 	TIMING(mc, cha).tRP = \
 		RO(Proc)->Uncore.MC[mc].Channel[cha].HSW.REG4C00.tRP;
@@ -3906,6 +3903,21 @@ void HSW_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
 		TIMING(mc, cha).CMD_Rate = 0;
 		break;
 	}
+/*
+	TIMING(mc, cha).B2B = \
+		RO(Proc)->Uncore.MC[mc].Channel[cha].HSW._.B2B;
+
+	TIMING(mc, cha).tXS = \
+		RO(Proc)->Uncore.MC[mc].Channel[cha].HSW._.tXS;
+*/
+	TIMING(mc, cha).PDM_EN = \
+		0 != RO(Proc)->Uncore.MC[mc].Channel[cha].HSW.PDWN.PDWN_Mode;
+
+	TIMING(mc, cha).PDM_MODE = \
+		RO(Proc)->Uncore.MC[mc].Channel[cha].HSW.PDWN.PDWN_Mode;
+
+	TIMING(mc, cha).PDM_AGGR = \
+		RO(Proc)->Uncore.MC[mc].Channel[cha].HSW.PDWN.PDWN_Mode;
 
       for (slot = 0; slot < RO(Shm)->Uncore.MC[mc].SlotCount; slot++)
       {

corefreqk.c

@@ -4489,6 +4489,9 @@ void Query_HSW_IMC(void __iomem *mchmap, unsigned short mc)
 
 	PUBLIC(RO(Proc))->Uncore.MC[mc].Channel[cha].HSW.Refresh.value = \
 							readl(mchmap + 0x4e98);
+
+	PUBLIC(RO(Proc))->Uncore.MC[mc].Channel[cha].HSW.PDWN.value = \
+							readl(mchmap + 0x4cb0);
     }
 	/*		Is Dual DIMM Per Channel Disable ?		*/
 	PUBLIC(RO(Proc))->Uncore.MC[mc].SlotCount = \

intelmsr.h

@@ -3331,6 +3331,29 @@ typedef union
 	};
 } HSW_DDR_RANK_TIMING;
 
+typedef union
+{	/* Device: 0 - Function: 0 - Offset Channel0: 4CB0h		*/
+	unsigned int		value;
+	struct {
+		unsigned int
+		PDWN_Idle_Ctr 	: 12-0,  /* Power-down entrance in DCLK	*/
+		PDWN_Mode	: 16-12, /* 1:APD,2:PPD,6:DLL-OFF,3-5,7-15:RSV*/
+		ReservedBits 	: 32-16;
+	};
+} HSW_PM_POWER_DOWN;
+
+typedef union
+{	/* Device: 0 - Function: 0 - Offset Channel0: 4E94h		*/
+	unsigned int		value;
+	struct {
+		unsigned int
+		OREF_RI 	:  8-0,  /* Rank idle perriod in DCLK	*/
+		Ref_HP_WM	: 12-8,  /* 8: Refresh priority to high	*/
+		Ref_Panic_WM	: 16-12, /* 9: Refresh priority to panic */
+		ReservedBits 	: 32-16;
+	};
+} HSW_TC_REFRESH_PARAM;
+
 typedef union
 {	/* Device: 0 - Function: 0 - Offset Channel0: 4E98h		*/
 	unsigned int		value;