Design: FPU integration into the QtRvSim pipeline

[jdupak]

[ppisa]

I have interest in this but I would like to discuss it to make it reasonable to add value and not to make QtRvSim less understandable for novices. My actual preference is to finish @jiristefan BHR, BTB and BHT into clean state which would be merged into mainline. Functionality is OK from my point when BHR is corrected but code style and suggestions should be resolved.

[jdupak]

Agreed, I have opened this issue to track the discussion and possibly involve other teachers teaching with QtRvSim. The point of this issue is to decide where in pipeline do we want to place the FPU, not to actually implement it.