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net: phy: bcm7xxx: Add EPHY entry for 72165
72165 is a 16nm process SoC with a 10/100 integrated Ethernet PHY, create a new macro and set of functions for this different process type. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20210917181551.2836036-1-f.fainelli@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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‎drivers/net/phy/bcm7xxx.c‎

Lines changed: 201 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -398,6 +398,190 @@ static int bcm7xxx_28nm_ephy_config_init(struct phy_device *phydev)
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return bcm7xxx_28nm_ephy_apd_enable(phydev);
399399
}
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static int bcm7xxx_16nm_ephy_afe_config(struct phy_device *phydev)
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{
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int tmp, rcalcode, rcalnewcodelp, rcalnewcode11, rcalnewcode11d2;
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/* Reset PHY */
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tmp = genphy_soft_reset(phydev);
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if (tmp)
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return tmp;
409+
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/* Reset AFE and PLL */
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bcm_phy_write_exp_sel(phydev, 0x0003, 0x0006);
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/* Clear reset */
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bcm_phy_write_exp_sel(phydev, 0x0003, 0x0000);
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/* Write PLL/AFE control register to select 54MHz crystal */
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bcm_phy_write_misc(phydev, 0x0030, 0x0001, 0x0000);
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bcm_phy_write_misc(phydev, 0x0031, 0x0000, 0x044a);
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/* Change Ka,Kp,Ki to pdiv=1 */
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bcm_phy_write_misc(phydev, 0x0033, 0x0002, 0x71a1);
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/* Configuration override */
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bcm_phy_write_misc(phydev, 0x0033, 0x0001, 0x8000);
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/* Change PLL_NDIV and PLL_NUDGE */
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bcm_phy_write_misc(phydev, 0x0031, 0x0001, 0x2f68);
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bcm_phy_write_misc(phydev, 0x0031, 0x0002, 0x0000);
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/* Reference frequency is 54Mhz, config_mode[15:14] = 3 (low
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* phase)
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*/
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bcm_phy_write_misc(phydev, 0x0030, 0x0003, 0xc036);
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/* Initialize bypass mode */
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bcm_phy_write_misc(phydev, 0x0032, 0x0003, 0x0000);
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/* Bypass code, default: VCOCLK enabled */
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bcm_phy_write_misc(phydev, 0x0033, 0x0000, 0x0002);
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/* LDOs at default setting */
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bcm_phy_write_misc(phydev, 0x0030, 0x0002, 0x01c0);
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/* Release PLL reset */
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bcm_phy_write_misc(phydev, 0x0030, 0x0001, 0x0001);
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/* Bandgap curvature correction to correct default */
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bcm_phy_write_misc(phydev, 0x0038, 0x0000, 0x0010);
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/* Run RCAL */
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bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x0038);
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bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x003b);
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udelay(2);
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bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x003f);
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mdelay(5);
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/* AFE_CAL_CONFIG_0, Vref=1000, Target=10, averaging enabled */
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bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x1c82);
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/* AFE_CAL_CONFIG_0, no reset and analog powerup */
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bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9e82);
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udelay(2);
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/* AFE_CAL_CONFIG_0, start calibration */
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bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9f82);
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udelay(100);
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/* AFE_CAL_CONFIG_0, clear start calibration, set HiBW */
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bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9e86);
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udelay(2);
463+
/* AFE_CAL_CONFIG_0, start calibration with hi BW mode set */
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bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9f86);
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udelay(100);
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/* Adjust 10BT amplitude additional +7% and 100BT +2% */
468+
bcm_phy_write_misc(phydev, 0x0038, 0x0001, 0xe7ea);
469+
/* Adjust 1G mode amplitude and 1G testmode1 */
470+
bcm_phy_write_misc(phydev, 0x0038, 0x0002, 0xede0);
471+
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/* Read CORE_EXPA9 */
473+
tmp = bcm_phy_read_exp(phydev, 0x00a9);
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/* CORE_EXPA9[6:1] is rcalcode[5:0] */
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rcalcode = (tmp & 0x7e) / 2;
476+
/* Correct RCAL code + 1 is -1% rprogr, LP: +16 */
477+
rcalnewcodelp = rcalcode + 16;
478+
/* Correct RCAL code + 1 is -15 rprogr, 11: +10 */
479+
rcalnewcode11 = rcalcode + 10;
480+
/* Saturate if necessary */
481+
if (rcalnewcodelp > 0x3f)
482+
rcalnewcodelp = 0x3f;
483+
if (rcalnewcode11 > 0x3f)
484+
rcalnewcode11 = 0x3f;
485+
/* REXT=1 BYP=1 RCAL_st1<5:0>=new rcal code */
486+
tmp = 0x00f8 + rcalnewcodelp * 256;
487+
/* Program into AFE_CAL_CONFIG_2 */
488+
bcm_phy_write_misc(phydev, 0x0039, 0x0003, tmp);
489+
/* AFE_BIAS_CONFIG_0 10BT bias code (Bias: E4) */
490+
bcm_phy_write_misc(phydev, 0x0038, 0x0001, 0xe7e4);
491+
/* invert adc clock output and 'adc refp ldo current To correct
492+
* default
493+
*/
494+
bcm_phy_write_misc(phydev, 0x003b, 0x0000, 0x8002);
495+
/* 100BT stair case, high BW, 1G stair case, alternate encode */
496+
bcm_phy_write_misc(phydev, 0x003c, 0x0003, 0xf882);
497+
/* 1000BT DAC transition method per Erol, bits[32], DAC Shuffle
498+
* sequence 1 + 10BT imp adjust bits
499+
*/
500+
bcm_phy_write_misc(phydev, 0x003d, 0x0000, 0x3201);
501+
/* Non-overlap fix */
502+
bcm_phy_write_misc(phydev, 0x003a, 0x0002, 0x0c00);
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504+
/* pwdb override (rxconfig<5>) to turn on RX LDO indpendent of
505+
* pwdb controls from DSP_TAP10
506+
*/
507+
bcm_phy_write_misc(phydev, 0x003a, 0x0001, 0x0020);
508+
509+
/* Remove references to channel 2 and 3 */
510+
bcm_phy_write_misc(phydev, 0x003b, 0x0002, 0x0000);
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bcm_phy_write_misc(phydev, 0x003b, 0x0003, 0x0000);
512+
513+
/* Set cal_bypassb bit rxconfig<43> */
514+
bcm_phy_write_misc(phydev, 0x003a, 0x0003, 0x0800);
515+
udelay(2);
516+
517+
/* Revert pwdb_override (rxconfig<5>) to 0 so that the RX pwr
518+
* is controlled by DSP.
519+
*/
520+
bcm_phy_write_misc(phydev, 0x003a, 0x0001, 0x0000);
521+
522+
/* Drop LSB */
523+
rcalnewcode11d2 = (rcalnewcode11 & 0xfffe) / 2;
524+
tmp = bcm_phy_read_misc(phydev, 0x003d, 0x0001);
525+
/* Clear bits [11:5] */
526+
tmp &= ~0xfe0;
527+
/* set txcfg_ch0<5>=1 (enable + set local rcal) */
528+
tmp |= 0x0020 | (rcalnewcode11d2 * 64);
529+
bcm_phy_write_misc(phydev, 0x003d, 0x0001, tmp);
530+
bcm_phy_write_misc(phydev, 0x003d, 0x0002, tmp);
531+
532+
tmp = bcm_phy_read_misc(phydev, 0x003d, 0x0000);
533+
/* set txcfg<45:44>=11 (enable Rextra + invert fullscaledetect)
534+
*/
535+
tmp &= ~0x3000;
536+
tmp |= 0x3000;
537+
bcm_phy_write_misc(phydev, 0x003d, 0x0000, tmp);
538+
539+
return 0;
540+
}
541+
542+
static int bcm7xxx_16nm_ephy_config_init(struct phy_device *phydev)
543+
{
544+
int ret, val;
545+
546+
ret = bcm7xxx_16nm_ephy_afe_config(phydev);
547+
if (ret)
548+
return ret;
549+
550+
ret = bcm_phy_set_eee(phydev, true);
551+
if (ret)
552+
return ret;
553+
554+
ret = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
555+
if (ret < 0)
556+
return ret;
557+
558+
val = ret;
559+
560+
/* Auto power down of DLL enabled,
561+
* TXC/RXC disabled during auto power down.
562+
*/
563+
val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
564+
val |= BIT(8);
565+
566+
ret = bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
567+
if (ret < 0)
568+
return ret;
569+
570+
return bcm_phy_enable_apd(phydev, true);
571+
}
572+
573+
static int bcm7xxx_16nm_ephy_resume(struct phy_device *phydev)
574+
{
575+
int ret;
576+
577+
/* Re-apply workarounds coming out suspend/resume */
578+
ret = bcm7xxx_16nm_ephy_config_init(phydev);
579+
if (ret)
580+
return ret;
581+
582+
return genphy_config_aneg(phydev);
583+
}
584+
401585
static int bcm7xxx_28nm_ephy_resume(struct phy_device *phydev)
402586
{
403587
int ret;
@@ -610,9 +794,25 @@ static void bcm7xxx_28nm_remove(struct phy_device *phydev)
610794
.resume = bcm7xxx_config_init, \
611795
}
612796

797+
#define BCM7XXX_16NM_EPHY(_oui, _name) \
798+
{ \
799+
.phy_id = (_oui), \
800+
.phy_id_mask = 0xfffffff0, \
801+
.name = _name, \
802+
/* PHY_BASIC_FEATURES */ \
803+
.flags = PHY_IS_INTERNAL, \
804+
.probe = bcm7xxx_28nm_probe, \
805+
.remove = bcm7xxx_28nm_remove, \
806+
.config_init = bcm7xxx_16nm_ephy_config_init, \
807+
.config_aneg = genphy_config_aneg, \
808+
.read_status = genphy_read_status, \
809+
.resume = bcm7xxx_16nm_ephy_resume, \
810+
}
811+
613812
static struct phy_driver bcm7xxx_driver[] = {
614813
BCM7XXX_28NM_EPHY(PHY_ID_BCM72113, "Broadcom BCM72113"),
615814
BCM7XXX_28NM_EPHY(PHY_ID_BCM72116, "Broadcom BCM72116"),
815+
BCM7XXX_16NM_EPHY(PHY_ID_BCM72165, "Broadcom BCM72165"),
616816
BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
617817
BCM7XXX_28NM_EPHY(PHY_ID_BCM7255, "Broadcom BCM7255"),
618818
BCM7XXX_28NM_EPHY(PHY_ID_BCM7260, "Broadcom BCM7260"),
@@ -635,6 +835,7 @@ static struct phy_driver bcm7xxx_driver[] = {
635835
static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
636836
{ PHY_ID_BCM72113, 0xfffffff0 },
637837
{ PHY_ID_BCM72116, 0xfffffff0, },
838+
{ PHY_ID_BCM72165, 0xfffffff0, },
638839
{ PHY_ID_BCM7250, 0xfffffff0, },
639840
{ PHY_ID_BCM7255, 0xfffffff0, },
640841
{ PHY_ID_BCM7260, 0xfffffff0, },

‎include/linux/brcmphy.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@
3232

3333
#define PHY_ID_BCM72113 0x35905310
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#define PHY_ID_BCM72116 0x35905350
35+
#define PHY_ID_BCM72165 0x35905340
3536
#define PHY_ID_BCM7250 0xae025280
3637
#define PHY_ID_BCM7255 0xae025120
3738
#define PHY_ID_BCM7260 0xae025190

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