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arinc9Paolo Abeni
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dt-bindings: net: dsa: mediatek,mt7530: improve binding description
Fix inaccurate information about PHY muxing, and merge standalone and multi-chip module MT7530 configuration methods. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230212131258.47551-1-arinc.unal@arinc9.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml

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@@ -24,56 +24,46 @@ description: |
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There is only the standalone version of MT7531.
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Port 5 on MT7530 has got various ways of configuration.
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For standalone MT7530:
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Port 5 on MT7530 has got various ways of configuration:
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- Port 5 can be used as a CPU port.
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- PHY 0 or 4 of the switch can be muxed to connect to the gmac of the SoC
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which port 5 is wired to. Usually used for connecting the wan port
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directly to the CPU to achieve 2 Gbps routing in total.
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- PHY 0 or 4 of the switch can be muxed to gmac5 of the switch. Therefore,
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the gmac of the SoC which is wired to port 5 can connect to the PHY.
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This is usually used for connecting the wan port directly to the CPU to
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achieve 2 Gbps routing in total.
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The driver looks up the reg on the ethernet-phy node which the phy-handle
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property refers to on the gmac node to mux the specified phy.
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The driver looks up the reg on the ethernet-phy node, which the phy-handle
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property on the gmac node refers to, to mux the specified phy.
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The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the
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compatible string and the reg must be 1. So, for now, only gmac1 of an
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compatible string and the reg must be 1. So, for now, only gmac1 of a
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MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this.
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Check out example 5 for a similar configuration.
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- Port 5 can be wired to an external phy. Port 5 becomes a DSA slave.
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Check out example 7 for a similar configuration.
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For multi-chip module MT7530:
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- Port 5 can be used as a CPU port.
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- PHY 0 or 4 of the switch can be muxed to connect to gmac1 of the SoC.
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Usually used for connecting the wan port directly to the CPU to achieve 2
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Gbps routing in total.
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The driver looks up the reg on the ethernet-phy node which the phy-handle
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property refers to on the gmac node to mux the specified phy.
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For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function.
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Check out example 5.
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- In case of an external phy wired to gmac1 of the SoC, port 5 must not be
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enabled.
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- For the multi-chip module MT7530, in case of an external phy wired to
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gmac1 of the SoC, port 5 must not be enabled.
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In case of muxing PHY 0 or 4, the external phy must not be enabled.
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For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function.
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Check out example 6.
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- Port 5 can be muxed to an external phy. Port 5 becomes a DSA slave.
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The external phy must be wired TX to TX to gmac1 of the SoC for this to
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work. Ubiquiti EdgeRouter X SFP is wired this way.
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- Port 5 can be wired to an external phy. Port 5 becomes a DSA slave.
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For the multi-chip module MT7530, the external phy must be wired TX to TX
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to gmac1 of the SoC for this to work. Ubiquiti EdgeRouter X SFP is wired
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this way.
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Muxing PHY 0 or 4 won't work when the external phy is connected TX to TX.
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For the multi-chip module MT7530, muxing PHY 0 or 4 won't work when the
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external phy is connected TX to TX.
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For the MT7621 SoCs, rgmii2 group must be claimed with gpio function.
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Check out example 7.
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properties:
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label = "lan4";
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};
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/* Commented out, phy4 is muxed to gmac1.
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/* Commented out, phy4 is connected to gmac1.
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port@4 {
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reg = <4>;
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label = "wan";

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