@@ -117,6 +117,18 @@ enum flash_dma_reg {
117117 FLASH_DMA_CURRENT_DESC_EXT ,
118118};
119119
120+ /* flash_dma registers v0*/
121+ static const u16 flash_dma_regs_v0 [] = {
122+ [FLASH_DMA_REVISION ] = 0x00 ,
123+ [FLASH_DMA_FIRST_DESC ] = 0x04 ,
124+ [FLASH_DMA_CTRL ] = 0x08 ,
125+ [FLASH_DMA_MODE ] = 0x0c ,
126+ [FLASH_DMA_STATUS ] = 0x10 ,
127+ [FLASH_DMA_INTERRUPT_DESC ] = 0x14 ,
128+ [FLASH_DMA_ERROR_STATUS ] = 0x18 ,
129+ [FLASH_DMA_CURRENT_DESC ] = 0x1c ,
130+ };
131+
120132/* flash_dma registers v1*/
121133static const u16 flash_dma_regs_v1 [] = {
122134 [FLASH_DMA_REVISION ] = 0x00 ,
@@ -597,6 +609,8 @@ static void brcmnand_flash_dma_revision_init(struct brcmnand_controller *ctrl)
597609 /* flash_dma register offsets */
598610 if (ctrl -> nand_version >= 0x0703 )
599611 ctrl -> flash_dma_offsets = flash_dma_regs_v4 ;
612+ else if (ctrl -> nand_version == 0x0602 )
613+ ctrl -> flash_dma_offsets = flash_dma_regs_v0 ;
600614 else
601615 ctrl -> flash_dma_offsets = flash_dma_regs_v1 ;
602616}
@@ -1673,8 +1687,11 @@ static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
16731687
16741688 flash_dma_writel (ctrl , FLASH_DMA_FIRST_DESC , lower_32_bits (desc ));
16751689 (void )flash_dma_readl (ctrl , FLASH_DMA_FIRST_DESC );
1676- flash_dma_writel (ctrl , FLASH_DMA_FIRST_DESC_EXT , upper_32_bits (desc ));
1677- (void )flash_dma_readl (ctrl , FLASH_DMA_FIRST_DESC_EXT );
1690+ if (ctrl -> nand_version > 0x0602 ) {
1691+ flash_dma_writel (ctrl , FLASH_DMA_FIRST_DESC_EXT ,
1692+ upper_32_bits (desc ));
1693+ (void )flash_dma_readl (ctrl , FLASH_DMA_FIRST_DESC_EXT );
1694+ }
16781695
16791696 /* Start FLASH_DMA engine */
16801697 ctrl -> dma_pending = true;
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