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broonie
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arm64/hwcap: Describe 2024 dpISA extensions to userspace
The 2024 dpISA introduces a number of architecture features all of which only add new instructions so only require the addition of hwcaps and ID register visibility. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20250107-arm64-2024-dpisa-v5-3-7578da51fc3d@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
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‎Documentation/arch/arm64/elf_hwcaps.rst‎

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -174,6 +174,56 @@ HWCAP_GCS
174174
Functionality implied by ID_AA64PFR1_EL1.GCS == 0b1, as
175175
described by Documentation/arch/arm64/gcs.rst.
176176

177+
HWCAP_CMPBR
178+
Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0010.
179+
180+
HWCAP_FPRCVT
181+
Functionality implied by ID_AA64ISAR3_EL1.FPRCVT == 0b0001.
182+
183+
HWCAP_F8MM8
184+
Functionality implied by ID_AA64FPFR0_EL1.F8MM8 == 0b0001.
185+
186+
HWCAP_F8MM4
187+
Functionality implied by ID_AA64FPFR0_EL1.F8MM4 == 0b0001.
188+
189+
HWCAP_SVE_F16MM
190+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
191+
ID_AA64ZFR0_EL1.F16MM == 0b0001.
192+
193+
HWCAP_SVE_ELTPERM
194+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
195+
ID_AA64ZFR0_EL1.ELTPERM == 0b0001.
196+
197+
HWCAP_SVE_AES2
198+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
199+
ID_AA64ZFR0_EL1.AES == 0b0011.
200+
201+
HWCAP_SVE_BFSCALE
202+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
203+
ID_AA64ZFR0_EL1.B16B16 == 0b0010.
204+
205+
HWCAP_SVE2P2
206+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
207+
ID_AA64ZFR0_EL1.SVEver == 0b0011.
208+
209+
HWCAP_SME2P2
210+
Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0011.
211+
212+
HWCAP_SME_SBITPERM
213+
Functionality implied by ID_AA64SMFR0_EL1.SBitPerm == 0b1.
214+
215+
HWCAP_SME_AES
216+
Functionality implied by ID_AA64SMFR0_EL1.AES == 0b1.
217+
218+
HWCAP_SME_SFEXPA
219+
Functionality implied by ID_AA64SMFR0_EL1.SFEXPA == 0b1.
220+
221+
HWCAP_SME_STMOP
222+
Functionality implied by ID_AA64SMFR0_EL1.STMOP == 0b1.
223+
224+
HWCAP_SME_SMOP4
225+
Functionality implied by ID_AA64SMFR0_EL1.SMOP4 == 0b1.
226+
177227
HWCAP2_DCPODP
178228
Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010.
179229

‎arch/arm64/include/asm/hwcap.h‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -93,6 +93,21 @@
9393
#define KERNEL_HWCAP_PACA __khwcap_feature(PACA)
9494
#define KERNEL_HWCAP_PACG __khwcap_feature(PACG)
9595
#define KERNEL_HWCAP_GCS __khwcap_feature(GCS)
96+
#define KERNEL_HWCAP_CMPBR __khwcap_feature(CMPBR)
97+
#define KERNEL_HWCAP_FPRCVT __khwcap_feature(FPRCVT)
98+
#define KERNEL_HWCAP_F8MM8 __khwcap_feature(F8MM8)
99+
#define KERNEL_HWCAP_F8MM4 __khwcap_feature(F8MM4)
100+
#define KERNEL_HWCAP_SVE_F16MM __khwcap_feature(SVE_F16MM)
101+
#define KERNEL_HWCAP_SVE_ELTPERM __khwcap_feature(SVE_ELTPERM)
102+
#define KERNEL_HWCAP_SVE_AES2 __khwcap_feature(SVE_AES2)
103+
#define KERNEL_HWCAP_SVE_BFSCALE __khwcap_feature(SVE_BFSCALE)
104+
#define KERNEL_HWCAP_SVE2P2 __khwcap_feature(SVE2P2)
105+
#define KERNEL_HWCAP_SME2P2 __khwcap_feature(SME2P2)
106+
#define KERNEL_HWCAP_SME_SBITPERM __khwcap_feature(SME_SBITPERM)
107+
#define KERNEL_HWCAP_SME_AES __khwcap_feature(SME_AES)
108+
#define KERNEL_HWCAP_SME_SFEXPA __khwcap_feature(SME_SFEXPA)
109+
#define KERNEL_HWCAP_SME_STMOP __khwcap_feature(SME_STMOP)
110+
#define KERNEL_HWCAP_SME_SMOP4 __khwcap_feature(SME_SMOP4)
96111

97112
#define __khwcap2_feature(x) (const_ilog2(HWCAP2_ ## x) + 64)
98113
#define KERNEL_HWCAP_DCPODP __khwcap2_feature(DCPODP)

‎arch/arm64/include/uapi/asm/hwcap.h‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,21 @@
5656
#define HWCAP_PACA (1 << 30)
5757
#define HWCAP_PACG (1UL << 31)
5858
#define HWCAP_GCS (1UL << 32)
59+
#define HWCAP_CMPBR (1UL << 33)
60+
#define HWCAP_FPRCVT (1UL << 34)
61+
#define HWCAP_F8MM8 (1UL << 35)
62+
#define HWCAP_F8MM4 (1UL << 36)
63+
#define HWCAP_SVE_F16MM (1UL << 37)
64+
#define HWCAP_SVE_ELTPERM (1UL << 38)
65+
#define HWCAP_SVE_AES2 (1UL << 39)
66+
#define HWCAP_SVE_BFSCALE (1UL << 40)
67+
#define HWCAP_SVE2P2 (1UL << 41)
68+
#define HWCAP_SME2P2 (1UL << 42)
69+
#define HWCAP_SME_SBITPERM (1UL << 43)
70+
#define HWCAP_SME_AES (1UL << 44)
71+
#define HWCAP_SME_SFEXPA (1UL << 45)
72+
#define HWCAP_SME_STMOP (1UL << 46)
73+
#define HWCAP_SME_SMOP4 (1UL << 47)
5974

6075
/*
6176
* HWCAP2 flags - for AT_HWCAP2

‎arch/arm64/kernel/cpufeature.c‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -268,6 +268,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
268268
};
269269

270270
static const struct arm64_ftr_bits ftr_id_aa64isar3[] = {
271+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0),
271272
ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0),
272273
ARM64_FTR_END,
273274
};
@@ -317,6 +318,8 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
317318
FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0),
318319
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
319320
FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0),
321+
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
322+
FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0),
320323
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
321324
FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0),
322325
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
@@ -329,6 +332,8 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
329332
FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0),
330333
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
331334
FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0),
335+
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
336+
FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0),
332337
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
333338
FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0),
334339
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
@@ -373,6 +378,16 @@ static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = {
373378
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0),
374379
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
375380
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0),
381+
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
382+
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0),
383+
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
384+
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0),
385+
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
386+
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0),
387+
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
388+
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0),
389+
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
390+
FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0),
376391
ARM64_FTR_END,
377392
};
378393

@@ -381,6 +396,8 @@ static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = {
381396
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0),
382397
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0),
383398
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0),
399+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0),
400+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0),
384401
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0),
385402
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0),
386403
ARM64_FTR_END,
@@ -3092,19 +3109,24 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
30923109
HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT),
30933110
#ifdef CONFIG_ARM64_SVE
30943111
HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE),
3112+
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2),
30953113
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1),
30963114
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
30973115
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
30983116
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
3117+
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2),
30993118
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
31003119
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16),
3120+
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE),
31013121
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
31023122
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16),
31033123
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
31043124
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
31053125
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
31063126
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
31073127
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
3128+
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM),
3129+
HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM),
31083130
#endif
31093131
#ifdef CONFIG_ARM64_GCS
31103132
HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS),
@@ -3124,6 +3146,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
31243146
HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV),
31253147
HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP),
31263148
HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC),
3149+
HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR),
31273150
HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM),
31283151
HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES),
31293152
HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
@@ -3133,6 +3156,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
31333156
HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME),
31343157
HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
31353158
HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2),
3159+
HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2),
31363160
HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1),
31373161
HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2),
31383162
HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64),
@@ -3150,6 +3174,13 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
31503174
HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA),
31513175
HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4),
31523176
HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2),
3177+
HWCAP_CAP(ID_AA64SMFR0_EL1, SF8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8MM8),
3178+
HWCAP_CAP(ID_AA64SMFR0_EL1, SF8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8MM4),
3179+
HWCAP_CAP(ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM),
3180+
HWCAP_CAP(ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES),
3181+
HWCAP_CAP(ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA),
3182+
HWCAP_CAP(ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP),
3183+
HWCAP_CAP(ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4),
31533184
#endif /* CONFIG_ARM64_SME */
31543185
HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT),
31553186
HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA),

‎arch/arm64/kernel/cpuinfo.c‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -145,6 +145,21 @@ static const char *const hwcap_str[] = {
145145
[KERNEL_HWCAP_SME_SF8DP4] = "smesf8dp4",
146146
[KERNEL_HWCAP_SME_SF8DP2] = "smesf8dp2",
147147
[KERNEL_HWCAP_POE] = "poe",
148+
[KERNEL_HWCAP_CMPBR] = "cmpbr",
149+
[KERNEL_HWCAP_FPRCVT] = "fprcvt",
150+
[KERNEL_HWCAP_F8MM8] = "f8mm8",
151+
[KERNEL_HWCAP_F8MM4] = "f8mm4",
152+
[KERNEL_HWCAP_SVE_F16MM] = "svef16mm",
153+
[KERNEL_HWCAP_SVE_ELTPERM] = "sveeltperm",
154+
[KERNEL_HWCAP_SVE_AES2] = "sveaes2",
155+
[KERNEL_HWCAP_SVE_BFSCALE] = "svebfscale",
156+
[KERNEL_HWCAP_SVE2P2] = "sve2p2",
157+
[KERNEL_HWCAP_SME2P2] = "sme2p2",
158+
[KERNEL_HWCAP_SME_SBITPERM] = "smesbitperm",
159+
[KERNEL_HWCAP_SME_AES] = "smeaes",
160+
[KERNEL_HWCAP_SME_SFEXPA] = "smesfexpa",
161+
[KERNEL_HWCAP_SME_STMOP] = "smestmop",
162+
[KERNEL_HWCAP_SME_SMOP4] = "smesmop4",
148163
};
149164

150165
#ifdef CONFIG_COMPAT

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