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crypto: marvell - create common Kconfig and Makefile for Marvell
Creats common Kconfig and Makefile for Marvell crypto drivers. Signed-off-by: SrujanaChalla <schalla@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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10 files changed

+69
-46
lines changed

10 files changed

+69
-46
lines changed

‎drivers/crypto/Kconfig‎

Lines changed: 1 addition & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -233,20 +233,6 @@ config CRYPTO_CRC32_S390
233233

234234
It is available with IBM z13 or later.
235235

236-
config CRYPTO_DEV_MARVELL_CESA
237-
tristate "Marvell's Cryptographic Engine driver"
238-
depends on PLAT_ORION || ARCH_MVEBU
239-
select CRYPTO_LIB_AES
240-
select CRYPTO_LIB_DES
241-
select CRYPTO_SKCIPHER
242-
select CRYPTO_HASH
243-
select SRAM
244-
help
245-
This driver allows you to utilize the Cryptographic Engines and
246-
Security Accelerator (CESA) which can be found on MVEBU and ORION
247-
platforms.
248-
This driver supports CPU offload through DMA transfers.
249-
250236
config CRYPTO_DEV_NIAGARA2
251237
tristate "Niagara2 Stream Processing Unit driver"
252238
select CRYPTO_LIB_DES
@@ -606,6 +592,7 @@ config CRYPTO_DEV_MXS_DCP
606592
source "drivers/crypto/qat/Kconfig"
607593
source "drivers/crypto/cavium/cpt/Kconfig"
608594
source "drivers/crypto/cavium/nitrox/Kconfig"
595+
source "drivers/crypto/marvell/Kconfig"
609596

610597
config CRYPTO_DEV_CAVIUM_ZIP
611598
tristate "Cavium ZIP driver"

‎drivers/crypto/Makefile‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ obj-$(CONFIG_CRYPTO_DEV_GEODE) += geode-aes.o
1818
obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hifn_795x.o
1919
obj-$(CONFIG_CRYPTO_DEV_IMGTEC_HASH) += img-hash.o
2020
obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o
21-
obj-$(CONFIG_CRYPTO_DEV_MARVELL_CESA) += marvell/
21+
obj-$(CONFIG_CRYPTO_DEV_MARVELL) += marvell/
2222
obj-$(CONFIG_CRYPTO_DEV_MEDIATEK) += mediatek/
2323
obj-$(CONFIG_CRYPTO_DEV_MXS_DCP) += mxs-dcp.o
2424
obj-$(CONFIG_CRYPTO_DEV_NIAGARA2) += n2_crypto.o

‎drivers/crypto/marvell/Kconfig‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
#
2+
# Marvell crypto drivers configuration
3+
#
4+
5+
config CRYPTO_DEV_MARVELL
6+
tristate
7+
8+
config CRYPTO_DEV_MARVELL_CESA
9+
tristate "Marvell's Cryptographic Engine driver"
10+
depends on PLAT_ORION || ARCH_MVEBU
11+
select CRYPTO_LIB_AES
12+
select CRYPTO_LIB_DES
13+
select CRYPTO_SKCIPHER
14+
select CRYPTO_HASH
15+
select SRAM
16+
select CRYPTO_DEV_MARVELL
17+
help
18+
This driver allows you to utilize the Cryptographic Engines and
19+
Security Accelerator (CESA) which can be found on MVEBU and ORION
20+
platforms.
21+
This driver supports CPU offload through DMA transfers.

‎drivers/crypto/marvell/Makefile‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,3 @@
1-
# SPDX-License-Identifier: GPL-2.0-only
2-
obj-$(CONFIG_CRYPTO_DEV_MARVELL_CESA) += marvell-cesa.o
3-
marvell-cesa-objs := cesa.o cipher.o hash.o tdma.o
1+
# SPDX-License-Identifier: GPL-2.0
2+
3+
obj-$(CONFIG_CRYPTO_DEV_MARVELL_CESA) += cesa/

‎drivers/crypto/marvell/cesa/Makefile‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
# SPDX-License-Identifier: GPL-2.0-only
2+
obj-$(CONFIG_CRYPTO_DEV_MARVELL_CESA) += marvell-cesa.o
3+
marvell-cesa-objs := cesa.o cipher.o hash.o tdma.o

‎drivers/crypto/marvell/cesa.c‎ renamed to ‎drivers/crypto/marvell/cesa/cesa.c‎

File renamed without changes.

‎drivers/crypto/marvell/cesa.h‎ renamed to ‎drivers/crypto/marvell/cesa/cesa.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -436,7 +436,7 @@ struct mv_cesa_dev {
436436
* @queue: fifo of the pending crypto requests
437437
* @load: engine load counter, useful for load balancing
438438
* @chain: list of the current tdma descriptors being processed
439-
* by this engine.
439+
* by this engine.
440440
* @complete_queue: fifo of the processed requests by the engine
441441
*
442442
* Structure storing CESA engine information.
@@ -467,7 +467,7 @@ struct mv_cesa_engine {
467467
* @step: launch the crypto operation on the next chunk
468468
* @cleanup: cleanup the crypto request (release associated data)
469469
* @complete: complete the request, i.e copy result or context from sram when
470-
* needed.
470+
* needed.
471471
*/
472472
struct mv_cesa_req_ops {
473473
int (*process)(struct crypto_async_request *req, u32 status);
@@ -734,6 +734,7 @@ static inline struct mv_cesa_engine *mv_cesa_select_engine(int weight)
734734
for (i = 0; i < cesa_dev->caps->nengines; i++) {
735735
struct mv_cesa_engine *engine = cesa_dev->engines + i;
736736
u32 load = atomic_read(&engine->load);
737+
737738
if (load < min_load) {
738739
min_load = load;
739740
selected = engine;

‎drivers/crypto/marvell/cipher.c‎ renamed to ‎drivers/crypto/marvell/cesa/cipher.c‎

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -106,8 +106,8 @@ static void mv_cesa_skcipher_std_step(struct skcipher_request *req)
106106

107107
mv_cesa_set_int_mask(engine, CESA_SA_INT_ACCEL0_DONE);
108108
writel_relaxed(CESA_SA_CFG_PARA_DIS, engine->regs + CESA_SA_CFG);
109-
BUG_ON(readl(engine->regs + CESA_SA_CMD) &
110-
CESA_SA_CMD_EN_CESA_SA_ACCL0);
109+
WARN_ON(readl(engine->regs + CESA_SA_CMD) &
110+
CESA_SA_CMD_EN_CESA_SA_ACCL0);
111111
writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
112112
}
113113

@@ -178,6 +178,7 @@ static inline void mv_cesa_skcipher_prepare(struct crypto_async_request *req,
178178
{
179179
struct skcipher_request *skreq = skcipher_request_cast(req);
180180
struct mv_cesa_skcipher_req *creq = skcipher_request_ctx(skreq);
181+
181182
creq->base.engine = engine;
182183

183184
if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
@@ -336,7 +337,8 @@ static int mv_cesa_skcipher_dma_req_init(struct skcipher_request *req,
336337
do {
337338
struct mv_cesa_op_ctx *op;
338339

339-
op = mv_cesa_dma_add_op(&basereq->chain, op_templ, skip_ctx, flags);
340+
op = mv_cesa_dma_add_op(&basereq->chain, op_templ, skip_ctx,
341+
flags);
340342
if (IS_ERR(op)) {
341343
ret = PTR_ERR(op);
342344
goto err_free_tdma;
@@ -365,9 +367,10 @@ static int mv_cesa_skcipher_dma_req_init(struct skcipher_request *req,
365367
} while (mv_cesa_skcipher_req_iter_next_op(&iter));
366368

367369
/* Add output data for IV */
368-
ret = mv_cesa_dma_add_result_op(&basereq->chain, CESA_SA_CFG_SRAM_OFFSET,
369-
CESA_SA_DATA_SRAM_OFFSET,
370-
CESA_TDMA_SRC_IN_SRAM, flags);
370+
ret = mv_cesa_dma_add_result_op(&basereq->chain,
371+
CESA_SA_CFG_SRAM_OFFSET,
372+
CESA_SA_DATA_SRAM_OFFSET,
373+
CESA_TDMA_SRC_IN_SRAM, flags);
371374

372375
if (ret)
373376
goto err_free_tdma;

‎drivers/crypto/marvell/hash.c‎ renamed to ‎drivers/crypto/marvell/cesa/hash.c‎

Lines changed: 22 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -141,9 +141,11 @@ static int mv_cesa_ahash_pad_req(struct mv_cesa_ahash_req *creq, u8 *buf)
141141

142142
if (creq->algo_le) {
143143
__le64 bits = cpu_to_le64(creq->len << 3);
144+
144145
memcpy(buf + padlen, &bits, sizeof(bits));
145146
} else {
146147
__be64 bits = cpu_to_be64(creq->len << 3);
148+
147149
memcpy(buf + padlen, &bits, sizeof(bits));
148150
}
149151

@@ -168,7 +170,8 @@ static void mv_cesa_ahash_std_step(struct ahash_request *req)
168170
if (!sreq->offset) {
169171
digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(req));
170172
for (i = 0; i < digsize / 4; i++)
171-
writel_relaxed(creq->state[i], engine->regs + CESA_IVDIG(i));
173+
writel_relaxed(creq->state[i],
174+
engine->regs + CESA_IVDIG(i));
172175
}
173176

174177
if (creq->cache_ptr)
@@ -245,8 +248,8 @@ static void mv_cesa_ahash_std_step(struct ahash_request *req)
245248

246249
mv_cesa_set_int_mask(engine, CESA_SA_INT_ACCEL0_DONE);
247250
writel_relaxed(CESA_SA_CFG_PARA_DIS, engine->regs + CESA_SA_CFG);
248-
BUG_ON(readl(engine->regs + CESA_SA_CMD) &
249-
CESA_SA_CMD_EN_CESA_SA_ACCL0);
251+
WARN_ON(readl(engine->regs + CESA_SA_CMD) &
252+
CESA_SA_CMD_EN_CESA_SA_ACCL0);
250253
writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
251254
}
252255

@@ -329,11 +332,12 @@ static void mv_cesa_ahash_complete(struct crypto_async_request *req)
329332
digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq));
330333

331334
if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ &&
332-
(creq->base.chain.last->flags & CESA_TDMA_TYPE_MSK) == CESA_TDMA_RESULT) {
335+
(creq->base.chain.last->flags & CESA_TDMA_TYPE_MSK) ==
336+
CESA_TDMA_RESULT) {
333337
__le32 *data = NULL;
334338

335339
/*
336-
* Result is already in the correct endianess when the SA is
340+
* Result is already in the correct endianness when the SA is
337341
* used
338342
*/
339343
data = creq->base.chain.last->op->ctx.hash.hash;
@@ -347,9 +351,9 @@ static void mv_cesa_ahash_complete(struct crypto_async_request *req)
347351
CESA_IVDIG(i));
348352
if (creq->last_req) {
349353
/*
350-
* Hardware's MD5 digest is in little endian format, but
351-
* SHA in big endian format
352-
*/
354+
* Hardware's MD5 digest is in little endian format, but
355+
* SHA in big endian format
356+
*/
353357
if (creq->algo_le) {
354358
__le32 *result = (void *)ahashreq->result;
355359

@@ -439,7 +443,8 @@ static bool mv_cesa_ahash_cache_req(struct ahash_request *req)
439443
struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
440444
bool cached = false;
441445

442-
if (creq->cache_ptr + req->nbytes < CESA_MAX_HASH_BLOCK_SIZE && !creq->last_req) {
446+
if (creq->cache_ptr + req->nbytes < CESA_MAX_HASH_BLOCK_SIZE &&
447+
!creq->last_req) {
443448
cached = true;
444449

445450
if (!req->nbytes)
@@ -648,7 +653,8 @@ static int mv_cesa_ahash_dma_req_init(struct ahash_request *req)
648653
if (!mv_cesa_ahash_req_iter_next_op(&iter))
649654
break;
650655

651-
op = mv_cesa_dma_add_frag(&basereq->chain, &creq->op_tmpl,
656+
op = mv_cesa_dma_add_frag(&basereq->chain,
657+
&creq->op_tmpl,
652658
frag_len, flags);
653659
if (IS_ERR(op)) {
654660
ret = PTR_ERR(op);
@@ -920,7 +926,7 @@ struct ahash_alg mv_md5_alg = {
920926
.cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
921927
.cra_init = mv_cesa_ahash_cra_init,
922928
.cra_module = THIS_MODULE,
923-
}
929+
}
924930
}
925931
};
926932

@@ -990,7 +996,7 @@ struct ahash_alg mv_sha1_alg = {
990996
.cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
991997
.cra_init = mv_cesa_ahash_cra_init,
992998
.cra_module = THIS_MODULE,
993-
}
999+
}
9941000
}
9951001
};
9961002

@@ -1063,7 +1069,7 @@ struct ahash_alg mv_sha256_alg = {
10631069
.cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
10641070
.cra_init = mv_cesa_ahash_cra_init,
10651071
.cra_module = THIS_MODULE,
1066-
}
1072+
}
10671073
}
10681074
};
10691075

@@ -1297,7 +1303,7 @@ struct ahash_alg mv_ahmac_md5_alg = {
12971303
.cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
12981304
.cra_init = mv_cesa_ahmac_cra_init,
12991305
.cra_module = THIS_MODULE,
1300-
}
1306+
}
13011307
}
13021308
};
13031309

@@ -1367,7 +1373,7 @@ struct ahash_alg mv_ahmac_sha1_alg = {
13671373
.cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
13681374
.cra_init = mv_cesa_ahmac_cra_init,
13691375
.cra_module = THIS_MODULE,
1370-
}
1376+
}
13711377
}
13721378
};
13731379

@@ -1437,6 +1443,6 @@ struct ahash_alg mv_ahmac_sha256_alg = {
14371443
.cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
14381444
.cra_init = mv_cesa_ahmac_cra_init,
14391445
.cra_module = THIS_MODULE,
1440-
}
1446+
}
14411447
}
14421448
};

‎drivers/crypto/marvell/tdma.c‎ renamed to ‎drivers/crypto/marvell/cesa/tdma.c‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -50,8 +50,8 @@ void mv_cesa_dma_step(struct mv_cesa_req *dreq)
5050
engine->regs + CESA_SA_CFG);
5151
writel_relaxed(dreq->chain.first->cur_dma,
5252
engine->regs + CESA_TDMA_NEXT_ADDR);
53-
BUG_ON(readl(engine->regs + CESA_SA_CMD) &
54-
CESA_SA_CMD_EN_CESA_SA_ACCL0);
53+
WARN_ON(readl(engine->regs + CESA_SA_CMD) &
54+
CESA_SA_CMD_EN_CESA_SA_ACCL0);
5555
writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
5656
}
5757

@@ -175,8 +175,10 @@ int mv_cesa_tdma_process(struct mv_cesa_engine *engine, u32 status)
175175
break;
176176
}
177177

178-
/* Save the last request in error to engine->req, so that the core
179-
* knows which request was fautly */
178+
/*
179+
* Save the last request in error to engine->req, so that the core
180+
* knows which request was fautly
181+
*/
180182
if (res) {
181183
spin_lock_bh(&engine->lock);
182184
engine->req = req;

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