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19 | 19 | #ifndef __ARCH_ARM_DAVINCI_SPI_H |
20 | 20 | #define __ARCH_ARM_DAVINCI_SPI_H |
21 | 21 |
|
| 22 | +#define SPI_INTERN_CS 0xFF |
| 23 | + |
22 | 24 | enum { |
23 | 25 | SPI_VERSION_1, /* For DM355/DM365/DM6467 */ |
24 | 26 | SPI_VERSION_2, /* For DA8xx */ |
25 | 27 | }; |
26 | 28 |
|
| 29 | +/** |
| 30 | + * davinci_spi_platform_data - Platform data for SPI master device on DaVinci |
| 31 | + * |
| 32 | + * @version: version of the SPI IP. Different DaVinci devices have slightly |
| 33 | + * varying versions of the same IP. |
| 34 | + * @num_chipselect: number of chipselects supported by this SPI master |
| 35 | + * @intr_line: interrupt line used to connect the SPI IP to the ARM interrupt |
| 36 | + * controller withn the SoC. Possible values are 0 and 1. |
| 37 | + * @chip_sel: list of GPIOs which can act as chip-selects for the SPI. |
| 38 | + * SPI_INTERN_CS denotes internal SPI chip-select. Not necessary |
| 39 | + * to populate if all chip-selects are internal. |
| 40 | + * @cshold_bug: set this to true if the SPI controller on your chip requires |
| 41 | + * a write to CSHOLD bit in between transfers (like in DM355). |
| 42 | + */ |
27 | 43 | struct davinci_spi_platform_data { |
28 | 44 | u8 version; |
29 | 45 | u8 num_chipselect; |
| 46 | + u8 intr_line; |
| 47 | + u8 *chip_sel; |
| 48 | + bool cshold_bug; |
| 49 | +}; |
| 50 | + |
| 51 | +/** |
| 52 | + * davinci_spi_config - Per-chip-select configuration for SPI slave devices |
| 53 | + * |
| 54 | + * @wdelay: amount of delay between transmissions. Measured in number of |
| 55 | + * SPI module clocks. |
| 56 | + * @odd_parity: polarity of parity flag at the end of transmit data stream. |
| 57 | + * 0 - odd parity, 1 - even parity. |
| 58 | + * @parity_enable: enable transmission of parity at end of each transmit |
| 59 | + * data stream. |
| 60 | + * @io_type: type of IO transfer. Choose between polled, interrupt and DMA. |
| 61 | + * @timer_disable: disable chip-select timers (setup and hold) |
| 62 | + * @c2tdelay: chip-select setup time. Measured in number of SPI module clocks. |
| 63 | + * @t2cdelay: chip-select hold time. Measured in number of SPI module clocks. |
| 64 | + * @t2edelay: transmit data finished to SPI ENAn pin inactive time. Measured |
| 65 | + * in number of SPI clocks. |
| 66 | + * @c2edelay: chip-select active to SPI ENAn signal active time. Measured in |
| 67 | + * number of SPI clocks. |
| 68 | + */ |
| 69 | +struct davinci_spi_config { |
30 | 70 | u8 wdelay; |
31 | 71 | u8 odd_parity; |
32 | 72 | u8 parity_enable; |
33 | | - u8 wait_enable; |
| 73 | +#define SPI_IO_TYPE_INTR 0 |
| 74 | +#define SPI_IO_TYPE_POLL 1 |
| 75 | +#define SPI_IO_TYPE_DMA 2 |
| 76 | + u8 io_type; |
34 | 77 | u8 timer_disable; |
35 | | - u8 clk_internal; |
36 | | - u8 cs_hold; |
37 | | - u8 intr_level; |
38 | | - u8 poll_mode; |
39 | | - u8 use_dma; |
40 | 78 | u8 c2tdelay; |
41 | 79 | u8 t2cdelay; |
| 80 | + u8 t2edelay; |
| 81 | + u8 c2edelay; |
42 | 82 | }; |
43 | 83 |
|
44 | 84 | #endif /* __ARCH_ARM_DAVINCI_SPI_H */ |
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