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Wrong register decoding in execute_op16_special_data_branch #1

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Ko- opened this issue Jun 28, 2019 · 0 comments · May be fixed by #2
Open

Wrong register decoding in execute_op16_special_data_branch #1

Ko- opened this issue Jun 28, 2019 · 0 comments · May be fixed by #2

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@Ko-
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Ko- commented Jun 28, 2019

Hi! I was trying this simulator and I noticed that I had an instruction mov r12, ... that somehow was writing to r8 according to the simulator. That shouldn't happen, of course. I checked the architecture reference manual and it seems like there's an off-by-one in the decoding of the following instructions:

  • ADD with register, encoding T2
  • CMP with register, encoding T2
  • MOV with register, encoding T1

I'll submit a PR that fixes this.

@Ko- Ko- linked a pull request Jun 28, 2019 that will close this issue
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