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Hi! I was trying this simulator and I noticed that I had an instruction mov r12, ... that somehow was writing to r8 according to the simulator. That shouldn't happen, of course. I checked the architecture reference manual and it seems like there's an off-by-one in the decoding of the following instructions:
ADD with register, encoding T2
CMP with register, encoding T2
MOV with register, encoding T1
I'll submit a PR that fixes this.
The text was updated successfully, but these errors were encountered:
Ko-
linked a pull request
Jun 28, 2019
that will
close
this issue
Hi! I was trying this simulator and I noticed that I had an instruction
mov r12, ...
that somehow was writing tor8
according to the simulator. That shouldn't happen, of course. I checked the architecture reference manual and it seems like there's an off-by-one in the decoding of the following instructions:ADD
with register, encoding T2CMP
with register, encoding T2MOV
with register, encoding T1I'll submit a PR that fixes this.
The text was updated successfully, but these errors were encountered: