2024-03-16_BJX2_DynCfgBlock0.txt

Possible/Idea:
* Part of the F3 block will be left as Dynamic Config Blocks.
** Say, F3-8..F3-F
* These blocks may be configured with a REQDCB instruction.
** This instruction will specify an immediate for the requested block.
** Along with encoding which block to configure.

Which instructions exist within each DCB may be updated at runtime, likely within function prologs.

Say:
* REQDCB 0x12345678, R8
Would request that F3-8 be configured with whatever extension corresponds to this magic number. This instruction may take a certain number of cycles to take effect.

After this instruction takes effect, instructions of the form:
* F3nm-8eoZ
Will be decoded according to the active configuration for that block.

The idea is that any magic number may be loaded into any of the DCBs, though some extensions may require multiple DCBs.


The processor may store its DCB state in the DCB0 and DCB1 registers.
* Using F3-8 .. F8-B will require preserving DCB0.
* Using F3-C .. F8-F will require preserving DCB1.
* These registers will be treated as callee-save in the ABI.
* The contents of these registers will be implementation defined.

Note that following an update to the DCB regisrers, there may be an indeterminite delay before the new blocks take effect.