Issue in generating the VHDL for the processor using Processor Generator (ProGe)

[Jedrek09]

Hello. I was having a problem in generating the VHDL for the processor using Processor Generator (ProGe). I did the selection of implementations for register files, immediate units, and function units. Due to the selection window not being very informative about the different implementations, I opted for automatic selection instead.I also enabled bus tracing from the Implementation-dialog's IC / Decoder Plugin tab and clicked "Save IDF" and named the file custom.idf. I then clicked "Generate Processor," created a directory named proge-output, and attempted to generate the processor. I encountered an issue during generating the VHDL for the processor using Processor Generator (ProGe). However, the dialogue box disappeared, and the terminal displayed an error. I also tried the alternate method using terminal commands, but I encountered errors there as well. Could you please guide me on how to resolve this issue?

[karihepola]

Hi,

Could you please paste the error you get when calling

generate_processor -i custom.idf -o proge-output custom.adf

in the terminal?

Thanks

[Jedrek09]

This is the error I get after running generateprocessor -t -i custom.idf -o proge-output custom.adf

FU entry 1 does not have an implementation in HDB /home/salman/openasip-devel/openasip/tce_tutorials/tce_tour/tour.hdb.
Segmentation fault (core dumped)

[karihepola]

Did you double-check that the entry in the HDB is as described in the tutorial? Were you able to add the implementation of the function unit successfully? Additionally, the IDF is an XML file that you can open with a text editor of your choice to inspect it. Does it point to a valid function unit entry in the HDB?

[Jedrek09]

Yes I rechecked the entry in the HDB as described in the tutorial. For the function unit implementation I used the automatic selection and was successful. After opening the IDF file in text editor I saw it points to a valid function unit entry in the HDB but is still showing error

[pjaaskel]

Can you send the files for us to test?

[Jedrek09]

custom.idf.txt

Here is the custom.idf file in a text editor. Please let me know if you need anything else

[karihepola]

Could you also add the adf and hdb?

[Jedrek09]

custom.adf.txt
tour.hdb.txt

Here are the required file you asked for.

[karihepola]

Sorry for the delay.

I cannot open the hdb file as it seems to be somehow corrupted. Can you add it as a zip without adding any extra extensions (.txt) to the file name.

Thanks

[Jedrek09]

custom.adf.zip
custom.idf.zip
tour.hdb.zip

Here are the required files you asked for.

[karihepola]

Still cannot open it. Are you able to open the hdb file with hdbeditor or an sqlite tool such sqlitebrowser?

[Jedrek09]

Yes by installing hbdeditor and sqlitebrowser through terminal command I was able to open the hdb file and view it

[karihepola]

I think the file is formatted as text (due to the .txt extension) at some point, which corrupts it. Can you upload the original file in the original format and check that it works by downloading it yourself after uploading it to github?

Thanks

[Jedrek09]

test file.zip

Kindly check if you can open the files now.

[karihepola]

Thanks, now it works.

If you inspect the idf, you can see that the reflecter function unit is mapped to fu entry 2 in the tour hdb, but the function entry 2 does not have any implementation defined in the hdb. I think you have accidentally added two empty definitions for this function unit in the hdb, which is causing issues. If you modify the idf by hand to reference fu entry 3, it will work, since that fu entry has an implementation defined. It will first give you an error though about missing load port definition, but it should work once you add that in the hdb by navigating (as in the tour instructions):

Function units -> reflect32(1) reflect8(1) -> Modify -> t1data p1... -> Load port