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coverify

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  1. euvm euvm Public

    Embedded UVM (D Language port of IEEE UVM 1.0)

    D 31 14

  2. axi4reg axi4reg Public

    AXI4 VIP for Reg Verifiation

    SystemVerilog 4 6

  3. riscv-dv riscv-dv Public

    Forked from chipsalliance/riscv-dv

    Random instruction generator for RISC-V processor verification

    D 2 8

  4. ibex ibex Public

    Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    SystemVerilog 1 1

  5. PeakRDL-euvm PeakRDL-euvm Public

    Euvm plugin for SystemRDL's PeakRDL tool.

    Python 1 3

  6. riscv-opcodes riscv-opcodes Public

    Forked from riscv/riscv-opcodes

    RISC-V Opcodes

    Python 1

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