PicoRV32 - A Size-Optimized RISC-V CPU

Verilog Ethernet components for FPGA implementation

RTL, Cmodel, and testbench for NVDLA

The RIFFA development repository

RISC-V Formal Verification Framework

Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated

ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

Hardware, Linux Driver and Library for the Zynq AXI DMA interface

ASIC Design kit for Skywater 130 for use with mflowgen