Verilator open-source SystemVerilog simulator and lint system

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

The root repo for lowRISC project and FPGA demos.

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

Clarvi simple RISC-V processor for teaching

Open SoC Debug Hardware Reference Implementation

NASTI slave compliant DDRx memory controller.