From afe77acb68944b84256aa472756436ab22aa1932 Mon Sep 17 00:00:00 2001 From: Sungkeun Kim Date: Thu, 18 Jul 2024 11:20:33 +0900 Subject: [PATCH] Fix for compilation error in PhysicallFilter I think this module is not tested during Chisel version is updated. I fixed compiler error by chiselTypeOf --- src/main/scala/devices/tilelink/PhysicalFilter.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/devices/tilelink/PhysicalFilter.scala b/src/main/scala/devices/tilelink/PhysicalFilter.scala index 1c52bffca83..575848a0890 100644 --- a/src/main/scala/devices/tilelink/PhysicalFilter.scala +++ b/src/main/scala/devices/tilelink/PhysicalFilter.scala @@ -235,7 +235,7 @@ class PhysicalFilter(params: PhysicalFilterParams)(implicit p: Parameters) exten // Frame an appropriate deny message val denyValid = RegInit(false.B) - val deny = Reg(in.d.bits) + val deny = Reg(chiselTypeOf(in.d.bits)) val d_opcode = TLMessages.adResponse(in.a.bits.opcode) val d_grant = edgeIn.manager.anySupportAcquireB.B && deny.opcode === TLMessages.Grant when (in.a.valid && !allow && deny_ready && a_first) { @@ -257,7 +257,7 @@ class PhysicalFilter(params: PhysicalFilterParams)(implicit p: Parameters) exten } } - val out_d = Wire(in.d.bits) + val out_d = Wire(chiselTypeOf(in.d.bits)) out_d := out.d.bits // Deny can have unconditional priority, because the only out.d message possible is