From 86bb656108ba5f169d116a04814d029474eccb2e Mon Sep 17 00:00:00 2001
From: Jiuyang Liu <liu@jiuyang.me>
Date: Thu, 13 Jul 2023 17:46:59 +0800
Subject: [PATCH] migrate to new BundleMap API

---
 src/main/scala/amba/axis/Bundles.scala       |  5 +---
 src/main/scala/amba/package.scala            | 29 ++++++++------------
 src/main/scala/tilelink/RegisterRouter.scala | 11 +++-----
 src/main/scala/tilelink/ToAXI4.scala         | 11 +++-----
 4 files changed, 21 insertions(+), 35 deletions(-)

diff --git a/src/main/scala/amba/axis/Bundles.scala b/src/main/scala/amba/axis/Bundles.scala
index be107726cab..c8a7832d8e2 100644
--- a/src/main/scala/amba/axis/Bundles.scala
+++ b/src/main/scala/amba/axis/Bundles.scala
@@ -18,10 +18,7 @@ case class AXISIdField  (width: Int) extends SimpleBundleField(AXISId)  (Output(
 case class AXISDestField(width: Int) extends SimpleBundleField(AXISDest)(Output(UInt(width.W)), 0.U)
 case class AXISKeepField(width: Int) extends SimpleBundleField(AXISKeep)(Output(UInt(width.W)), ~0.U(width.W))
 case class AXISStrbField(width: Int) extends SimpleBundleField(AXISStrb)(Output(UInt(width.W)), ~0.U(width.W))
-case class AXISDataField(width: Int) extends BundleField(AXISData) {
-  def data = Output(UInt(width.W))
-  def default(x: UInt): Unit = { x := DontCare }
-}
+case class AXISDataField(width: Int) extends BundleField[UInt](AXISData, Output(UInt(width.W)), _ := DontCare)
 
 class AXISBundleBits(val params: AXISBundleParameters) extends BundleMap(AXISBundle.keys(params)) {
   def last = if (params.hasLast) apply(AXISLast) else true.B
diff --git a/src/main/scala/amba/package.scala b/src/main/scala/amba/package.scala
index 11c9f5e1cea..2af015abd9b 100644
--- a/src/main/scala/amba/package.scala
+++ b/src/main/scala/amba/package.scala
@@ -17,23 +17,18 @@ package object amba {
   }
 
   case object AMBAProt extends ControlKey[AMBAProtBundle]("amba_prot")
-  case class AMBAProtField() extends BundleField(AMBAProt) {
-    def data = Output(new AMBAProtBundle)
-    def default(x: AMBAProtBundle): Unit = {
-      x.bufferable := false.B
-      x.modifiable := false.B
-      x.readalloc  := false.B
-      x.writealloc := false.B
-      x.privileged := true.B
-      x.secure     := true.B
-      x.fetch      := false.B
-    }
-  }
+
+  case class AMBAProtField() extends BundleField[AMBAProtBundle](AMBAProt, Output(new AMBAProtBundle), x => {
+    x.bufferable := false.B
+    x.modifiable := false.B
+    x.readalloc  := false.B
+    x.writealloc := false.B
+    x.privileged := true.B
+    x.secure     := true.B
+    x.fetch      := false.B
+  })
 
   // Used to convert a TileLink corrupt signal into an AMBA user bit
   case object AMBACorrupt extends DataKey[Bool]("corrupt")
-  case class AMBACorruptField() extends BundleField(AMBACorrupt) {
-    def data = Output(Bool())
-    def default(x: Bool): Unit = { x := false.B }
-  }
-}
+  case class AMBACorruptField() extends BundleField[Bool](AMBACorrupt, Output(Bool()), x => x := false.B)
+}
\ No newline at end of file
diff --git a/src/main/scala/tilelink/RegisterRouter.scala b/src/main/scala/tilelink/RegisterRouter.scala
index 76b6f6ad7dc..5a76cce107e 100644
--- a/src/main/scala/tilelink/RegisterRouter.scala
+++ b/src/main/scala/tilelink/RegisterRouter.scala
@@ -18,13 +18,10 @@ class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extend
 }
 
 case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra")
-case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField(TLRegisterRouterExtra) {
-  def data = Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits))
-  def default(x: TLRegisterRouterExtraBundle) = {
-    x.size   := 0.U
-    x.source := 0.U
-  }
-}
+case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => {
+  x.size   := 0.U
+  x.source := 0.U
+})
 
 /** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers.
   * It provides functionality for describing and outputting metdata about the registers in several formats.
diff --git a/src/main/scala/tilelink/ToAXI4.scala b/src/main/scala/tilelink/ToAXI4.scala
index 92cc088516d..2c8ab84bb31 100644
--- a/src/main/scala/tilelink/ToAXI4.scala
+++ b/src/main/scala/tilelink/ToAXI4.scala
@@ -16,13 +16,10 @@ class AXI4TLStateBundle(val sourceBits: Int) extends Bundle {
 }
 
 case object AXI4TLState extends ControlKey[AXI4TLStateBundle]("tl_state")
-case class AXI4TLStateField(sourceBits: Int) extends BundleField(AXI4TLState) {
-  def data = Output(new AXI4TLStateBundle(sourceBits))
-  def default(x: AXI4TLStateBundle) = {
-    x.size   := 0.U
-    x.source := 0.U
-  }
-}
+case class AXI4TLStateField(sourceBits: Int) extends BundleField[AXI4TLStateBundle](AXI4TLState, Output(new AXI4TLStateBundle(sourceBits)), x => {
+  x.size := 0.U
+  x.source := 0.U
+})
 
 /** TLtoAXI4IdMap serves as a record for the translation performed between id spaces.
   *