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Currently, we have three tester interfaces:
- Circuit ("synthesizable") tester, the only tester included in chisel3 (everything else lives in a separate repo). The testdriver, like the DUT, is synthesizable hardware and is written in Chisel.
- Peek-poke tester, where Scala drives the device-under-test through peek, poke, and check commands. Obviously non-synthesizable, since it's possible to peek values, do some compute in Scala-land, and poke the results back.
- Advanced tester, like the peek-poke tester, but provides parallel actions with a limited amount of interfaces (like Decoupled).
Of course, all these testers have their problems and advantages (some fundamental, some engineering):
- Neither peek-poke nor advanced tester are available in the chisel3 repository. You have to include a separate dependency. Minor usability nit, though I think many like Python's approach of "batteries included".
- Circuit tester is great for lightweight or concurrent tests, but sequencing events in time usually requires the test writer to manually write a state machine. Not fun.
- Circuit tester is synthesizable, meaning that full testbenches can be deployed on FPGA (and generally are self-contained). Apparently some people actually do this.
- Circuit tester doesn't support any backends other than Verilator, and Verilator has a high compilation cost. The chisel3 standard tests usually take several minutes to run, probably a good percentage of that time is compiling design through Verilator.
- It's difficult to specify concurrency (see Better tester concurrency specifications? #547) in the peek-poke tester, and advanced tester only allows limited concurrency models. The circuit tester has concurrency native from its circuit nature.
The goal here is to unify all the different testers into a single tester included in Chisel3.
Reasoning:
- support all the different backends (mainly for performance reasons: chisel3 tests may run faster through the FIRRterpreter)
- unify the test specification model (which may be a hybrid approach, as detailed below)
- include it in base chisel3 (tests aren't optional for engineers serious about hardware design).
Some hybrid approaches have been suggested:
- If synthesizability isn't useful, then it's possible to write the circuit tester programming model in the peek-poke tester framework. Only the step command needs to be added to the peek-poke tester.
- It is also possible to translate series of step, check, and pokes to synthesizable hardware, having Chisel generate the state machine. There would be no poke support, since the testbench would be standalone and not have a Scala testdriver.
- Several attempts have been made before with systems like these, for whatever reason they have never gained traction.
- This may make testvector literal specification a non-issue, since all test constructs live in Chisel-land and can seamlessly use Chisel literals and future features like Bundle literals.
@jackkoenig @jackbackrack @sdtwigg @dt27182 @chick @azidar @aswaterman
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