diff --git a/include/Surelog/ErrorReporting/ErrorDefinition.h b/include/Surelog/ErrorReporting/ErrorDefinition.h index 8ea1bb0c28..8a07c3f183 100644 --- a/include/Surelog/ErrorReporting/ErrorDefinition.h +++ b/include/Surelog/ErrorReporting/ErrorDefinition.h @@ -237,7 +237,7 @@ class ErrorDefinition { ELAB_USE_INTERFACE_AS_SIGNAL_TYPE = 538, ELAB_UNKNOWN_STRUCT_MEMBER = 539, ELAB_UNKNOWN_INTERFACE_MEMBER = 540, - ELAB_UNKNOWN_PARAMETER = 541, + ELAB_UNKNOWN_PARAMETER_COMMAND = 541, ELAB_EXPRESSION_LOOP = 542, ELAB_SKIPPING_BLACKBOX_MODULE = 543, ELAB_SKIPPING_BLACKBOX_INSTANCE = 544, @@ -248,6 +248,7 @@ class ErrorDefinition { ELAB_SYSTEM_INFO = 549, ELAB_UNKNOWN_PORT = 550, ELAB_TOP_PARAMETER_NO_DEFAULT = 551, + ELAB_UNKNOWN_PARAMETER_OVERRIDE = 552, LIB_FILE_MAPS_TO_MULTIPLE_LIBS = 600, UHDM_UNSUPPORTED_EXPR = 700, UHDM_UNSUPPORTED_STMT = 701, diff --git a/src/DesignCompile/DesignElaboration.cpp b/src/DesignCompile/DesignElaboration.cpp index d4f79f85eb..176273d91b 100644 --- a/src/DesignCompile/DesignElaboration.cpp +++ b/src/DesignCompile/DesignElaboration.cpp @@ -2023,6 +2023,18 @@ std::vector DesignElaboration::collectParams_( // Named param const std::string_view name = parentFile->SymName(child); overridenParams.insert(name); + if (module) { + Parameter* p = module->getParameter(name); + if (p == nullptr) { + Location loc(parentFile->getFileId(paramAssign), + parentFile->Line(paramAssign), + parentFile->Column(paramAssign), + st->registerSymbol(name)); + Error err(ErrorDefinition::ELAB_UNKNOWN_PARAMETER_OVERRIDE, loc); + errors->addError(err); + continue; + } + } NodeId expr = parentFile->Sibling(child); if (!expr) { Location loc( @@ -2523,7 +2535,7 @@ void DesignElaboration::checkElaboration_() { Location loc( m_compileDesign->getCompiler()->getSymbolTable()->registerSymbol( name)); - Error err(ErrorDefinition::ELAB_UNKNOWN_PARAMETER, loc); + Error err(ErrorDefinition::ELAB_UNKNOWN_PARAMETER_COMMAND, loc); m_compileDesign->getCompiler()->getErrorContainer()->addError(err); } } diff --git a/src/ErrorReporting/ErrorDefinition.cpp b/src/ErrorReporting/ErrorDefinition.cpp index 6f74a49fcd..54777d2412 100644 --- a/src/ErrorReporting/ErrorDefinition.cpp +++ b/src/ErrorReporting/ErrorDefinition.cpp @@ -419,7 +419,9 @@ bool ErrorDefinition::init() { rec(ELAB_UNKNOWN_INTERFACE_MEMBER, ERROR, ELAB, "Unknown interface member \"%s\"", "%exloc interface definition for \"%exobj\""); - rec(ELAB_UNKNOWN_PARAMETER, ERROR, ELAB, + rec(ELAB_UNKNOWN_PARAMETER_OVERRIDE, ERROR, ELAB, + "Unknown parameter override \"%s\""); + rec(ELAB_UNKNOWN_PARAMETER_COMMAND, ERROR, ELAB, "Unknown parameter in command line override \"%s\""); rec(ELAB_EXPRESSION_LOOP, ERROR, ELAB, "Expression loop in instance \"%s\""); rec(ELAB_SKIPPING_BLACKBOX_MODULE, INFO, ELAB, diff --git a/tests/BlackParrotMuteErrors/BlackParrotMuteErrors.log b/tests/BlackParrotMuteErrors/BlackParrotMuteErrors.log index 8a8cf2fa33..778395efd4 100644 --- a/tests/BlackParrotMuteErrors/BlackParrotMuteErrors.log +++ b/tests/BlackParrotMuteErrors/BlackParrotMuteErrors.log @@ -6601,6 +6601,7 @@ AST_DEBUG_END [INF:CP0335] ${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv:884:38: Compile generate block "work@otp_ctrl.gen_partitions[5].gen_buffered". [INF:CP0335] ${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv:882:39: Compile generate block "work@otp_ctrl.gen_partitions[6]". [NTE:EL0503] ${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv:877:1: Top level module "work@otp_ctrl". +[ERR:EL0552] ${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv:887:9: Unknown parameter override "DataDefault". [NTE:EL0508] Nb Top level modules: 1. [NTE:EL0509] Max instance depth: 4. [NTE:EL0510] Nb instances: 5. @@ -6610,11 +6611,11 @@ AST_DEBUG_END array_typespec 77 assignment 11 begin 4 -bit_select 24 +bit_select 16 class_defn 8 class_typespec 4 class_var 3 -constant 12728 +constant 12704 design 1 enum_const 231 enum_typespec 51 @@ -6626,9 +6627,8 @@ gen_for 1 gen_if 1 gen_scope 22 gen_scope_array 22 -hier_path 26 +hier_path 18 import_typespec 14 -indexed_part_select 4 int_typespec 3977 int_var 6 integer_typespec 30 @@ -6639,15 +6639,15 @@ logic_typespec 2833 logic_var 27 module_inst 46 named_begin 2 -operation 656 +operation 648 package 10 packed_array_typespec 36 param_assign 3583 parameter 4817 range 2801 ref_module 5 -ref_obj 270 -ref_typespec 10706 +ref_obj 262 +ref_typespec 10698 ref_var 3 return_stmt 8 string_typespec 1104 @@ -6663,11 +6663,11 @@ unsupported_typespec 378 array_typespec 77 assignment 19 begin 8 -bit_select 28 +bit_select 20 class_defn 8 class_typespec 4 class_var 3 -constant 12728 +constant 12704 design 1 enum_const 236 enum_typespec 52 @@ -6679,9 +6679,8 @@ gen_for 1 gen_if 1 gen_scope 33 gen_scope_array 33 -hier_path 34 +hier_path 26 import_typespec 14 -indexed_part_select 4 int_typespec 3977 int_var 6 integer_typespec 30 @@ -6692,15 +6691,15 @@ logic_typespec 2833 logic_var 27 module_inst 50 named_begin 2 -operation 758 +operation 750 package 10 packed_array_typespec 36 param_assign 4547 parameter 4817 range 2817 ref_module 5 -ref_obj 344 -ref_typespec 12725 +ref_obj 336 +ref_typespec 12717 ref_var 5 return_stmt 29 string_typespec 1104 @@ -122424,7 +122423,7 @@ design: (work@otp_ctrl) |vpiPattern: \_constant: , line:821:19, endln:821:27 |vpiParent: - \_operation: , line:887:37, endln:887:57 + \_tagged_pattern: , line:821:19, endln:821:27 |vpiDecompile:11'd1536 |vpiSize:11 |DEC:1536 @@ -122443,7 +122442,7 @@ design: (work@otp_ctrl) |vpiPattern: \_constant: , line:822:19, endln:822:22 |vpiParent: - \_operation: , line:887:61, endln:887:79 + \_tagged_pattern: , line:822:19, endln:822:22 |vpiDecompile:208 |vpiSize:64 |UINT:208 @@ -122587,7 +122586,7 @@ design: (work@otp_ctrl) |vpiPattern: \_constant: , line:832:19, endln:832:27 |vpiParent: - \_operation: , line:887:37, endln:887:57 + \_tagged_pattern: , line:832:19, endln:832:27 |vpiDecompile:11'd1744 |vpiSize:11 |DEC:1744 @@ -122606,7 +122605,7 @@ design: (work@otp_ctrl) |vpiPattern: \_constant: , line:833:19, endln:833:21 |vpiParent: - \_operation: , line:887:61, endln:887:79 + \_tagged_pattern: , line:833:19, endln:833:21 |vpiDecompile:40 |vpiSize:64 |UINT:40 @@ -122751,7 +122750,7 @@ design: (work@otp_ctrl) |vpiPattern: \_constant: , line:843:19, endln:843:27 |vpiParent: - \_operation: , line:887:37, endln:887:57 + \_tagged_pattern: , line:843:19, endln:843:27 |vpiDecompile:11'd1784 |vpiSize:11 |DEC:1784 @@ -122770,7 +122769,7 @@ design: (work@otp_ctrl) |vpiPattern: \_constant: , line:844:19, endln:844:21 |vpiParent: - \_operation: , line:887:61, endln:887:79 + \_tagged_pattern: , line:844:19, endln:844:21 |vpiDecompile:88 |vpiSize:64 |UINT:88 @@ -122915,7 +122914,7 @@ design: (work@otp_ctrl) |vpiPattern: \_constant: , line:854:19, endln:854:27 |vpiParent: - \_operation: , line:887:37, endln:887:57 + \_tagged_pattern: , line:854:19, endln:854:27 |vpiDecompile:11'd1872 |vpiSize:11 |DEC:1872 @@ -122934,7 +122933,7 @@ design: (work@otp_ctrl) |vpiPattern: \_constant: , line:855:19, endln:855:22 |vpiParent: - \_operation: , line:887:61, endln:887:79 + \_tagged_pattern: , line:855:19, endln:855:22 |vpiDecompile:120 |vpiSize:64 |UINT:120 @@ -232144,51 +232143,6 @@ design: (work@otp_ctrl) |vpiSize:64 |UINT:0 |vpiConstType:9 -\_operation: , line:887:37, endln:887:57 - |vpiParent: - \_indexed_part_select: PartInvDefault (PartInvDefault), line:887:37, endln:887:79 - |vpiOpType:25 - |vpiOperand: - \_constant: , line:821:19, endln:821:27 - |vpiOperand: - \_constant: , line:887:56, endln:887:57 - |vpiParent: - \_operation: , line:887:37, endln:887:57 - |vpiDecompile:8 - |vpiSize:64 - |UINT:8 - |vpiConstType:9 -\_indexed_part_select: PartInvDefault (PartInvDefault), line:887:37, endln:887:79 - |vpiName:PartInvDefault - |vpiDefName:PartInvDefault - |vpiConstantSelect:1 - |vpiIndexedPartSelectType:1 - |vpiBaseExpr: - \_constant: , line:887:37, endln:887:55 - |vpiDecompile:12288 - |vpiSize:64 - |INT:12288 - |vpiConstType:7 - |vpiWidthExpr: - \_constant: , line:887:61, endln:887:77 - |vpiDecompile:1664 - |vpiSize:64 - |INT:1664 - |vpiConstType:7 -\_operation: , line:887:61, endln:887:79 - |vpiParent: - \_indexed_part_select: PartInvDefault (PartInvDefault), line:887:37, endln:887:79 - |vpiOpType:25 - |vpiOperand: - \_constant: , line:822:19, endln:822:22 - |vpiOperand: - \_constant: , line:887:78, endln:887:79 - |vpiParent: - \_operation: , line:887:61, endln:887:79 - |vpiDecompile:8 - |vpiSize:64 - |UINT:8 - |vpiConstType:9 \_operation: , line:786:33, endln:786:77 |vpiParent: \_param_assign: , line:786:18, endln:786:77 @@ -235581,51 +235535,6 @@ design: (work@otp_ctrl) |vpiSize:64 |UINT:0 |vpiConstType:9 -\_operation: , line:887:37, endln:887:57 - |vpiParent: - \_indexed_part_select: PartInvDefault (PartInvDefault), line:887:37, endln:887:79 - |vpiOpType:25 - |vpiOperand: - \_constant: , line:832:19, endln:832:27 - |vpiOperand: - \_constant: , line:887:56, endln:887:57 - |vpiParent: - \_operation: , line:887:37, endln:887:57 - |vpiDecompile:8 - |vpiSize:64 - |UINT:8 - |vpiConstType:9 -\_indexed_part_select: PartInvDefault (PartInvDefault), line:887:37, endln:887:79 - |vpiName:PartInvDefault - |vpiDefName:PartInvDefault - |vpiConstantSelect:1 - |vpiIndexedPartSelectType:1 - |vpiBaseExpr: - \_constant: , line:887:37, endln:887:55 - |vpiDecompile:13952 - |vpiSize:64 - |INT:13952 - |vpiConstType:7 - |vpiWidthExpr: - \_constant: , line:887:61, endln:887:77 - |vpiDecompile:320 - |vpiSize:64 - |INT:320 - |vpiConstType:7 -\_operation: , line:887:61, endln:887:79 - |vpiParent: - \_indexed_part_select: PartInvDefault (PartInvDefault), line:887:37, endln:887:79 - |vpiOpType:25 - |vpiOperand: - \_constant: , line:833:19, endln:833:21 - |vpiOperand: - \_constant: , line:887:78, endln:887:79 - |vpiParent: - \_operation: , line:887:61, endln:887:79 - |vpiDecompile:8 - |vpiSize:64 - |UINT:8 - |vpiConstType:9 \_operation: , line:786:33, endln:786:77 |vpiParent: \_param_assign: , line:786:18, endln:786:77 @@ -239018,51 +238927,6 @@ design: (work@otp_ctrl) |vpiSize:64 |UINT:0 |vpiConstType:9 -\_operation: , line:887:37, endln:887:57 - |vpiParent: - \_indexed_part_select: PartInvDefault (PartInvDefault), line:887:37, endln:887:79 - |vpiOpType:25 - |vpiOperand: - \_constant: , line:843:19, endln:843:27 - |vpiOperand: - \_constant: , line:887:56, endln:887:57 - |vpiParent: - \_operation: , line:887:37, endln:887:57 - |vpiDecompile:8 - |vpiSize:64 - |UINT:8 - |vpiConstType:9 -\_indexed_part_select: PartInvDefault (PartInvDefault), line:887:37, endln:887:79 - |vpiName:PartInvDefault - |vpiDefName:PartInvDefault - |vpiConstantSelect:1 - |vpiIndexedPartSelectType:1 - |vpiBaseExpr: - \_constant: , line:887:37, endln:887:55 - |vpiDecompile:14272 - |vpiSize:64 - |INT:14272 - |vpiConstType:7 - |vpiWidthExpr: - \_constant: , line:887:61, endln:887:77 - |vpiDecompile:704 - |vpiSize:64 - |INT:704 - |vpiConstType:7 -\_operation: , line:887:61, endln:887:79 - |vpiParent: - \_indexed_part_select: PartInvDefault (PartInvDefault), line:887:37, endln:887:79 - |vpiOpType:25 - |vpiOperand: - \_constant: , line:844:19, endln:844:21 - |vpiOperand: - \_constant: , line:887:78, endln:887:79 - |vpiParent: - \_operation: , line:887:61, endln:887:79 - |vpiDecompile:8 - |vpiSize:64 - |UINT:8 - |vpiConstType:9 \_operation: , line:786:33, endln:786:77 |vpiParent: \_param_assign: , line:786:18, endln:786:77 @@ -242455,51 +242319,6 @@ design: (work@otp_ctrl) |vpiSize:64 |UINT:0 |vpiConstType:9 -\_operation: , line:887:37, endln:887:57 - |vpiParent: - \_indexed_part_select: PartInvDefault (PartInvDefault), line:887:37, endln:887:79 - |vpiOpType:25 - |vpiOperand: - \_constant: , line:854:19, endln:854:27 - |vpiOperand: - \_constant: , line:887:56, endln:887:57 - |vpiParent: - \_operation: , line:887:37, endln:887:57 - |vpiDecompile:8 - |vpiSize:64 - |UINT:8 - |vpiConstType:9 -\_indexed_part_select: PartInvDefault (PartInvDefault), line:887:37, endln:887:79 - |vpiName:PartInvDefault - |vpiDefName:PartInvDefault - |vpiConstantSelect:1 - |vpiIndexedPartSelectType:1 - |vpiBaseExpr: - \_constant: , line:887:37, endln:887:55 - |vpiDecompile:14976 - |vpiSize:64 - |INT:14976 - |vpiConstType:7 - |vpiWidthExpr: - \_constant: , line:887:61, endln:887:77 - |vpiDecompile:960 - |vpiSize:64 - |INT:960 - |vpiConstType:7 -\_operation: , line:887:61, endln:887:79 - |vpiParent: - \_indexed_part_select: PartInvDefault (PartInvDefault), line:887:37, endln:887:79 - |vpiOpType:25 - |vpiOperand: - \_constant: , line:855:19, endln:855:22 - |vpiOperand: - \_constant: , line:887:78, endln:887:79 - |vpiParent: - \_operation: , line:887:61, endln:887:79 - |vpiDecompile:8 - |vpiSize:64 - |UINT:8 - |vpiConstType:9 \_operation: , line:786:33, endln:786:77 |vpiParent: \_param_assign: , line:786:18, endln:786:77 @@ -274447,7 +274266,7 @@ design: (work@otp_ctrl) =================== [ FATAL] : 0 [ SYNTAX] : 0 -[ ERROR] : 0 +[ ERROR] : 1 [WARNING] : 6 [ NOTE] : 5 diff --git a/tests/UhdmCoverage/UhdmCoverage.log b/tests/UhdmCoverage/UhdmCoverage.log index f26ed1e1f2..35fb872c87 100644 --- a/tests/UhdmCoverage/UhdmCoverage.log +++ b/tests/UhdmCoverage/UhdmCoverage.log @@ -900,7 +900,7 @@ AST_DEBUG_END [NTE:EL0504] Multiple top level modules in design. [WRN:EL0500] ${SURELOG_DIR}/tests/UhdmCoverage/dut.sv:27:9: Cannot find a module definition for "work@divSqrtRecFNToRaw_small.threeronew::M". [WRN:EL0500] ${SURELOG_DIR}/tests/UhdmCoverage/dut.sv:75:1: Cannot find a module definition for "work@a::U1". -[NTE:EL0537] ${SURELOG_DIR}/tests/UhdmCoverage/dut.sv:107:10: Empty parameter override for p. +[ERR:EL0552] ${SURELOG_DIR}/tests/UhdmCoverage/dut.sv:107:10: Unknown parameter override "p". [NTE:EL0508] Nb Top level modules: 8. [NTE:EL0509] Max instance depth: 3. [NTE:EL0510] Nb instances: 12. @@ -3563,6 +3563,6 @@ design: (work@divSqrtRecFNToRaw_small) =================== [ FATAL] : 0 [ SYNTAX] : 0 -[ ERROR] : 0 +[ ERROR] : 1 [WARNING] : 14 -[ NOTE] : 15 +[ NOTE] : 14 diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index f1702aa3c1..8a134efc61 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -64,20 +64,20 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; -- Configuring done -- Generating done -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess -[ 6%] Generating 15_exu.sv -[ 12%] Generating 14_mem_lib.sv +[ 6%] Generating 10_lsu_bus_intf.sv +[ 12%] Generating 11_ifu_bp_ctl.sv [ 18%] Generating 12_beh_lib.sv [ 25%] Generating 13_ifu_mem_ctl.sv -[ 31%] Generating 1_lsu_stbuf.sv -[ 37%] Generating 11_ifu_bp_ctl.sv +[ 31%] Generating 14_mem_lib.sv +[ 37%] Generating 15_exu.sv [ 43%] Generating 16_dec_decode_ctl.sv -[ 50%] Generating 10_lsu_bus_intf.sv -[ 56%] Generating 2_ahb_to_axi4.sv -[ 62%] Generating 3_rvjtag_tap.sv +[ 50%] Generating 2_ahb_to_axi4.sv +[ 62%] Generating 1_lsu_stbuf.sv [ 68%] Generating 4_dec_tlu_ctl.sv +[ 56%] Generating 3_rvjtag_tap.sv [ 75%] Generating 5_lsu_bus_buffer.sv +[ 81%] Generating 6_dbg.sv [ 87%] Generating 7_axi4_to_ahb.sv -[ 87%] Generating 6_dbg.sv [ 93%] Generating 8_ifu_aln_ctl.sv [100%] Generating 9_tb_top.sv [100%] Built target Parse diff --git a/third_party/tests/xgate/Xgate.log b/third_party/tests/xgate/Xgate.log index db44e5fc36..42fc9daab8 100644 --- a/third_party/tests/xgate/Xgate.log +++ b/third_party/tests/xgate/Xgate.log @@ -39,7 +39,7 @@ [INF:CP0303] ${SURELOG_DIR}/third_party/tests/xgate/cells_sim.v:217:1: Compile module "work@LUT4". [INF:CP0303] ${SURELOG_DIR}/third_party/tests/xgate/cells_sim.v:232:1: Compile module "work@LUT5". [INF:CP0303] ${SURELOG_DIR}/third_party/tests/xgate/cells_sim.v:252:1: Compile module "work@LUT6". -[INF:CP0303] ${SURELOG_DIR}/third_party/tests/xgate/gnl_4_8_7_2.0_gnl_8000_08_7_80_80.v:16:1: Compile module "work@LUT6_2". +[INF:CP0303] ${SURELOG_DIR}/third_party/tests/xgate/cells_sim.v:271:1: Compile module "work@LUT6_2". [INF:CP0303] ${SURELOG_DIR}/third_party/tests/xgate/cells_sim.v:2462:1: Compile module "work@MULT18X18". [INF:CP0303] ${SURELOG_DIR}/third_party/tests/xgate/cells_sim.v:2474:1: Compile module "work@MULT18X18S". [INF:CP0303] ${SURELOG_DIR}/third_party/tests/xgate/cells_sim.v:2494:1: Compile module "work@MULT18X18SIO". @@ -99,7 +99,7 @@ [INF:CP0303] ${SURELOG_DIR}/third_party/tests/xgate/cells_sim.v:2386:1: Compile module "work@SRLC32E". [INF:CP0303] ${SURELOG_DIR}/third_party/tests/xgate/cells_sim.v:24:1: Compile module "work@VCC". [INF:CP0303] ${SURELOG_DIR}/third_party/tests/xgate/cells_sim.v:362:1: Compile module "work@XORCY". -[INF:CP0303] ${SURELOG_DIR}/third_party/tests/xgate/gnl_4_8_7_2.0_gnl_8000_08_7_80_80.v:66:1: Compile module "work@gnl_8000_08_7_80_80". +[INF:CP0303] ${SURELOG_DIR}/third_party/tests/xgate/gnl_4_8_7_2.0_gnl_8000_08_7_80_80.v:17:1: Compile module "work@gnl_8000_08_7_80_80". [INF:CP0302] Compile class "work@mailbox". [INF:CP0302] Compile class "work@process". [INF:CP0302] Compile class "work@semaphore". @@ -135,6 +135,8 @@ there are 1 more instances of this message. [NTE:CP0309] ${SURELOG_DIR}/third_party/tests/xgate/cells_sim.v:218:20: Implicit port type (wire) for "O". [NTE:CP0309] ${SURELOG_DIR}/third_party/tests/xgate/cells_sim.v:233:20: Implicit port type (wire) for "O". [NTE:CP0309] ${SURELOG_DIR}/third_party/tests/xgate/cells_sim.v:253:20: Implicit port type (wire) for "O". +[NTE:CP0309] ${SURELOG_DIR}/third_party/tests/xgate/cells_sim.v:271:22: Implicit port type (wire) for "O6", +there are 1 more instances of this message. [NTE:CP0309] ${SURELOG_DIR}/third_party/tests/xgate/cells_sim.v:2465:26: Implicit port type (wire) for "P". [NTE:CP0309] ${SURELOG_DIR}/third_party/tests/xgate/cells_sim.v:2497:26: Implicit port type (wire) for "P", there are 1 more instances of this message. @@ -2737,25 +2739,25 @@ there are 1 more instances of this message. [INF:CP0335] ${SURELOG_DIR}/third_party/tests/xgate/cells_sim.v:489:11: Compile generate block "work@gnl_8000_08_7_80_80.FD_ppn.genblk1". [INF:CP0335] ${SURELOG_DIR}/third_party/tests/xgate/cells_sim.v:489:11: Compile generate block "work@gnl_8000_08_7_80_80.FD_ppo.genblk1". [INF:CP0335] ${SURELOG_DIR}/third_party/tests/xgate/cells_sim.v:489:11: Compile generate block "work@gnl_8000_08_7_80_80.FD_ppp.genblk1". -[NTE:EL0503] ${SURELOG_DIR}/third_party/tests/xgate/gnl_4_8_7_2.0_gnl_8000_08_7_80_80.v:66:1: Top level module "work@gnl_8000_08_7_80_80". +[NTE:EL0503] ${SURELOG_DIR}/third_party/tests/xgate/gnl_4_8_7_2.0_gnl_8000_08_7_80_80.v:17:1: Top level module "work@gnl_8000_08_7_80_80". [NTE:EL0508] Nb Top level modules: 1. -[NTE:EL0509] Max instance depth: 3. -[NTE:EL0510] Nb instances: 11473. -[NTE:EL0511] Nb leaf instances: 8557. +[NTE:EL0509] Max instance depth: 2. +[NTE:EL0510] Nb instances: 10681. +[NTE:EL0511] Nb leaf instances: 8161. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === always 2621 assignment 5419 -attribute 26994 +attribute 26992 begin 170 -bit_select 21645 +bit_select 21649 case_item 84 case_stmt 13 class_defn 8 class_typespec 4 class_var 3 -constant 582146 -cont_assign 67764 +constant 580189 +cont_assign 67766 design 1 enum_const 5 enum_typespec 1 @@ -2772,24 +2774,24 @@ if_else 2588 if_stmt 2632 indexed_part_select 33 initial 32 -int_typespec 24122 +int_typespec 23727 int_var 4 integer_typespec 61 io_decl 11 -logic_net 143659 -logic_typespec 146960 +logic_net 138520 +logic_typespec 139841 logic_var 1 -module_inst 23048 -operation 85597 +module_inst 21464 +operation 85599 package 2 -param_assign 19436 -parameter 19436 +param_assign 19041 +parameter 19041 part_select 118339 -port 120161 -range 112699 -ref_module 10683 -ref_obj 270886 -ref_typespec 257992 +port 115000 +range 112313 +ref_module 10681 +ref_obj 260573 +ref_typespec 246915 string_typespec 300 sys_func_call 23 task 9 @@ -2799,16 +2801,16 @@ unsupported_typespec 160 === UHDM Object Stats Begin (Elaborated Model) === always 5140 assignment 12976 -attribute 37909 +attribute 37115 begin 170 -bit_select 40712 +bit_select 40716 case_item 84 case_stmt 13 class_defn 8 class_typespec 4 class_var 3 -constant 582146 -cont_assign 105895 +constant 580189 +cont_assign 105897 design 1 enum_const 10 enum_typespec 2 @@ -2825,24 +2827,24 @@ if_else 5107 if_stmt 5151 indexed_part_select 33 initial 2551 -int_typespec 24122 +int_typespec 23727 int_var 4 integer_typespec 61 io_decl 22 -logic_net 143659 -logic_typespec 146960 +logic_net 138520 +logic_typespec 139841 logic_var 1 -module_inst 23048 -operation 133643 +module_inst 21464 +operation 133645 package 2 -param_assign 19436 -parameter 19436 +param_assign 19041 +parameter 19041 part_select 177487 -port 182773 -range 112699 -ref_module 10683 -ref_obj 460664 -ref_typespec 320609 +port 172464 +range 112313 +ref_module 10681 +ref_obj 440055 +ref_typespec 304384 string_typespec 300 sys_func_call 23 task 18 @@ -2853,7 +2855,7 @@ unsupported_typespec 160 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 -[ NOTE] : 87 +[ NOTE] : 88 ============================== Begin Linting Results ============================== [LINT]: :0:0: Unsupported typespec, diff --git a/third_party/tests/xgate/gnl_4_8_7_2.0_gnl_8000_08_7_80_80.v b/third_party/tests/xgate/gnl_4_8_7_2.0_gnl_8000_08_7_80_80.v index 70d78187c9..67126be98b 100644 --- a/third_party/tests/xgate/gnl_4_8_7_2.0_gnl_8000_08_7_80_80.v +++ b/third_party/tests/xgate/gnl_4_8_7_2.0_gnl_8000_08_7_80_80.v @@ -13,55 +13,6 @@ // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps -module LUT6_2 - (O5, - O6, - I0, - I1, - I2, - I3, - I4, - I5); - output O5; - output O6; - input I0; - input I1; - input I2; - input I3; - input I4; - input I5; - - wire I0; - wire I1; - wire I2; - wire I3; - wire I4; - wire I5; - wire O5; - wire O6; - - (* HLUTNM = "LUT6_2" *) - LUT5 #( - .INIT(32'h00000000)) - LUT5 - (.I0(I0), - .I1(I1), - .I2(I2), - .I3(I3), - .I4(I4), - .O(O5)); - (* HLUTNM = "LUT6_2" *) - LUT6 #( - .INIT(64'h0000000000000000)) - LUT6 - (.I0(I0), - .I1(I1), - .I2(I2), - .I3(I3), - .I4(I4), - .I5(I5), - .O(O6)); -endmodule (* ECO_CHECKSUM = "bf1951fa" *) (* STRUCTURAL_NETLIST = "yes" *)