Skip to content

Commit 1e48881

Browse files
tlivelychencha3
authored andcommitted
[WebAssembly] Select BUILD_VECTOR with large unsigned lane values (llvm#85880)
Previously we expected lane constants to be in the range of signed values for each lane size, but the included test case produced large unsigned values that fall outside that range. Allow instruction selection to proceed in this case rather than failing. Fixes llvm#63817.
1 parent 8926019 commit 1e48881

File tree

2 files changed

+19
-2
lines changed

2 files changed

+19
-2
lines changed

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -46,10 +46,12 @@ defm "" : ARGUMENT<V128, v2i64>;
4646
defm "" : ARGUMENT<V128, v4f32>;
4747
defm "" : ARGUMENT<V128, v2f64>;
4848

49-
// Constrained immediate argument types
49+
// Constrained immediate argument types. Allow any value from the minimum signed
50+
// value to the maximum unsigned value for the lane size.
5051
foreach SIZE = [8, 16] in
5152
def ImmI#SIZE : ImmLeaf<i32,
52-
"return -(1 << ("#SIZE#" - 1)) <= Imm && Imm < (1 << ("#SIZE#" - 1));"
53+
// -2^(n-1) <= Imm < 2^n
54+
"return -(1 << ("#SIZE#" - 1)) <= Imm && Imm < (1 << "#SIZE#");"
5355
>;
5456
foreach SIZE = [2, 4, 8, 16, 32] in
5557
def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc < %s -mtriple=wasm32 -mattr=+simd128 | FileCheck %s
3+
4+
;; Regression test for a bug in which BUILD_VECTOR nodes with large unsigned
5+
;; lane constants were not properly selected.
6+
define <4 x i8> @test(<4 x i8> %0) {
7+
; CHECK-LABEL: test:
8+
; CHECK: .functype test (v128) -> (v128)
9+
; CHECK-NEXT: # %bb.0:
10+
; CHECK-NEXT: v128.const 255, 17, 255, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
11+
; CHECK-NEXT: # fallthrough-return
12+
%V1 = or <4 x i8> <i8 255, i8 255, i8 255, i8 255>, %0
13+
%V2 = insertelement <4 x i8> %V1, i8 17, i32 1
14+
ret <4 x i8> %V2
15+
}

0 commit comments

Comments
 (0)