Added ReverseVector combinational module

Author: Konstantin Pavlov

README.md

@@ -5,31 +5,31 @@
 
 ### CONTENTS:
 
-**/Advanced Synthesis Cookbook/**		- useful code from Altera's cookbook  
-**/KCPSM6_Release9_30Sept14/**		- Xilinx's Picoblaze soft processor  
-**/pacoblaze-2.2/**		- version of Picoblaze adapted for Altera devices  
-
-**Main_tb.v**		- basic testbench template  
-
-**ActionBurst**		- multichannel one-shot triggering module  
-**ActionBurst2**		- multichannel one-shot triggering with variable steps module  
-**ClkDivider**		- wide reference clock divider  
-**DeBounce**		- two-cycle debounce for input buttons  
-**DynDelay**		- dynamic delay for arbitrary input signal made on general-purpose trigger elements  
-**EdgeDetect**		- edge detector, gives one-tick pulses on every signal edge  
-**Encoder**		- digital encoder input logic module  
-**fifo**   - single-clock FIFO buffer (queue) implementation  
-**NDivide**		- primitive integer divider  
-**lifo**   - single-clock LIFO buffer (stack) implementation  
-**PulseGen**		- generates pulses with given width and delay  
-**ResetSet**		- SR trigger variant w/o metastable state, set dominates here  
-**SetReset**		- SR trigger variant w/o metastable state, reset dominates here  
-**StaticDelay**		- static delay for arbitrary input signal made on Xilinx`s SRL16E primitives. Also serves as input synchronizer, a standard way to get rid of metastability issues  
-
-**UartRx**		- straightforward yet simple UART receiver implementation for FPGA written in Verilog  
-**UartTx**		- straightforward yet simple UART transmitter implementation for FPGA written in Verilog  
-**UartRxExtreme**		- extreme minimal UART receiver implementation for FPGA written in Verilog  
-**UartTxExtreme**		- extreme minimal UART transmitter implementation for FPGA written in Verilog  
+**/Advanced Synthesis Cookbook/**   - useful code from Altera's cookbook
+**/KCPSM6_Release9_30Sept14/**    - Xilinx's Picoblaze soft processor
+**/pacoblaze-2.2/**   - version of Picoblaze adapted for Altera devices
+
+**Main_tb.v**   - basic testbench template
+
+**ActionBurst**   - multichannel one-shot triggering module
+**ActionBurst2**    - multichannel one-shot triggering with variable steps module
+**ClkDivider**    - wide reference clock divider
+**DeBounce**    - two-cycle debounce for input buttons
+**DynDelay**    - dynamic delay for arbitrary input signal made on general-purpose trigger elements
+**EdgeDetect**    - edge detector, gives one-tick pulses on every signal edge
+**Encoder**   - digital encoder input logic module
+**fifo**    - single-clock FIFO buffer (queue) implementation
+**NDivide**   - primitive integer divider
+**lifo**   - single-clock LIFO buffer (stack) implementation
+**PulseGen**    - generates pulses with given width and delay
+**ResetSet**    - SR trigger variant w/o metastable state, set dominates here
+**ReverseVector**    - reverses signal order within multi-bit bus
+**SetReset**    - SR trigger variant w/o metastable state, reset dominates here
+**StaticDelay**   - static delay for arbitrary input signal made on Xilinx`s SRL16E primitives. Also serves as input synchronizer, a standard way to get rid of metastability issues
+**UartRx**    - straightforward yet simple UART receiver implementation for FPGA written in Verilog
+**UartTx**    - straightforward yet simple UART transmitter implementation for FPGA written in Verilog
+**UartRxExtreme**   - extreme minimal UART receiver implementation for FPGA written in Verilog
+**UartTxExtreme**   - extreme minimal UART transmitter implementation for FPGA written in Verilog
 
 Also added some simple testbenches for selected modules
 

ReverseVector.sv

@@ -0,0 +1,53 @@
+//------------------------------------------------------------------------------
+// ReverseVector.sv
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+//  "Physically" reverses signal order within multi-bit bus
+//  Thus in[7] signal becomes out[0], in[6] becomes out[1] and vise-versa
+//  Module is being synthesized into combinational logic only
+
+
+/* --- INSTANTIATION TEMPLATE BEGIN ---
+
+ReverseVector #(
+  .WIDTH( 8 )         // WIDTH must be >=2
+) RV1 (
+  .in( smth[7:0] ),
+  .out( htms[7:0] )   // reversed bit order
+);
+
+--- INSTANTIATION TEMPLATE END ---*/
+
+
+module ReverseVector #(
+  WIDTH = 8         // WIDTH must be >=2
+)(
+  input [(WIDTH-1):0] in,
+  output logic [(WIDTH-1):0] out
+);
+
+
+genvar i;
+
+generate
+  for (i = 0; i < (WIDTH/2) ; i++) begin
+    always_comb begin
+      out[i] = in[WIDTH-1-i];
+      out[WIDTH-1-i] = in[i];
+    end // always_comb
+  end // for
+endgenerate
+
+// additional assign needed when WIDTH is odd
+generate
+  if ( WIDTH%2 ) begin
+    always_comb begin
+      out[WIDTH/2] = in[WIDTH/2];
+    end // always_comb
+  end // for
+endgenerate
+
+
+endmodule

ReverseVector_tb.sv

@@ -0,0 +1,105 @@
+//------------------------------------------------------------------------------
+// ReverseVector_tb.sv
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+// testbench for ReverseVector module
+
+
+`timescale 1ns / 1ps
+
+module main_tb();
+
+logic clk200;
+initial begin
+  #0 clk200 = 1;
+  forever
+    #2.5 clk200 = ~clk200;
+end
+
+logic rst;
+initial begin
+  #10.2 rst = 1;
+  #5 rst = 0;
+  //#10000;
+  forever begin
+    #9985 rst = ~rst;
+    #5 rst = ~rst;
+  end
+end
+
+logic nrst;
+assign nrst = ~rst;
+
+logic rst_once;
+initial begin       // initializing non-X data before PLL starts
+  #10.2 rst_once = 1;
+  #5 rst_once = 0;
+end
+initial begin
+  #510.2 rst_once = 1;    // PLL starts at 500ns, clock appears, so doing the reset for modules
+  #5 rst_once = 0;
+end
+
+logic nrst_once;
+assign nrst_once = ~rst_once;
+
+logic [31:0] DerivedClocks;
+ClkDivider #(
+  .WIDTH( 32 )
+) CD1 (
+  .clk( clk200 ),
+  .nrst( nrst_once ),
+  .out( DerivedClocks[31:0] )
+);
+
+logic [31:0] E_DerivedClocks;
+EdgeDetect #(
+  .WIDTH( 32 )
+) ED1 (
+  .clk( clk200 ),
+  .nrst( nrst_once ),
+  .in( DerivedClocks[31:0] ),
+  .rising( E_DerivedClocks[31:0] ),
+  .falling(  ),
+  .both(  )
+);
+
+logic [15:0] RandomNumber1;
+c_rand RNG1 (
+  .clk( clk200 ),
+  .rst( rst_once ),
+  .reseed( 1'b0 ),
+  .seed_val( DerivedClocks[31:0] ),
+  .out( RandomNumber1[15:0] )
+);
+
+logic start;
+initial begin
+  #0 start = 1'b0;
+  #100.2 start = 1'b1;
+  #5 start = 1'b0;
+end
+
+// Module under test ==========================================================
+
+// odd width
+logic [14:0] reversed1;
+ReverseVector #(
+  .WIDTH( 15 )         // WIDTH must be >=2
+) RV1 (
+  .in( RandomNumber1[14:0] ),
+  .out( reversed1[14:0] )   // reversed bit order
+);
+
+// even width
+logic [13:0] reversed2;
+ReverseVector #(
+  .WIDTH( 14 )         // WIDTH must be >=2
+) RV2 (
+  .in( reversed1[13:0] ),
+  .out( reversed2[13:0] )   // reversed bit order
+);
+
+endmodule