Added altera cookbook

Author: pConst

Advanced Synthesis Cookbook/arbitration/arbiter.v

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+// Copyright 2007 Altera Corporation. All rights reserved.  
+// Altera products are protected under numerous U.S. and foreign patents, 
+// maskwork rights, copyrights and other intellectual property laws.  
+//
+// This reference design file, and your use thereof, is subject to and governed
+// by the terms and conditions of the applicable Altera Reference Design 
+// License Agreement (either as signed by you or found at www.altera.com).  By
+// using this reference design file, you indicate your acceptance of such terms
+// and conditions between you and Altera Corporation.  In the event that you do
+// not agree with such terms and conditions, you may not use the reference 
+// design file and please promptly destroy any copies you have made.
+//
+// This reference design file is being provided on an "as-is" basis and as an 
+// accommodation and therefore all warranties, representations or guarantees of 
+// any kind (whether express, implied or statutory) including, without 
+// limitation, warranties of merchantability, non-infringement, or fitness for
+// a particular purpose, are specifically disclaimed.  By making this reference
+// design file available, Altera expressly does not recommend, suggest or 
+// require that this reference design file be used in combination with any 
+// other product not provided by Altera.
+/////////////////////////////////////////////////////////////////////////////
+
+
+// baeckler - 02-13-2007
+//
+// 'base' is a one hot signal indicating the first request
+// that should be considered for a grant.  Followed by higher
+// indexed requests, then wrapping around.
+//
+
+module arbiter (
+	req, grant, base
+);
+
+parameter WIDTH = 16;
+
+input [WIDTH-1:0] req;
+output [WIDTH-1:0] grant;
+input [WIDTH-1:0] base;
+
+wire [2*WIDTH-1:0] double_req = {req,req};
+wire [2*WIDTH-1:0] double_grant = double_req & ~(double_req-base);
+assign grant = double_grant[WIDTH-1:0] | double_grant[2*WIDTH-1:WIDTH];
+	
+endmodule

Advanced Synthesis Cookbook/arbitration/arbiter_tb.v

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+// Copyright 2007 Altera Corporation. All rights reserved.  
+// Altera products are protected under numerous U.S. and foreign patents, 
+// maskwork rights, copyrights and other intellectual property laws.  
+//
+// This reference design file, and your use thereof, is subject to and governed
+// by the terms and conditions of the applicable Altera Reference Design 
+// License Agreement (either as signed by you or found at www.altera.com).  By
+// using this reference design file, you indicate your acceptance of such terms
+// and conditions between you and Altera Corporation.  In the event that you do
+// not agree with such terms and conditions, you may not use the reference 
+// design file and please promptly destroy any copies you have made.
+//
+// This reference design file is being provided on an "as-is" basis and as an 
+// accommodation and therefore all warranties, representations or guarantees of 
+// any kind (whether express, implied or statutory) including, without 
+// limitation, warranties of merchantability, non-infringement, or fitness for
+// a particular purpose, are specifically disclaimed.  By making this reference
+// design file available, Altera expressly does not recommend, suggest or 
+// require that this reference design file be used in combination with any 
+// other product not provided by Altera.
+/////////////////////////////////////////////////////////////////////////////
+
+
+//baeckler - 02-13-2007
+
+module arbiter_tb ();
+
+reg [15:0] req;
+reg [3:0] base;
+
+wire [15:0] grant, grant_two;
+reg fail;
+
+// weaker unit for testing
+reference_arbiter arb (.req(req),.base(base),.grant(grant));
+
+// convert the encoded base to one hot
+// ideally it would be generated in one hot
+reg [15:0] decoded_base;
+always @(*) begin
+	decoded_base = 0;
+	decoded_base[base] = 1'b1;
+end
+
+// device under test
+arbiter a2 (.req(req),.grant(grant_two),.base(decoded_base));
+	defparam a2 .WIDTH = 16;
+
+always begin
+	#100
+	req = $random & $random & $random;
+	base = $random;
+	
+	#5 
+	if (grant !== grant_two) begin
+		$display ("Mismatch at time %d",$time);
+		fail = 1;
+	end
+end
+
+initial begin
+	fail = 0;
+	#1000000 if (!fail) $display ("PASS");
+	$stop();
+end
+
+endmodule
+
+
+/////////////////////////////////////////
+// Less efficient easier to understand
+// unit for reference
+/////////////////////////////////////////
+module reference_arbiter (
+	req,grant,base
+);
+
+input [15:0] req;
+output [15:0] grant;
+input [3:0] base;
+
+// rotate the request lines
+wire [15:0] b0 = base[0] ? {req[0],req[15:1]} : req[15:0] ;
+wire [15:0] b1 = base[1] ? {b0[1:0],b0[15:2]} : b0[15:0] ;
+wire [15:0] b2 = base[2] ? {b1[3:0],b1[15:4]} : b1[15:0] ;
+wire [15:0] b3 = base[3] ? {b2[7:0],b2[15:8]} : b2[15:0] ;
+
+// pick the lowest one for a grant
+wire [15:0] rotated_grant = b3 & ~(b3-1);
+
+// unrotate the grant
+wire [15:0] b4 = base[0] ? {rotated_grant[14:0],rotated_grant[15]} : rotated_grant[15:0] ;
+wire [15:0] b5 = base[1] ? {b4[13:0],b4[15:14]} : b4[15:0] ;
+wire [15:0] b6 = base[2] ? {b5[11:0],b5[15:12]} : b5[15:0] ;
+wire [15:0] b7 = base[3] ? {b6[7:0],b6[15:8]} : b6[15:0] ;
+
+assign grant = b7;
+
+endmodule

Advanced Synthesis Cookbook/arbitration/bitscan.v

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+// Copyright 2007 Altera Corporation. All rights reserved.  
+// Altera products are protected under numerous U.S. and foreign patents, 
+// maskwork rights, copyrights and other intellectual property laws.  
+//
+// This reference design file, and your use thereof, is subject to and governed
+// by the terms and conditions of the applicable Altera Reference Design 
+// License Agreement (either as signed by you or found at www.altera.com).  By
+// using this reference design file, you indicate your acceptance of such terms
+// and conditions between you and Altera Corporation.  In the event that you do
+// not agree with such terms and conditions, you may not use the reference 
+// design file and please promptly destroy any copies you have made.
+//
+// This reference design file is being provided on an "as-is" basis and as an 
+// accommodation and therefore all warranties, representations or guarantees of 
+// any kind (whether express, implied or statutory) including, without 
+// limitation, warranties of merchantability, non-infringement, or fitness for
+// a particular purpose, are specifically disclaimed.  By making this reference
+// design file available, Altera expressly does not recommend, suggest or 
+// require that this reference design file be used in combination with any 
+// other product not provided by Altera.
+/////////////////////////////////////////////////////////////////////////////
+
+module bitscan (req,sel);
+parameter WIDTH = 16;
+input [WIDTH-1:0] req;
+output [WIDTH-1:0] sel;
+
+assign sel = req & ~(req-1);
+
+endmodule
+

Advanced Synthesis Cookbook/arbitration/bitscan_tb.v

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+// Copyright 2007 Altera Corporation. All rights reserved.  
+// Altera products are protected under numerous U.S. and foreign patents, 
+// maskwork rights, copyrights and other intellectual property laws.  
+//
+// This reference design file, and your use thereof, is subject to and governed
+// by the terms and conditions of the applicable Altera Reference Design 
+// License Agreement (either as signed by you or found at www.altera.com).  By
+// using this reference design file, you indicate your acceptance of such terms
+// and conditions between you and Altera Corporation.  In the event that you do
+// not agree with such terms and conditions, you may not use the reference 
+// design file and please promptly destroy any copies you have made.
+//
+// This reference design file is being provided on an "as-is" basis and as an 
+// accommodation and therefore all warranties, representations or guarantees of 
+// any kind (whether express, implied or statutory) including, without 
+// limitation, warranties of merchantability, non-infringement, or fitness for
+// a particular purpose, are specifically disclaimed.  By making this reference
+// design file available, Altera expressly does not recommend, suggest or 
+// require that this reference design file be used in combination with any 
+// other product not provided by Altera.
+/////////////////////////////////////////////////////////////////////////////
+
+
+module bitscan_tb ();
+parameter WIDTH = 16;
+reg [WIDTH-1:0] req;
+wire [WIDTH-1:0] sel;
+
+bitscan b (.req(req),.sel(sel));
+  defparam b .WIDTH = WIDTH;
+
+initial begin
+  req = 16'h8000;
+end
+
+integer n;
+reg [WIDTH-1:0] result;
+reg fail = 0;
+
+always begin 
+  #100 req = $random & $random & $random;
+  #10 
+  result = 0;
+  for (n=0; n<WIDTH; n=n+1)
+  begin
+	if (req[n] == 1'b1) begin
+		result[n] = 1'b1;
+		n = WIDTH;
+	end
+  end
+  #10 if (sel !== result) begin
+	$display ("Mismatch at time %d",$time);
+	fail = 1'b1;
+	$stop();
+  end
+end
+
+initial begin
+	#1000000 if (!fail) $display ("PASS");
+	$stop();
+end
+
+endmodule

Advanced Synthesis Cookbook/arbitration/log2.inc

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+// Copyright 2007 Altera Corporation. All rights reserved.  
+// Altera products are protected under numerous U.S. and foreign patents, 
+// maskwork rights, copyrights and other intellectual property laws.  
+//
+// This reference design file, and your use thereof, is subject to and governed
+// by the terms and conditions of the applicable Altera Reference Design 
+// License Agreement (either as signed by you or found at www.altera.com).  By
+// using this reference design file, you indicate your acceptance of such terms
+// and conditions between you and Altera Corporation.  In the event that you do
+// not agree with such terms and conditions, you may not use the reference 
+// design file and please promptly destroy any copies you have made.
+//
+// This reference design file is being provided on an "as-is" basis and as an 
+// accommodation and therefore all warranties, representations or guarantees of 
+// any kind (whether express, implied or statutory) including, without 
+// limitation, warranties of merchantability, non-infringement, or fitness for
+// a particular purpose, are specifically disclaimed.  By making this reference
+// design file available, Altera expressly does not recommend, suggest or 
+// require that this reference design file be used in combination with any 
+// other product not provided by Altera.
+/////////////////////////////////////////////////////////////////////////////
+
+// baeckler - 12-12-2006
+// helper function to compute LOG base 2
+//
+// NOTE - This is a somewhat abusive definition of LOG2(v) as the
+//   number of bits required to represent "v".  So log2(256) will be
+//   9 rather than 8 (256 = 9'b1_0000_0000).  I apologize for any
+//   confusion this may cause.
+//
+
+function integer log2;
+  input integer val;
+  begin
+	 log2 = 0;
+	 while (val > 0) begin
+	    val = val >> 1;
+		log2 = log2 + 1;
+	 end
+  end
+endfunction

Advanced Synthesis Cookbook/arbitration/prio_encode.cpp

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+// Copyright 2007 Altera Corporation. All rights reserved.  
+// Altera products are protected under numerous U.S. and foreign patents, 
+// maskwork rights, copyrights and other intellectual property laws.  
+//
+// This reference design file, and your use thereof, is subject to and governed
+// by the terms and conditions of the applicable Altera Reference Design 
+// License Agreement (either as signed by you or found at www.altera.com).  By
+// using this reference design file, you indicate your acceptance of such terms
+// and conditions between you and Altera Corporation.  In the event that you do
+// not agree with such terms and conditions, you may not use the reference 
+// design file and please promptly destroy any copies you have made.
+//
+// This reference design file is being provided on an "as-is" basis and as an 
+// accommodation and therefore all warranties, representations or guarantees of 
+// any kind (whether express, implied or statutory) including, without 
+// limitation, warranties of merchantability, non-infringement, or fitness for
+// a particular purpose, are specifically disclaimed.  By making this reference
+// design file available, Altera expressly does not recommend, suggest or 
+// require that this reference design file be used in combination with any 
+// other product not provided by Altera.
+/////////////////////////////////////////////////////////////////////////////
+
+//baeckler - 11-14-2006
+
+#include <stdio.h>
+
+int log2 (int n)
+{
+	int bits = 0;
+	while (n)
+	{
+		n >>= 1;
+		bits++;
+	}
+	return (bits);
+}
+
+int main (void)
+{
+	unsigned int num_ins = 6;
+	unsigned int num_outs = log2(num_ins);
+
+	unsigned int num_cases = (1<<num_ins);
+	unsigned int n = 0, k = 0;
+	unsigned int out_val = 0;
+
+	fprintf (stdout,"//baeckler - 11-14-2006\n");
+	fprintf (stdout,"// priority encoder\n");
+	fprintf (stdout,"//   no requests - output = 0\n");
+	fprintf (stdout,"//   request bit 0 (highest priority) - output = 1\n");
+	fprintf (stdout,"//   request bit %d (lowest priority) - output = %d\n",num_ins-1,num_ins);
+	fprintf (stdout,"module prio_encode (reqs,out);\n");
+	fprintf (stdout,"input [%d:0] reqs;\n",num_ins-1);
+	fprintf (stdout,"output [%d:0] out;\n",num_outs-1);
+	fprintf (stdout,"reg [%d:0] out;\n\n",num_outs-1);
+
+	fprintf (stdout,"    always @(*) begin\n");
+	fprintf (stdout,"      case(reqs)\n");
+	
+	fprintf (stdout,"        // 0 is special, no reqs\n");
+	fprintf (stdout,"        %d'd%d: out = %d;\n\n",num_ins,0,0);		    
+	
+	for (n=1; n<num_cases; n++)
+	{	
+		out_val = 1;
+		k = n;
+		while (k && !(k&1))
+		{
+			k >>=1;
+			out_val += 1;	
+		}	
+		fprintf (stdout,"        %d'd%d: out = %d;\n",num_ins,n,out_val);		    
+	}
+	fprintf (stdout,"      endcase\n");
+	fprintf (stdout,"    end\n");
+	fprintf (stdout,"endmodule\n");
+	return (0);
+}