fix orderning

ccattuto · ccattuto · commit bbe219f1d018 · 2024-05-04T21:57:41.000+02:00
diff --git a/uart/UARTReceiver.v b/uart/UARTReceiver.v
@@ -132,9 +132,9 @@ module UARTReceiver #(
                 `STOP_BIT: begin
                     if (&sampleCount) begin
                         if (&inputReg) begin
-                            valid <= 1;
                             if (!valid) begin
                                 out <= data;
+                                valid <= 1;
                             end else begin
                                 overrun <= 1;
                             end
