RX "valid" goes high one clock cycle after received data has been latched into "out".

Author: ccattuto

uart/UARTReceiver.v

@@ -64,6 +64,7 @@ module UARTReceiver #(
     reg [2:0] inputReg;     // shift reg for input signal
     reg [3:0] sampleCount;   // clock count for 16x oversample
     reg [7:0] data;         // input data buffer
+    reg data_ready;
 
     always @(posedge clk) begin
         if (reset || !enable) begin
@@ -72,7 +73,10 @@ module UARTReceiver #(
         end else if (rxCounter < RX_CLOCK_PERIOD - 1) begin
             // RX clock
             rxCounter <= rxCounter + 1;
-            if (ready) begin
+            if (data_ready) begin
+                data_ready <= 0;
+                valid <= 1;
+            end else if (ready) begin
                 valid <= 0;
             end
         end else begin
@@ -90,6 +94,7 @@ module UARTReceiver #(
                     bitIndex <= 3'b0;
                     sampleCount <= 4'b0;
                     data <= 8'b0;
+                    data_ready <= 0;
                     if (enable) begin
                         state <= `IDLE;
                     end
@@ -101,6 +106,7 @@ module UARTReceiver #(
                         bitIndex <= 3'b0;
                         sampleCount <= 4'b0;
                         data <= 8'b0;
+                        data_ready <= 0;
                         error <= 0;
                         overrun <= 0;
                     end else if (!(|inputReg) || (|sampleCount)) begin
@@ -134,7 +140,7 @@ module UARTReceiver #(
                         if (&inputReg) begin
                             if (!valid) begin
                                 out <= data;
-                                valid <= 1;
+                                data_ready <= 1;
                             end else begin
                                 overrun <= 1;
                             end