From c6fc946912c5f7077f08e31f0e4ebf2f76063324 Mon Sep 17 00:00:00 2001 From: dean Date: Thu, 21 Sep 2017 18:01:35 -0400 Subject: [PATCH] DM: actually fixed warnings --- .../ATMEL/samd51/include/component/ac.h | 198 +- .../ATMEL/samd51/include/component/adc.h | 422 +-- .../ATMEL/samd51/include/component/aes.h | 152 +- .../ATMEL/samd51/include/component/ccl.h | 116 +- .../ATMEL/samd51/include/component/cmcc.h | 142 +- .../ATMEL/samd51/include/component/dac.h | 142 +- .../ATMEL/samd51/include/component/dmac.h | 456 +-- .../ATMEL/samd51/include/component/dsu.h | 346 +-- .../ATMEL/samd51/include/component/eic.h | 234 +- .../ATMEL/samd51/include/component/evsys.h | 118 +- .../ATMEL/samd51/include/component/freqm.h | 60 +- .../ATMEL/samd51/include/component/gclk.h | 110 +- .../ATMEL/samd51/include/component/hmatrixb.h | 8 +- .../ATMEL/samd51/include/component/i2s.h | 300 +- .../ATMEL/samd51/include/component/icm.h | 234 +- .../ATMEL/samd51/include/component/mclk.h | 216 +- .../ATMEL/samd51/include/component/nvmctrl.h | 372 +-- .../samd51/include/component/osc32kctrl.h | 102 +- .../ATMEL/samd51/include/component/oscctrl.h | 306 +- .../ATMEL/samd51/include/component/pac.h | 326 +- .../ATMEL/samd51/include/component/pcc.h | 74 +- .../ATMEL/samd51/include/component/pdec.h | 288 +- .../ATMEL/samd51/include/component/pm.h | 80 +- .../ATMEL/samd51/include/component/port.h | 138 +- .../ATMEL/samd51/include/component/qspi.h | 226 +- .../ATMEL/samd51/include/component/ramecc.h | 44 +- .../ATMEL/samd51/include/component/rstc.h | 30 +- .../ATMEL/samd51/include/component/rtc.h | 728 ++--- .../ATMEL/samd51/include/component/sdhc.h | 1708 +++++------ .../ATMEL/samd51/include/component/sercom.h | 652 ++-- .../ATMEL/samd51/include/component/supc.h | 266 +- .../ATMEL/samd51/include/component/tal.h | 474 +-- .../ATMEL/samd51/include/component/tc.h | 298 +- .../ATMEL/samd51/include/component/tcc.h | 674 ++-- .../ATMEL/samd51/include/component/trng.h | 38 +- .../ATMEL/samd51/include/component/usb.h | 616 ++-- .../ATMEL/samd51/include/component/wdt.h | 134 +- .../ATMEL/samd51/include/pio/samd51g18a.h | 1260 ++++---- .../ATMEL/samd51/include/pio/samd51g19a.h | 1260 ++++---- .../ATMEL/samd51/include/pio/samd51j18a.h | 1744 +++++------ .../ATMEL/samd51/include/pio/samd51j19a.h | 1744 +++++------ .../ATMEL/samd51/include/pio/samd51j20a.h | 1744 +++++------ .../ATMEL/samd51/include/pio/samd51n19a.h | 2416 +++++++-------- .../ATMEL/samd51/include/pio/samd51n20a.h | 2416 +++++++-------- .../ATMEL/samd51/include/pio/samd51p19a.h | 2712 ++++++++--------- .../ATMEL/samd51/include/pio/samd51p20a.h | 2712 ++++++++--------- .../Device/ATMEL/samd51/include/samd51.h | 2 - .../Device/ATMEL/samd51/include/samd51g18a.h | 11 + .../Device/ATMEL/samd51/include/samd51g19a.h | 11 + .../Device/ATMEL/samd51/include/samd51j18a.h | 11 + .../Device/ATMEL/samd51/include/samd51j19a.h | 11 + .../Device/ATMEL/samd51/include/samd51j20a.h | 11 + .../Device/ATMEL/samd51/include/samd51n19a.h | 11 + .../Device/ATMEL/samd51/include/samd51n20a.h | 11 + .../Device/ATMEL/samd51/include/samd51p19a.h | 11 + .../Device/ATMEL/samd51/include/samd51p20a.h | 11 + 56 files changed, 14517 insertions(+), 14420 deletions(-) diff --git a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/ac.h b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/ac.h index 4dff3fe..316787d 100644 --- a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/ac.h +++ b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/ac.h @@ -51,13 +51,13 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ -#define AC_CTRLA_RESETVALUE _U(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ +#define AC_CTRLA_RESETVALUE _Ul(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ #define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ -#define AC_CTRLA_SWRST (_U(0x1) << AC_CTRLA_SWRST_Pos) +#define AC_CTRLA_SWRST (_Ul(0x1) << AC_CTRLA_SWRST_Pos) #define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ -#define AC_CTRLA_ENABLE (_U(0x1) << AC_CTRLA_ENABLE_Pos) -#define AC_CTRLA_MASK _U(0x03) /**< \brief (AC_CTRLA) MASK Register */ +#define AC_CTRLA_ENABLE (_Ul(0x1) << AC_CTRLA_ENABLE_Pos) +#define AC_CTRLA_MASK _Ul(0x03) /**< \brief (AC_CTRLA) MASK Register */ /* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -76,16 +76,16 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ -#define AC_CTRLB_RESETVALUE _U(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ +#define AC_CTRLB_RESETVALUE _Ul(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ #define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ #define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos) #define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ #define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos) #define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ -#define AC_CTRLB_START_Msk (_U(0x3) << AC_CTRLB_START_Pos) +#define AC_CTRLB_START_Msk (_Ul(0x3) << AC_CTRLB_START_Pos) #define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) -#define AC_CTRLB_MASK _U(0x03) /**< \brief (AC_CTRLB) MASK Register */ +#define AC_CTRLB_MASK _Ul(0x03) /**< \brief (AC_CTRLB) MASK Register */ /* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -118,35 +118,35 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ -#define AC_EVCTRL_RESETVALUE _U(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ +#define AC_EVCTRL_RESETVALUE _Ul(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ #define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ #define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos) #define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ #define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos) #define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ -#define AC_EVCTRL_COMPEO_Msk (_U(0x3) << AC_EVCTRL_COMPEO_Pos) +#define AC_EVCTRL_COMPEO_Msk (_Ul(0x3) << AC_EVCTRL_COMPEO_Pos) #define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) #define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ #define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos) #define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ -#define AC_EVCTRL_WINEO_Msk (_U(0x1) << AC_EVCTRL_WINEO_Pos) +#define AC_EVCTRL_WINEO_Msk (_Ul(0x1) << AC_EVCTRL_WINEO_Pos) #define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) #define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ #define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos) #define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ #define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos) #define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ -#define AC_EVCTRL_COMPEI_Msk (_U(0x3) << AC_EVCTRL_COMPEI_Pos) +#define AC_EVCTRL_COMPEI_Msk (_Ul(0x3) << AC_EVCTRL_COMPEI_Pos) #define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) #define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ #define AC_EVCTRL_INVEI0 (1 << AC_EVCTRL_INVEI0_Pos) #define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ #define AC_EVCTRL_INVEI1 (1 << AC_EVCTRL_INVEI1_Pos) #define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ -#define AC_EVCTRL_INVEI_Msk (_U(0x3) << AC_EVCTRL_INVEI_Pos) +#define AC_EVCTRL_INVEI_Msk (_Ul(0x3) << AC_EVCTRL_INVEI_Pos) #define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) -#define AC_EVCTRL_MASK _U(0x3313) /**< \brief (AC_EVCTRL) MASK Register */ +#define AC_EVCTRL_MASK _Ul(0x3313) /**< \brief (AC_EVCTRL) MASK Register */ /* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -169,21 +169,21 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ -#define AC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ +#define AC_INTENCLR_RESETVALUE _Ul(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ #define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ #define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos) #define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ #define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos) #define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ -#define AC_INTENCLR_COMP_Msk (_U(0x3) << AC_INTENCLR_COMP_Pos) +#define AC_INTENCLR_COMP_Msk (_Ul(0x3) << AC_INTENCLR_COMP_Pos) #define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) #define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ #define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos) #define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ -#define AC_INTENCLR_WIN_Msk (_U(0x1) << AC_INTENCLR_WIN_Pos) +#define AC_INTENCLR_WIN_Msk (_Ul(0x1) << AC_INTENCLR_WIN_Pos) #define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) -#define AC_INTENCLR_MASK _U(0x13) /**< \brief (AC_INTENCLR) MASK Register */ +#define AC_INTENCLR_MASK _Ul(0x13) /**< \brief (AC_INTENCLR) MASK Register */ /* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -206,21 +206,21 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ -#define AC_INTENSET_RESETVALUE _U(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ +#define AC_INTENSET_RESETVALUE _Ul(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ #define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ #define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos) #define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ #define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos) #define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ -#define AC_INTENSET_COMP_Msk (_U(0x3) << AC_INTENSET_COMP_Pos) +#define AC_INTENSET_COMP_Msk (_Ul(0x3) << AC_INTENSET_COMP_Pos) #define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) #define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ #define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos) #define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ -#define AC_INTENSET_WIN_Msk (_U(0x1) << AC_INTENSET_WIN_Pos) +#define AC_INTENSET_WIN_Msk (_Ul(0x1) << AC_INTENSET_WIN_Pos) #define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) -#define AC_INTENSET_MASK _U(0x13) /**< \brief (AC_INTENSET) MASK Register */ +#define AC_INTENSET_MASK _Ul(0x13) /**< \brief (AC_INTENSET) MASK Register */ /* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -243,21 +243,21 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define AC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ +#define AC_INTFLAG_RESETVALUE _Ul(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ #define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ #define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos) #define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ #define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos) #define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ -#define AC_INTFLAG_COMP_Msk (_U(0x3) << AC_INTFLAG_COMP_Pos) +#define AC_INTFLAG_COMP_Msk (_Ul(0x3) << AC_INTFLAG_COMP_Pos) #define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) #define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ #define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos) #define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ -#define AC_INTFLAG_WIN_Msk (_U(0x1) << AC_INTFLAG_WIN_Pos) +#define AC_INTFLAG_WIN_Msk (_Ul(0x1) << AC_INTFLAG_WIN_Pos) #define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) -#define AC_INTFLAG_MASK _U(0x13) /**< \brief (AC_INTFLAG) MASK Register */ +#define AC_INTFLAG_MASK _Ul(0x13) /**< \brief (AC_INTFLAG) MASK Register */ /* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -278,25 +278,25 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ -#define AC_STATUSA_RESETVALUE _U(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ +#define AC_STATUSA_RESETVALUE _Ul(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ #define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ #define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos) #define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ #define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos) #define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ -#define AC_STATUSA_STATE_Msk (_U(0x3) << AC_STATUSA_STATE_Pos) +#define AC_STATUSA_STATE_Msk (_Ul(0x3) << AC_STATUSA_STATE_Pos) #define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) #define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ -#define AC_STATUSA_WSTATE0_Msk (_U(0x3) << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_Msk (_Ul(0x3) << AC_STATUSA_WSTATE0_Pos) #define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) -#define AC_STATUSA_WSTATE0_ABOVE_Val _U(0x0) /**< \brief (AC_STATUSA) Signal is above window */ -#define AC_STATUSA_WSTATE0_INSIDE_Val _U(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ -#define AC_STATUSA_WSTATE0_BELOW_Val _U(0x2) /**< \brief (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE_Val _Ul(0x0) /**< \brief (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _Ul(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _Ul(0x2) /**< \brief (AC_STATUSA) Signal is below window */ #define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) #define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) #define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_MASK _U(0x33) /**< \brief (AC_STATUSA) MASK Register */ +#define AC_STATUSA_MASK _Ul(0x33) /**< \brief (AC_STATUSA) MASK Register */ /* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -315,16 +315,16 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ -#define AC_STATUSB_RESETVALUE _U(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ +#define AC_STATUSB_RESETVALUE _Ul(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ #define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ #define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos) #define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ #define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos) #define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ -#define AC_STATUSB_READY_Msk (_U(0x3) << AC_STATUSB_READY_Pos) +#define AC_STATUSB_READY_Msk (_Ul(0x3) << AC_STATUSB_READY_Pos) #define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) -#define AC_STATUSB_MASK _U(0x03) /**< \brief (AC_STATUSB) MASK Register */ +#define AC_STATUSB_MASK _Ul(0x03) /**< \brief (AC_STATUSB) MASK Register */ /* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -338,11 +338,11 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ -#define AC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */ +#define AC_DBGCTRL_RESETVALUE _Ul(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */ #define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ -#define AC_DBGCTRL_DBGRUN (_U(0x1) << AC_DBGCTRL_DBGRUN_Pos) -#define AC_DBGCTRL_MASK _U(0x01) /**< \brief (AC_DBGCTRL) MASK Register */ +#define AC_DBGCTRL_DBGRUN (_Ul(0x1) << AC_DBGCTRL_DBGRUN_Pos) +#define AC_DBGCTRL_MASK _Ul(0x01) /**< \brief (AC_DBGCTRL) MASK Register */ /* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -357,22 +357,22 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ -#define AC_WINCTRL_RESETVALUE _U(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ +#define AC_WINCTRL_RESETVALUE _Ul(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ #define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ -#define AC_WINCTRL_WEN0 (_U(0x1) << AC_WINCTRL_WEN0_Pos) +#define AC_WINCTRL_WEN0 (_Ul(0x1) << AC_WINCTRL_WEN0_Pos) #define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ -#define AC_WINCTRL_WINTSEL0_Msk (_U(0x3) << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_Msk (_Ul(0x3) << AC_WINCTRL_WINTSEL0_Pos) #define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) -#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ -#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ -#define AC_WINCTRL_WINTSEL0_BELOW_Val _U(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ -#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _Ul(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _Ul(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _Ul(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _Ul(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ #define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) #define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) #define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) #define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_MASK _U(0x07) /**< \brief (AC_WINCTRL) MASK Register */ +#define AC_WINCTRL_MASK _Ul(0x07) /**< \brief (AC_WINCTRL) MASK Register */ /* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -386,12 +386,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ -#define AC_SCALER_RESETVALUE _U(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ +#define AC_SCALER_RESETVALUE _Ul(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ #define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ -#define AC_SCALER_VALUE_Msk (_U(0x3F) << AC_SCALER_VALUE_Pos) +#define AC_SCALER_VALUE_Msk (_Ul(0x3F) << AC_SCALER_VALUE_Pos) #define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) -#define AC_SCALER_MASK _U(0x3F) /**< \brief (AC_SCALER) MASK Register */ +#define AC_SCALER_MASK _Ul(0x3F) /**< \brief (AC_SCALER) MASK Register */ /* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -423,36 +423,36 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ -#define AC_COMPCTRL_RESETVALUE _U(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ +#define AC_COMPCTRL_RESETVALUE _Ul(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ #define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ -#define AC_COMPCTRL_ENABLE (_U(0x1) << AC_COMPCTRL_ENABLE_Pos) +#define AC_COMPCTRL_ENABLE (_Ul(0x1) << AC_COMPCTRL_ENABLE_Pos) #define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ -#define AC_COMPCTRL_SINGLE (_U(0x1) << AC_COMPCTRL_SINGLE_Pos) +#define AC_COMPCTRL_SINGLE (_Ul(0x1) << AC_COMPCTRL_SINGLE_Pos) #define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ -#define AC_COMPCTRL_INTSEL_Msk (_U(0x3) << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_Msk (_Ul(0x3) << AC_COMPCTRL_INTSEL_Pos) #define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) -#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ -#define AC_COMPCTRL_INTSEL_RISING_Val _U(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ -#define AC_COMPCTRL_INTSEL_FALLING_Val _U(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ -#define AC_COMPCTRL_INTSEL_EOC_Val _U(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _Ul(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _Ul(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _Ul(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _Ul(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ #define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) #define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) #define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) #define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) #define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ -#define AC_COMPCTRL_RUNSTDBY (_U(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) +#define AC_COMPCTRL_RUNSTDBY (_Ul(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) #define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ -#define AC_COMPCTRL_MUXNEG_Msk (_U(0x7) << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_Msk (_Ul(0x7) << AC_COMPCTRL_MUXNEG_Pos) #define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) -#define AC_COMPCTRL_MUXNEG_PIN0_Val _U(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXNEG_PIN1_Val _U(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXNEG_PIN2_Val _U(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXNEG_PIN3_Val _U(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXNEG_GND_Val _U(0x4) /**< \brief (AC_COMPCTRL) Ground */ -#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ -#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ -#define AC_COMPCTRL_MUXNEG_DAC_Val _U(0x7) /**< \brief (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0_Val _Ul(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _Ul(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _Ul(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _Ul(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _Ul(0x4) /**< \brief (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _Ul(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _Ul(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _Ul(0x7) /**< \brief (AC_COMPCTRL) DAC output */ #define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) #define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) #define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) @@ -462,55 +462,55 @@ typedef union { #define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) #define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) #define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ -#define AC_COMPCTRL_MUXPOS_Msk (_U(0x7) << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_Msk (_Ul(0x7) << AC_COMPCTRL_MUXPOS_Pos) #define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) -#define AC_COMPCTRL_MUXPOS_PIN0_Val _U(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXPOS_PIN1_Val _U(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXPOS_PIN2_Val _U(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXPOS_PIN3_Val _U(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */ +#define AC_COMPCTRL_MUXPOS_PIN0_Val _Ul(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _Ul(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _Ul(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _Ul(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_VSCALE_Val _Ul(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */ #define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) #define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) #define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) #define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) #define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) #define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ -#define AC_COMPCTRL_SWAP (_U(0x1) << AC_COMPCTRL_SWAP_Pos) +#define AC_COMPCTRL_SWAP (_Ul(0x1) << AC_COMPCTRL_SWAP_Pos) #define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ -#define AC_COMPCTRL_SPEED_Msk (_U(0x3) << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_Msk (_Ul(0x3) << AC_COMPCTRL_SPEED_Pos) #define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) -#define AC_COMPCTRL_SPEED_HIGH_Val _U(0x3) /**< \brief (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_HIGH_Val _Ul(0x3) /**< \brief (AC_COMPCTRL) High speed */ #define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) #define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ -#define AC_COMPCTRL_HYSTEN (_U(0x1) << AC_COMPCTRL_HYSTEN_Pos) +#define AC_COMPCTRL_HYSTEN (_Ul(0x1) << AC_COMPCTRL_HYSTEN_Pos) #define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ -#define AC_COMPCTRL_HYST_Msk (_U(0x3) << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_Msk (_Ul(0x3) << AC_COMPCTRL_HYST_Pos) #define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) -#define AC_COMPCTRL_HYST_HYST50_Val _U(0x0) /**< \brief (AC_COMPCTRL) 50mV */ -#define AC_COMPCTRL_HYST_HYST100_Val _U(0x1) /**< \brief (AC_COMPCTRL) 100mV */ -#define AC_COMPCTRL_HYST_HYST150_Val _U(0x2) /**< \brief (AC_COMPCTRL) 150mV */ +#define AC_COMPCTRL_HYST_HYST50_Val _Ul(0x0) /**< \brief (AC_COMPCTRL) 50mV */ +#define AC_COMPCTRL_HYST_HYST100_Val _Ul(0x1) /**< \brief (AC_COMPCTRL) 100mV */ +#define AC_COMPCTRL_HYST_HYST150_Val _Ul(0x2) /**< \brief (AC_COMPCTRL) 150mV */ #define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) #define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos) #define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos) #define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ -#define AC_COMPCTRL_FLEN_Msk (_U(0x7) << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_Msk (_Ul(0x7) << AC_COMPCTRL_FLEN_Pos) #define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) -#define AC_COMPCTRL_FLEN_OFF_Val _U(0x0) /**< \brief (AC_COMPCTRL) No filtering */ -#define AC_COMPCTRL_FLEN_MAJ3_Val _U(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ -#define AC_COMPCTRL_FLEN_MAJ5_Val _U(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF_Val _Ul(0x0) /**< \brief (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _Ul(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _Ul(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ #define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) #define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) #define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) #define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ -#define AC_COMPCTRL_OUT_Msk (_U(0x3) << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_Msk (_Ul(0x3) << AC_COMPCTRL_OUT_Pos) #define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) -#define AC_COMPCTRL_OUT_OFF_Val _U(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_ASYNC_Val _U(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_SYNC_Val _U(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF_Val _Ul(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _Ul(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _Ul(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ #define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) #define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) #define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_MASK _U(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */ +#define AC_COMPCTRL_MASK _Ul(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */ /* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -533,22 +533,22 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ -#define AC_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ +#define AC_SYNCBUSY_RESETVALUE _Ul(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ #define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ -#define AC_SYNCBUSY_SWRST (_U(0x1) << AC_SYNCBUSY_SWRST_Pos) +#define AC_SYNCBUSY_SWRST (_Ul(0x1) << AC_SYNCBUSY_SWRST_Pos) #define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ -#define AC_SYNCBUSY_ENABLE (_U(0x1) << AC_SYNCBUSY_ENABLE_Pos) +#define AC_SYNCBUSY_ENABLE (_Ul(0x1) << AC_SYNCBUSY_ENABLE_Pos) #define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ -#define AC_SYNCBUSY_WINCTRL (_U(0x1) << AC_SYNCBUSY_WINCTRL_Pos) +#define AC_SYNCBUSY_WINCTRL (_Ul(0x1) << AC_SYNCBUSY_WINCTRL_Pos) #define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ #define AC_SYNCBUSY_COMPCTRL0 (1 << AC_SYNCBUSY_COMPCTRL0_Pos) #define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ #define AC_SYNCBUSY_COMPCTRL1 (1 << AC_SYNCBUSY_COMPCTRL1_Pos) #define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL_Msk (_U(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL_Msk (_Ul(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) #define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) -#define AC_SYNCBUSY_MASK _U(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */ +#define AC_SYNCBUSY_MASK _Ul(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */ /* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -562,12 +562,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AC_CALIB_OFFSET 0x24 /**< \brief (AC_CALIB offset) Calibration */ -#define AC_CALIB_RESETVALUE _U(0x0101) /**< \brief (AC_CALIB reset_value) Calibration */ +#define AC_CALIB_RESETVALUE _Ul(0x0101) /**< \brief (AC_CALIB reset_value) Calibration */ #define AC_CALIB_BIAS0_Pos 0 /**< \brief (AC_CALIB) COMP0/1 Bias Scaling */ -#define AC_CALIB_BIAS0_Msk (_U(0x3) << AC_CALIB_BIAS0_Pos) +#define AC_CALIB_BIAS0_Msk (_Ul(0x3) << AC_CALIB_BIAS0_Pos) #define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos)) -#define AC_CALIB_MASK _U(0x0003) /**< \brief (AC_CALIB) MASK Register */ +#define AC_CALIB_MASK _Ul(0x0003) /**< \brief (AC_CALIB) MASK Register */ /** \brief AC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) diff --git a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/adc.h b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/adc.h index 107f454..946de25 100644 --- a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/adc.h +++ b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/adc.h @@ -58,36 +58,36 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ -#define ADC_CTRLA_RESETVALUE _U(0x0000) /**< \brief (ADC_CTRLA reset_value) Control A */ +#define ADC_CTRLA_RESETVALUE _Ul(0x0000) /**< \brief (ADC_CTRLA reset_value) Control A */ #define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ -#define ADC_CTRLA_SWRST (_U(0x1) << ADC_CTRLA_SWRST_Pos) +#define ADC_CTRLA_SWRST (_Ul(0x1) << ADC_CTRLA_SWRST_Pos) #define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ -#define ADC_CTRLA_ENABLE (_U(0x1) << ADC_CTRLA_ENABLE_Pos) +#define ADC_CTRLA_ENABLE (_Ul(0x1) << ADC_CTRLA_ENABLE_Pos) #define ADC_CTRLA_DUALSEL_Pos 3 /**< \brief (ADC_CTRLA) Dual Mode Trigger Selection */ -#define ADC_CTRLA_DUALSEL_Msk (_U(0x3) << ADC_CTRLA_DUALSEL_Pos) +#define ADC_CTRLA_DUALSEL_Msk (_Ul(0x3) << ADC_CTRLA_DUALSEL_Pos) #define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos)) -#define ADC_CTRLA_DUALSEL_BOTH_Val _U(0x0) /**< \brief (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */ -#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U(0x1) /**< \brief (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ +#define ADC_CTRLA_DUALSEL_BOTH_Val _Ul(0x0) /**< \brief (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */ +#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _Ul(0x1) /**< \brief (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ #define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos) #define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos) #define ADC_CTRLA_SLAVEEN_Pos 5 /**< \brief (ADC_CTRLA) Slave Enable */ -#define ADC_CTRLA_SLAVEEN (_U(0x1) << ADC_CTRLA_SLAVEEN_Pos) +#define ADC_CTRLA_SLAVEEN (_Ul(0x1) << ADC_CTRLA_SLAVEEN_Pos) #define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run in Standby */ -#define ADC_CTRLA_RUNSTDBY (_U(0x1) << ADC_CTRLA_RUNSTDBY_Pos) +#define ADC_CTRLA_RUNSTDBY (_Ul(0x1) << ADC_CTRLA_RUNSTDBY_Pos) #define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ -#define ADC_CTRLA_ONDEMAND (_U(0x1) << ADC_CTRLA_ONDEMAND_Pos) +#define ADC_CTRLA_ONDEMAND (_Ul(0x1) << ADC_CTRLA_ONDEMAND_Pos) #define ADC_CTRLA_PRESCALER_Pos 8 /**< \brief (ADC_CTRLA) Prescaler Configuration */ -#define ADC_CTRLA_PRESCALER_Msk (_U(0x7) << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_Msk (_Ul(0x7) << ADC_CTRLA_PRESCALER_Pos) #define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos)) -#define ADC_CTRLA_PRESCALER_DIV2_Val _U(0x0) /**< \brief (ADC_CTRLA) Peripheral clock divided by 2 */ -#define ADC_CTRLA_PRESCALER_DIV4_Val _U(0x1) /**< \brief (ADC_CTRLA) Peripheral clock divided by 4 */ -#define ADC_CTRLA_PRESCALER_DIV8_Val _U(0x2) /**< \brief (ADC_CTRLA) Peripheral clock divided by 8 */ -#define ADC_CTRLA_PRESCALER_DIV16_Val _U(0x3) /**< \brief (ADC_CTRLA) Peripheral clock divided by 16 */ -#define ADC_CTRLA_PRESCALER_DIV32_Val _U(0x4) /**< \brief (ADC_CTRLA) Peripheral clock divided by 32 */ -#define ADC_CTRLA_PRESCALER_DIV64_Val _U(0x5) /**< \brief (ADC_CTRLA) Peripheral clock divided by 64 */ -#define ADC_CTRLA_PRESCALER_DIV128_Val _U(0x6) /**< \brief (ADC_CTRLA) Peripheral clock divided by 128 */ -#define ADC_CTRLA_PRESCALER_DIV256_Val _U(0x7) /**< \brief (ADC_CTRLA) Peripheral clock divided by 256 */ +#define ADC_CTRLA_PRESCALER_DIV2_Val _Ul(0x0) /**< \brief (ADC_CTRLA) Peripheral clock divided by 2 */ +#define ADC_CTRLA_PRESCALER_DIV4_Val _Ul(0x1) /**< \brief (ADC_CTRLA) Peripheral clock divided by 4 */ +#define ADC_CTRLA_PRESCALER_DIV8_Val _Ul(0x2) /**< \brief (ADC_CTRLA) Peripheral clock divided by 8 */ +#define ADC_CTRLA_PRESCALER_DIV16_Val _Ul(0x3) /**< \brief (ADC_CTRLA) Peripheral clock divided by 16 */ +#define ADC_CTRLA_PRESCALER_DIV32_Val _Ul(0x4) /**< \brief (ADC_CTRLA) Peripheral clock divided by 32 */ +#define ADC_CTRLA_PRESCALER_DIV64_Val _Ul(0x5) /**< \brief (ADC_CTRLA) Peripheral clock divided by 64 */ +#define ADC_CTRLA_PRESCALER_DIV128_Val _Ul(0x6) /**< \brief (ADC_CTRLA) Peripheral clock divided by 128 */ +#define ADC_CTRLA_PRESCALER_DIV256_Val _Ul(0x7) /**< \brief (ADC_CTRLA) Peripheral clock divided by 256 */ #define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos) #define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos) #define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos) @@ -97,8 +97,8 @@ typedef union { #define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos) #define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos) #define ADC_CTRLA_R2R_Pos 15 /**< \brief (ADC_CTRLA) Rail to Rail Operation Enable */ -#define ADC_CTRLA_R2R (_U(0x1) << ADC_CTRLA_R2R_Pos) -#define ADC_CTRLA_MASK _U(0x87FB) /**< \brief (ADC_CTRLA) MASK Register */ +#define ADC_CTRLA_R2R (_Ul(0x1) << ADC_CTRLA_R2R_Pos) +#define ADC_CTRLA_MASK _Ul(0x87FB) /**< \brief (ADC_CTRLA) MASK Register */ /* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -117,21 +117,21 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_EVCTRL_OFFSET 0x02 /**< \brief (ADC_EVCTRL offset) Event Control */ -#define ADC_EVCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ +#define ADC_EVCTRL_RESETVALUE _Ul(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ #define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ -#define ADC_EVCTRL_FLUSHEI (_U(0x1) << ADC_EVCTRL_FLUSHEI_Pos) +#define ADC_EVCTRL_FLUSHEI (_Ul(0x1) << ADC_EVCTRL_FLUSHEI_Pos) #define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ -#define ADC_EVCTRL_STARTEI (_U(0x1) << ADC_EVCTRL_STARTEI_Pos) +#define ADC_EVCTRL_STARTEI (_Ul(0x1) << ADC_EVCTRL_STARTEI_Pos) #define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ -#define ADC_EVCTRL_FLUSHINV (_U(0x1) << ADC_EVCTRL_FLUSHINV_Pos) +#define ADC_EVCTRL_FLUSHINV (_Ul(0x1) << ADC_EVCTRL_FLUSHINV_Pos) #define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Start Conversion Event Invert Enable */ -#define ADC_EVCTRL_STARTINV (_U(0x1) << ADC_EVCTRL_STARTINV_Pos) +#define ADC_EVCTRL_STARTINV (_Ul(0x1) << ADC_EVCTRL_STARTINV_Pos) #define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ -#define ADC_EVCTRL_RESRDYEO (_U(0x1) << ADC_EVCTRL_RESRDYEO_Pos) +#define ADC_EVCTRL_RESRDYEO (_Ul(0x1) << ADC_EVCTRL_RESRDYEO_Pos) #define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ -#define ADC_EVCTRL_WINMONEO (_U(0x1) << ADC_EVCTRL_WINMONEO_Pos) -#define ADC_EVCTRL_MASK _U(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */ +#define ADC_EVCTRL_WINMONEO (_Ul(0x1) << ADC_EVCTRL_WINMONEO_Pos) +#define ADC_EVCTRL_MASK _Ul(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */ /* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -145,11 +145,11 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_DBGCTRL_OFFSET 0x03 /**< \brief (ADC_DBGCTRL offset) Debug Control */ -#define ADC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ +#define ADC_DBGCTRL_RESETVALUE _Ul(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ #define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ -#define ADC_DBGCTRL_DBGRUN (_U(0x1) << ADC_DBGCTRL_DBGRUN_Pos) -#define ADC_DBGCTRL_MASK _U(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ +#define ADC_DBGCTRL_DBGRUN (_Ul(0x1) << ADC_DBGCTRL_DBGRUN_Pos) +#define ADC_DBGCTRL_MASK _Ul(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ /* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -167,43 +167,43 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_INPUTCTRL_OFFSET 0x04 /**< \brief (ADC_INPUTCTRL offset) Input Control */ -#define ADC_INPUTCTRL_RESETVALUE _U(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ +#define ADC_INPUTCTRL_RESETVALUE _Ul(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ #define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ -#define ADC_INPUTCTRL_MUXPOS_Msk (_U(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_Msk (_Ul(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) #define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) -#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U(0x14) /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U(0x15) /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U(0x16) /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U(0x17) /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U(0x18) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U(0x19) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ -#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U(0x1B) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ -#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U(0x1C) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ -#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U(0x1D) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ -#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U(0x1E) /**< \brief (ADC_INPUTCTRL) DAC Output */ -#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U(0x1F) /**< \brief (ADC_INPUTCTRL) PTC output (only on ADC0) */ +#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _Ul(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _Ul(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _Ul(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _Ul(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _Ul(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _Ul(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _Ul(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _Ul(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _Ul(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _Ul(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _Ul(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _Ul(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _Ul(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _Ul(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _Ul(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _Ul(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _Ul(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _Ul(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _Ul(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _Ul(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _Ul(0x14) /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _Ul(0x15) /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _Ul(0x16) /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _Ul(0x17) /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _Ul(0x18) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _Ul(0x19) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _Ul(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _Ul(0x1B) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _Ul(0x1C) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ +#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _Ul(0x1D) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ +#define ADC_INPUTCTRL_MUXPOS_DAC_Val _Ul(0x1E) /**< \brief (ADC_INPUTCTRL) DAC Output */ +#define ADC_INPUTCTRL_MUXPOS_PTC_Val _Ul(0x1F) /**< \brief (ADC_INPUTCTRL) PTC output (only on ADC0) */ #define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) #define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) #define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) @@ -237,19 +237,19 @@ typedef union { #define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) #define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos) #define ADC_INPUTCTRL_DIFFMODE_Pos 7 /**< \brief (ADC_INPUTCTRL) Differential Mode */ -#define ADC_INPUTCTRL_DIFFMODE (_U(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos) +#define ADC_INPUTCTRL_DIFFMODE (_Ul(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos) #define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ -#define ADC_INPUTCTRL_MUXNEG_Msk (_U(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_Msk (_Ul(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) #define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) -#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXNEG_GND_Val _U(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */ +#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _Ul(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _Ul(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _Ul(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _Ul(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _Ul(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _Ul(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _Ul(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _Ul(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val _Ul(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */ #define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) #define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) #define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) @@ -260,8 +260,8 @@ typedef union { #define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) #define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) #define ADC_INPUTCTRL_DSEQSTOP_Pos 15 /**< \brief (ADC_INPUTCTRL) Stop DMA Sequencing */ -#define ADC_INPUTCTRL_DSEQSTOP (_U(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos) -#define ADC_INPUTCTRL_MASK _U(0x9F9F) /**< \brief (ADC_INPUTCTRL) MASK Register */ +#define ADC_INPUTCTRL_DSEQSTOP (_Ul(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos) +#define ADC_INPUTCTRL_MASK _Ul(0x9F9F) /**< \brief (ADC_INPUTCTRL) MASK Register */ /* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -281,41 +281,41 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_CTRLB_OFFSET 0x06 /**< \brief (ADC_CTRLB offset) Control B */ -#define ADC_CTRLB_RESETVALUE _U(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */ +#define ADC_CTRLB_RESETVALUE _Ul(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */ #define ADC_CTRLB_LEFTADJ_Pos 0 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ -#define ADC_CTRLB_LEFTADJ (_U(0x1) << ADC_CTRLB_LEFTADJ_Pos) +#define ADC_CTRLB_LEFTADJ (_Ul(0x1) << ADC_CTRLB_LEFTADJ_Pos) #define ADC_CTRLB_FREERUN_Pos 1 /**< \brief (ADC_CTRLB) Free Running Mode */ -#define ADC_CTRLB_FREERUN (_U(0x1) << ADC_CTRLB_FREERUN_Pos) +#define ADC_CTRLB_FREERUN (_Ul(0x1) << ADC_CTRLB_FREERUN_Pos) #define ADC_CTRLB_CORREN_Pos 2 /**< \brief (ADC_CTRLB) Digital Correction Logic Enable */ -#define ADC_CTRLB_CORREN (_U(0x1) << ADC_CTRLB_CORREN_Pos) +#define ADC_CTRLB_CORREN (_Ul(0x1) << ADC_CTRLB_CORREN_Pos) #define ADC_CTRLB_RESSEL_Pos 3 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ -#define ADC_CTRLB_RESSEL_Msk (_U(0x3) << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_Msk (_Ul(0x3) << ADC_CTRLB_RESSEL_Pos) #define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) -#define ADC_CTRLB_RESSEL_12BIT_Val _U(0x0) /**< \brief (ADC_CTRLB) 12-bit result */ -#define ADC_CTRLB_RESSEL_16BIT_Val _U(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */ -#define ADC_CTRLB_RESSEL_10BIT_Val _U(0x2) /**< \brief (ADC_CTRLB) 10-bit result */ -#define ADC_CTRLB_RESSEL_8BIT_Val _U(0x3) /**< \brief (ADC_CTRLB) 8-bit result */ +#define ADC_CTRLB_RESSEL_12BIT_Val _Ul(0x0) /**< \brief (ADC_CTRLB) 12-bit result */ +#define ADC_CTRLB_RESSEL_16BIT_Val _Ul(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */ +#define ADC_CTRLB_RESSEL_10BIT_Val _Ul(0x2) /**< \brief (ADC_CTRLB) 10-bit result */ +#define ADC_CTRLB_RESSEL_8BIT_Val _Ul(0x3) /**< \brief (ADC_CTRLB) 8-bit result */ #define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) #define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) #define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) #define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) #define ADC_CTRLB_WINMODE_Pos 8 /**< \brief (ADC_CTRLB) Window Monitor Mode */ -#define ADC_CTRLB_WINMODE_Msk (_U(0x7) << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_Msk (_Ul(0x7) << ADC_CTRLB_WINMODE_Pos) #define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos)) -#define ADC_CTRLB_WINMODE_DISABLE_Val _U(0x0) /**< \brief (ADC_CTRLB) No window mode (default) */ -#define ADC_CTRLB_WINMODE_MODE1_Val _U(0x1) /**< \brief (ADC_CTRLB) RESULT > WINLT */ -#define ADC_CTRLB_WINMODE_MODE2_Val _U(0x2) /**< \brief (ADC_CTRLB) RESULT < WINUT */ -#define ADC_CTRLB_WINMODE_MODE3_Val _U(0x3) /**< \brief (ADC_CTRLB) WINLT < RESULT < WINUT */ -#define ADC_CTRLB_WINMODE_MODE4_Val _U(0x4) /**< \brief (ADC_CTRLB) !(WINLT < RESULT < WINUT) */ +#define ADC_CTRLB_WINMODE_DISABLE_Val _Ul(0x0) /**< \brief (ADC_CTRLB) No window mode (default) */ +#define ADC_CTRLB_WINMODE_MODE1_Val _Ul(0x1) /**< \brief (ADC_CTRLB) RESULT > WINLT */ +#define ADC_CTRLB_WINMODE_MODE2_Val _Ul(0x2) /**< \brief (ADC_CTRLB) RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE3_Val _Ul(0x3) /**< \brief (ADC_CTRLB) WINLT < RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE4_Val _Ul(0x4) /**< \brief (ADC_CTRLB) !(WINLT < RESULT < WINUT) */ #define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos) #define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos) #define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos) #define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos) #define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos) #define ADC_CTRLB_WINSS_Pos 11 /**< \brief (ADC_CTRLB) Window Single Sample */ -#define ADC_CTRLB_WINSS (_U(0x1) << ADC_CTRLB_WINSS_Pos) -#define ADC_CTRLB_MASK _U(0x0F1F) /**< \brief (ADC_CTRLB) MASK Register */ +#define ADC_CTRLB_WINSS (_Ul(0x1) << ADC_CTRLB_WINSS_Pos) +#define ADC_CTRLB_MASK _Ul(0x0F1F) /**< \brief (ADC_CTRLB) MASK Register */ /* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -330,17 +330,17 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_REFCTRL_OFFSET 0x08 /**< \brief (ADC_REFCTRL offset) Reference Control */ -#define ADC_REFCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ +#define ADC_REFCTRL_RESETVALUE _Ul(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ #define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ -#define ADC_REFCTRL_REFSEL_Msk (_U(0xF) << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_Msk (_Ul(0xF) << ADC_REFCTRL_REFSEL_Pos) #define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) -#define ADC_REFCTRL_REFSEL_INTREF_Val _U(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ -#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ -#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U(0x3) /**< \brief (ADC_REFCTRL) VDDANA */ -#define ADC_REFCTRL_REFSEL_AREFA_Val _U(0x4) /**< \brief (ADC_REFCTRL) External Reference */ -#define ADC_REFCTRL_REFSEL_AREFB_Val _U(0x5) /**< \brief (ADC_REFCTRL) External Reference */ -#define ADC_REFCTRL_REFSEL_AREFC_Val _U(0x6) /**< \brief (ADC_REFCTRL) External Reference (only on ADC1) */ +#define ADC_REFCTRL_REFSEL_INTREF_Val _Ul(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _Ul(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _Ul(0x3) /**< \brief (ADC_REFCTRL) VDDANA */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _Ul(0x4) /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_AREFB_Val _Ul(0x5) /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_AREFC_Val _Ul(0x6) /**< \brief (ADC_REFCTRL) External Reference (only on ADC1) */ #define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) #define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) #define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) @@ -348,8 +348,8 @@ typedef union { #define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) #define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos) #define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ -#define ADC_REFCTRL_REFCOMP (_U(0x1) << ADC_REFCTRL_REFCOMP_Pos) -#define ADC_REFCTRL_MASK _U(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ +#define ADC_REFCTRL_REFCOMP (_Ul(0x1) << ADC_REFCTRL_REFCOMP_Pos) +#define ADC_REFCTRL_MASK _Ul(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ /* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -364,22 +364,22 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_AVGCTRL_OFFSET 0x0A /**< \brief (ADC_AVGCTRL offset) Average Control */ -#define ADC_AVGCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ +#define ADC_AVGCTRL_RESETVALUE _Ul(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ #define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ -#define ADC_AVGCTRL_SAMPLENUM_Msk (_U(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_Msk (_Ul(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) #define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) -#define ADC_AVGCTRL_SAMPLENUM_1_Val _U(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ -#define ADC_AVGCTRL_SAMPLENUM_2_Val _U(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ -#define ADC_AVGCTRL_SAMPLENUM_4_Val _U(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ -#define ADC_AVGCTRL_SAMPLENUM_8_Val _U(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ -#define ADC_AVGCTRL_SAMPLENUM_16_Val _U(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ -#define ADC_AVGCTRL_SAMPLENUM_32_Val _U(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ -#define ADC_AVGCTRL_SAMPLENUM_64_Val _U(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ -#define ADC_AVGCTRL_SAMPLENUM_128_Val _U(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ -#define ADC_AVGCTRL_SAMPLENUM_256_Val _U(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ -#define ADC_AVGCTRL_SAMPLENUM_512_Val _U(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1_Val _Ul(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _Ul(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _Ul(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _Ul(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _Ul(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _Ul(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _Ul(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _Ul(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _Ul(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _Ul(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _Ul(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ #define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) #define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) #define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) @@ -392,9 +392,9 @@ typedef union { #define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) #define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) #define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ -#define ADC_AVGCTRL_ADJRES_Msk (_U(0x7) << ADC_AVGCTRL_ADJRES_Pos) +#define ADC_AVGCTRL_ADJRES_Msk (_Ul(0x7) << ADC_AVGCTRL_ADJRES_Pos) #define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) -#define ADC_AVGCTRL_MASK _U(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ +#define ADC_AVGCTRL_MASK _Ul(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ /* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -409,14 +409,14 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_SAMPCTRL_OFFSET 0x0B /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ -#define ADC_SAMPCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ +#define ADC_SAMPCTRL_RESETVALUE _Ul(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ #define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ -#define ADC_SAMPCTRL_SAMPLEN_Msk (_U(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) +#define ADC_SAMPCTRL_SAMPLEN_Msk (_Ul(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) #define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) #define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ -#define ADC_SAMPCTRL_OFFCOMP (_U(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) -#define ADC_SAMPCTRL_MASK _U(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */ +#define ADC_SAMPCTRL_OFFCOMP (_Ul(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) +#define ADC_SAMPCTRL_MASK _Ul(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */ /* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -429,12 +429,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_WINLT_OFFSET 0x0C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ -#define ADC_WINLT_RESETVALUE _U(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ +#define ADC_WINLT_RESETVALUE _Ul(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ #define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ -#define ADC_WINLT_WINLT_Msk (_U(0xFFFF) << ADC_WINLT_WINLT_Pos) +#define ADC_WINLT_WINLT_Msk (_Ul(0xFFFF) << ADC_WINLT_WINLT_Pos) #define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) -#define ADC_WINLT_MASK _U(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ +#define ADC_WINLT_MASK _Ul(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ /* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -447,12 +447,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_WINUT_OFFSET 0x0E /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ -#define ADC_WINUT_RESETVALUE _U(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ +#define ADC_WINUT_RESETVALUE _Ul(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ #define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ -#define ADC_WINUT_WINUT_Msk (_U(0xFFFF) << ADC_WINUT_WINUT_Pos) +#define ADC_WINUT_WINUT_Msk (_Ul(0xFFFF) << ADC_WINUT_WINUT_Pos) #define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) -#define ADC_WINUT_MASK _U(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ +#define ADC_WINUT_MASK _Ul(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ /* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -466,12 +466,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_GAINCORR_OFFSET 0x10 /**< \brief (ADC_GAINCORR offset) Gain Correction */ -#define ADC_GAINCORR_RESETVALUE _U(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ +#define ADC_GAINCORR_RESETVALUE _Ul(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ #define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ -#define ADC_GAINCORR_GAINCORR_Msk (_U(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) +#define ADC_GAINCORR_GAINCORR_Msk (_Ul(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) #define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) -#define ADC_GAINCORR_MASK _U(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ +#define ADC_GAINCORR_MASK _Ul(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ /* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -485,12 +485,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_OFFSETCORR_OFFSET 0x12 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ -#define ADC_OFFSETCORR_RESETVALUE _U(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ +#define ADC_OFFSETCORR_RESETVALUE _Ul(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ #define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ -#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_Ul(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) #define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) -#define ADC_OFFSETCORR_MASK _U(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ +#define ADC_OFFSETCORR_MASK _Ul(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ /* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -505,13 +505,13 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_SWTRIG_OFFSET 0x14 /**< \brief (ADC_SWTRIG offset) Software Trigger */ -#define ADC_SWTRIG_RESETVALUE _U(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ +#define ADC_SWTRIG_RESETVALUE _Ul(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ #define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ -#define ADC_SWTRIG_FLUSH (_U(0x1) << ADC_SWTRIG_FLUSH_Pos) +#define ADC_SWTRIG_FLUSH (_Ul(0x1) << ADC_SWTRIG_FLUSH_Pos) #define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ -#define ADC_SWTRIG_START (_U(0x1) << ADC_SWTRIG_START_Pos) -#define ADC_SWTRIG_MASK _U(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ +#define ADC_SWTRIG_START (_Ul(0x1) << ADC_SWTRIG_START_Pos) +#define ADC_SWTRIG_MASK _Ul(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ /* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -527,15 +527,15 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_INTENCLR_OFFSET 0x2C /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ -#define ADC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ +#define ADC_INTENCLR_RESETVALUE _Ul(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ #define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ -#define ADC_INTENCLR_RESRDY (_U(0x1) << ADC_INTENCLR_RESRDY_Pos) +#define ADC_INTENCLR_RESRDY (_Ul(0x1) << ADC_INTENCLR_RESRDY_Pos) #define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ -#define ADC_INTENCLR_OVERRUN (_U(0x1) << ADC_INTENCLR_OVERRUN_Pos) +#define ADC_INTENCLR_OVERRUN (_Ul(0x1) << ADC_INTENCLR_OVERRUN_Pos) #define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ -#define ADC_INTENCLR_WINMON (_U(0x1) << ADC_INTENCLR_WINMON_Pos) -#define ADC_INTENCLR_MASK _U(0x07) /**< \brief (ADC_INTENCLR) MASK Register */ +#define ADC_INTENCLR_WINMON (_Ul(0x1) << ADC_INTENCLR_WINMON_Pos) +#define ADC_INTENCLR_MASK _Ul(0x07) /**< \brief (ADC_INTENCLR) MASK Register */ /* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -551,15 +551,15 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_INTENSET_OFFSET 0x2D /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ -#define ADC_INTENSET_RESETVALUE _U(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ +#define ADC_INTENSET_RESETVALUE _Ul(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ #define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ -#define ADC_INTENSET_RESRDY (_U(0x1) << ADC_INTENSET_RESRDY_Pos) +#define ADC_INTENSET_RESRDY (_Ul(0x1) << ADC_INTENSET_RESRDY_Pos) #define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ -#define ADC_INTENSET_OVERRUN (_U(0x1) << ADC_INTENSET_OVERRUN_Pos) +#define ADC_INTENSET_OVERRUN (_Ul(0x1) << ADC_INTENSET_OVERRUN_Pos) #define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ -#define ADC_INTENSET_WINMON (_U(0x1) << ADC_INTENSET_WINMON_Pos) -#define ADC_INTENSET_MASK _U(0x07) /**< \brief (ADC_INTENSET) MASK Register */ +#define ADC_INTENSET_WINMON (_Ul(0x1) << ADC_INTENSET_WINMON_Pos) +#define ADC_INTENSET_MASK _Ul(0x07) /**< \brief (ADC_INTENSET) MASK Register */ /* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -575,15 +575,15 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_INTFLAG_OFFSET 0x2E /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define ADC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ +#define ADC_INTFLAG_RESETVALUE _Ul(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ #define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ -#define ADC_INTFLAG_RESRDY (_U(0x1) << ADC_INTFLAG_RESRDY_Pos) +#define ADC_INTFLAG_RESRDY (_Ul(0x1) << ADC_INTFLAG_RESRDY_Pos) #define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ -#define ADC_INTFLAG_OVERRUN (_U(0x1) << ADC_INTFLAG_OVERRUN_Pos) +#define ADC_INTFLAG_OVERRUN (_Ul(0x1) << ADC_INTFLAG_OVERRUN_Pos) #define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ -#define ADC_INTFLAG_WINMON (_U(0x1) << ADC_INTFLAG_WINMON_Pos) -#define ADC_INTFLAG_MASK _U(0x07) /**< \brief (ADC_INTFLAG) MASK Register */ +#define ADC_INTFLAG_WINMON (_Ul(0x1) << ADC_INTFLAG_WINMON_Pos) +#define ADC_INTFLAG_MASK _Ul(0x07) /**< \brief (ADC_INTFLAG) MASK Register */ /* -------- ADC_STATUS : (ADC Offset: 0x2F) (R/ 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -598,14 +598,14 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_STATUS_OFFSET 0x2F /**< \brief (ADC_STATUS offset) Status */ -#define ADC_STATUS_RESETVALUE _U(0x00) /**< \brief (ADC_STATUS reset_value) Status */ +#define ADC_STATUS_RESETVALUE _Ul(0x00) /**< \brief (ADC_STATUS reset_value) Status */ #define ADC_STATUS_ADCBUSY_Pos 0 /**< \brief (ADC_STATUS) ADC Busy Status */ -#define ADC_STATUS_ADCBUSY (_U(0x1) << ADC_STATUS_ADCBUSY_Pos) +#define ADC_STATUS_ADCBUSY (_Ul(0x1) << ADC_STATUS_ADCBUSY_Pos) #define ADC_STATUS_WCC_Pos 2 /**< \brief (ADC_STATUS) Window Comparator Counter */ -#define ADC_STATUS_WCC_Msk (_U(0x3F) << ADC_STATUS_WCC_Pos) +#define ADC_STATUS_WCC_Msk (_Ul(0x3F) << ADC_STATUS_WCC_Pos) #define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos)) -#define ADC_STATUS_MASK _U(0xFD) /**< \brief (ADC_STATUS) MASK Register */ +#define ADC_STATUS_MASK _Ul(0xFD) /**< \brief (ADC_STATUS) MASK Register */ /* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) (R/ 32) Synchronization Busy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -630,33 +630,33 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_SYNCBUSY_OFFSET 0x30 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ -#define ADC_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ +#define ADC_SYNCBUSY_RESETVALUE _Ul(0x00000000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ #define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ -#define ADC_SYNCBUSY_SWRST (_U(0x1) << ADC_SYNCBUSY_SWRST_Pos) +#define ADC_SYNCBUSY_SWRST (_Ul(0x1) << ADC_SYNCBUSY_SWRST_Pos) #define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ -#define ADC_SYNCBUSY_ENABLE (_U(0x1) << ADC_SYNCBUSY_ENABLE_Pos) +#define ADC_SYNCBUSY_ENABLE (_Ul(0x1) << ADC_SYNCBUSY_ENABLE_Pos) #define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) Input Control Synchronization Busy */ -#define ADC_SYNCBUSY_INPUTCTRL (_U(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) +#define ADC_SYNCBUSY_INPUTCTRL (_Ul(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) #define ADC_SYNCBUSY_CTRLB_Pos 3 /**< \brief (ADC_SYNCBUSY) Control B Synchronization Busy */ -#define ADC_SYNCBUSY_CTRLB (_U(0x1) << ADC_SYNCBUSY_CTRLB_Pos) +#define ADC_SYNCBUSY_CTRLB (_Ul(0x1) << ADC_SYNCBUSY_CTRLB_Pos) #define ADC_SYNCBUSY_REFCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) Reference Control Synchronization Busy */ -#define ADC_SYNCBUSY_REFCTRL (_U(0x1) << ADC_SYNCBUSY_REFCTRL_Pos) +#define ADC_SYNCBUSY_REFCTRL (_Ul(0x1) << ADC_SYNCBUSY_REFCTRL_Pos) #define ADC_SYNCBUSY_AVGCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) Average Control Synchronization Busy */ -#define ADC_SYNCBUSY_AVGCTRL (_U(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) +#define ADC_SYNCBUSY_AVGCTRL (_Ul(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) #define ADC_SYNCBUSY_SAMPCTRL_Pos 6 /**< \brief (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy */ -#define ADC_SYNCBUSY_SAMPCTRL (_U(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) +#define ADC_SYNCBUSY_SAMPCTRL (_Ul(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) #define ADC_SYNCBUSY_WINLT_Pos 7 /**< \brief (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy */ -#define ADC_SYNCBUSY_WINLT (_U(0x1) << ADC_SYNCBUSY_WINLT_Pos) +#define ADC_SYNCBUSY_WINLT (_Ul(0x1) << ADC_SYNCBUSY_WINLT_Pos) #define ADC_SYNCBUSY_WINUT_Pos 8 /**< \brief (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy */ -#define ADC_SYNCBUSY_WINUT (_U(0x1) << ADC_SYNCBUSY_WINUT_Pos) +#define ADC_SYNCBUSY_WINUT (_Ul(0x1) << ADC_SYNCBUSY_WINUT_Pos) #define ADC_SYNCBUSY_GAINCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) Gain Correction Synchronization Busy */ -#define ADC_SYNCBUSY_GAINCORR (_U(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) +#define ADC_SYNCBUSY_GAINCORR (_Ul(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) #define ADC_SYNCBUSY_OFFSETCORR_Pos 10 /**< \brief (ADC_SYNCBUSY) Offset Correction Synchronization Busy */ -#define ADC_SYNCBUSY_OFFSETCORR (_U(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) +#define ADC_SYNCBUSY_OFFSETCORR (_Ul(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) #define ADC_SYNCBUSY_SWTRIG_Pos 11 /**< \brief (ADC_SYNCBUSY) Software Trigger Synchronization Busy */ -#define ADC_SYNCBUSY_SWTRIG (_U(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) -#define ADC_SYNCBUSY_MASK _U(0x00000FFF) /**< \brief (ADC_SYNCBUSY) MASK Register */ +#define ADC_SYNCBUSY_SWTRIG (_Ul(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) +#define ADC_SYNCBUSY_MASK _Ul(0x00000FFF) /**< \brief (ADC_SYNCBUSY) MASK Register */ /* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -669,12 +669,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_DSEQDATA_OFFSET 0x34 /**< \brief (ADC_DSEQDATA offset) DMA Sequencial Data */ -#define ADC_DSEQDATA_RESETVALUE _U(0x00000000) /**< \brief (ADC_DSEQDATA reset_value) DMA Sequencial Data */ +#define ADC_DSEQDATA_RESETVALUE _Ul(0x00000000) /**< \brief (ADC_DSEQDATA reset_value) DMA Sequencial Data */ #define ADC_DSEQDATA_DATA_Pos 0 /**< \brief (ADC_DSEQDATA) DMA Sequential Data */ -#define ADC_DSEQDATA_DATA_Msk (_U(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos) +#define ADC_DSEQDATA_DATA_Msk (_Ul(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos) #define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos)) -#define ADC_DSEQDATA_MASK _U(0xFFFFFFFF) /**< \brief (ADC_DSEQDATA) MASK Register */ +#define ADC_DSEQDATA_MASK _Ul(0xFFFFFFFF) /**< \brief (ADC_DSEQDATA) MASK Register */ /* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -697,29 +697,29 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_DSEQCTRL_OFFSET 0x38 /**< \brief (ADC_DSEQCTRL offset) DMA Sequential Control */ -#define ADC_DSEQCTRL_RESETVALUE _U(0x00000000) /**< \brief (ADC_DSEQCTRL reset_value) DMA Sequential Control */ +#define ADC_DSEQCTRL_RESETVALUE _Ul(0x00000000) /**< \brief (ADC_DSEQCTRL reset_value) DMA Sequential Control */ #define ADC_DSEQCTRL_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQCTRL) Input Control */ -#define ADC_DSEQCTRL_INPUTCTRL (_U(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos) +#define ADC_DSEQCTRL_INPUTCTRL (_Ul(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos) #define ADC_DSEQCTRL_CTRLB_Pos 1 /**< \brief (ADC_DSEQCTRL) Control B */ -#define ADC_DSEQCTRL_CTRLB (_U(0x1) << ADC_DSEQCTRL_CTRLB_Pos) +#define ADC_DSEQCTRL_CTRLB (_Ul(0x1) << ADC_DSEQCTRL_CTRLB_Pos) #define ADC_DSEQCTRL_REFCTRL_Pos 2 /**< \brief (ADC_DSEQCTRL) Reference Control */ -#define ADC_DSEQCTRL_REFCTRL (_U(0x1) << ADC_DSEQCTRL_REFCTRL_Pos) +#define ADC_DSEQCTRL_REFCTRL (_Ul(0x1) << ADC_DSEQCTRL_REFCTRL_Pos) #define ADC_DSEQCTRL_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQCTRL) Average Control */ -#define ADC_DSEQCTRL_AVGCTRL (_U(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos) +#define ADC_DSEQCTRL_AVGCTRL (_Ul(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos) #define ADC_DSEQCTRL_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQCTRL) Sampling Time Control */ -#define ADC_DSEQCTRL_SAMPCTRL (_U(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos) +#define ADC_DSEQCTRL_SAMPCTRL (_Ul(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos) #define ADC_DSEQCTRL_WINLT_Pos 5 /**< \brief (ADC_DSEQCTRL) Window Monitor Lower Threshold */ -#define ADC_DSEQCTRL_WINLT (_U(0x1) << ADC_DSEQCTRL_WINLT_Pos) +#define ADC_DSEQCTRL_WINLT (_Ul(0x1) << ADC_DSEQCTRL_WINLT_Pos) #define ADC_DSEQCTRL_WINUT_Pos 6 /**< \brief (ADC_DSEQCTRL) Window Monitor Upper Threshold */ -#define ADC_DSEQCTRL_WINUT (_U(0x1) << ADC_DSEQCTRL_WINUT_Pos) +#define ADC_DSEQCTRL_WINUT (_Ul(0x1) << ADC_DSEQCTRL_WINUT_Pos) #define ADC_DSEQCTRL_GAINCORR_Pos 7 /**< \brief (ADC_DSEQCTRL) Gain Correction */ -#define ADC_DSEQCTRL_GAINCORR (_U(0x1) << ADC_DSEQCTRL_GAINCORR_Pos) +#define ADC_DSEQCTRL_GAINCORR (_Ul(0x1) << ADC_DSEQCTRL_GAINCORR_Pos) #define ADC_DSEQCTRL_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQCTRL) Offset Correction */ -#define ADC_DSEQCTRL_OFFSETCORR (_U(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos) +#define ADC_DSEQCTRL_OFFSETCORR (_Ul(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos) #define ADC_DSEQCTRL_AUTOSTART_Pos 31 /**< \brief (ADC_DSEQCTRL) ADC Auto-Start Conversion */ -#define ADC_DSEQCTRL_AUTOSTART (_U(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos) -#define ADC_DSEQCTRL_MASK _U(0x800001FF) /**< \brief (ADC_DSEQCTRL) MASK Register */ +#define ADC_DSEQCTRL_AUTOSTART (_Ul(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos) +#define ADC_DSEQCTRL_MASK _Ul(0x800001FF) /**< \brief (ADC_DSEQCTRL) MASK Register */ /* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) (R/ 32) DMA Sequencial Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -742,29 +742,29 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_DSEQSTAT_OFFSET 0x3C /**< \brief (ADC_DSEQSTAT offset) DMA Sequencial Status */ -#define ADC_DSEQSTAT_RESETVALUE _U(0x00000000) /**< \brief (ADC_DSEQSTAT reset_value) DMA Sequencial Status */ +#define ADC_DSEQSTAT_RESETVALUE _Ul(0x00000000) /**< \brief (ADC_DSEQSTAT reset_value) DMA Sequencial Status */ #define ADC_DSEQSTAT_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQSTAT) Input Control */ -#define ADC_DSEQSTAT_INPUTCTRL (_U(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos) +#define ADC_DSEQSTAT_INPUTCTRL (_Ul(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos) #define ADC_DSEQSTAT_CTRLB_Pos 1 /**< \brief (ADC_DSEQSTAT) Control B */ -#define ADC_DSEQSTAT_CTRLB (_U(0x1) << ADC_DSEQSTAT_CTRLB_Pos) +#define ADC_DSEQSTAT_CTRLB (_Ul(0x1) << ADC_DSEQSTAT_CTRLB_Pos) #define ADC_DSEQSTAT_REFCTRL_Pos 2 /**< \brief (ADC_DSEQSTAT) Reference Control */ -#define ADC_DSEQSTAT_REFCTRL (_U(0x1) << ADC_DSEQSTAT_REFCTRL_Pos) +#define ADC_DSEQSTAT_REFCTRL (_Ul(0x1) << ADC_DSEQSTAT_REFCTRL_Pos) #define ADC_DSEQSTAT_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQSTAT) Average Control */ -#define ADC_DSEQSTAT_AVGCTRL (_U(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos) +#define ADC_DSEQSTAT_AVGCTRL (_Ul(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos) #define ADC_DSEQSTAT_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQSTAT) Sampling Time Control */ -#define ADC_DSEQSTAT_SAMPCTRL (_U(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos) +#define ADC_DSEQSTAT_SAMPCTRL (_Ul(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos) #define ADC_DSEQSTAT_WINLT_Pos 5 /**< \brief (ADC_DSEQSTAT) Window Monitor Lower Threshold */ -#define ADC_DSEQSTAT_WINLT (_U(0x1) << ADC_DSEQSTAT_WINLT_Pos) +#define ADC_DSEQSTAT_WINLT (_Ul(0x1) << ADC_DSEQSTAT_WINLT_Pos) #define ADC_DSEQSTAT_WINUT_Pos 6 /**< \brief (ADC_DSEQSTAT) Window Monitor Upper Threshold */ -#define ADC_DSEQSTAT_WINUT (_U(0x1) << ADC_DSEQSTAT_WINUT_Pos) +#define ADC_DSEQSTAT_WINUT (_Ul(0x1) << ADC_DSEQSTAT_WINUT_Pos) #define ADC_DSEQSTAT_GAINCORR_Pos 7 /**< \brief (ADC_DSEQSTAT) Gain Correction */ -#define ADC_DSEQSTAT_GAINCORR (_U(0x1) << ADC_DSEQSTAT_GAINCORR_Pos) +#define ADC_DSEQSTAT_GAINCORR (_Ul(0x1) << ADC_DSEQSTAT_GAINCORR_Pos) #define ADC_DSEQSTAT_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQSTAT) Offset Correction */ -#define ADC_DSEQSTAT_OFFSETCORR (_U(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos) +#define ADC_DSEQSTAT_OFFSETCORR (_Ul(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos) #define ADC_DSEQSTAT_BUSY_Pos 31 /**< \brief (ADC_DSEQSTAT) DMA Sequencing Busy */ -#define ADC_DSEQSTAT_BUSY (_U(0x1) << ADC_DSEQSTAT_BUSY_Pos) -#define ADC_DSEQSTAT_MASK _U(0x800001FF) /**< \brief (ADC_DSEQSTAT) MASK Register */ +#define ADC_DSEQSTAT_BUSY (_Ul(0x1) << ADC_DSEQSTAT_BUSY_Pos) +#define ADC_DSEQSTAT_MASK _Ul(0x800001FF) /**< \brief (ADC_DSEQSTAT) MASK Register */ /* -------- ADC_RESULT : (ADC Offset: 0x40) (R/ 16) Result Conversion Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -777,12 +777,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_RESULT_OFFSET 0x40 /**< \brief (ADC_RESULT offset) Result Conversion Value */ -#define ADC_RESULT_RESETVALUE _U(0x0000) /**< \brief (ADC_RESULT reset_value) Result Conversion Value */ +#define ADC_RESULT_RESETVALUE _Ul(0x0000) /**< \brief (ADC_RESULT reset_value) Result Conversion Value */ #define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ -#define ADC_RESULT_RESULT_Msk (_U(0xFFFF) << ADC_RESULT_RESULT_Pos) +#define ADC_RESULT_RESULT_Msk (_Ul(0xFFFF) << ADC_RESULT_RESULT_Pos) #define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) -#define ADC_RESULT_MASK _U(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ +#define ADC_RESULT_MASK _Ul(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ /* -------- ADC_RESS : (ADC Offset: 0x44) (R/ 16) Last Sample Result -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -795,12 +795,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_RESS_OFFSET 0x44 /**< \brief (ADC_RESS offset) Last Sample Result */ -#define ADC_RESS_RESETVALUE _U(0x0000) /**< \brief (ADC_RESS reset_value) Last Sample Result */ +#define ADC_RESS_RESETVALUE _Ul(0x0000) /**< \brief (ADC_RESS reset_value) Last Sample Result */ #define ADC_RESS_RESS_Pos 0 /**< \brief (ADC_RESS) Last ADC conversion result */ -#define ADC_RESS_RESS_Msk (_U(0xFFFF) << ADC_RESS_RESS_Pos) +#define ADC_RESS_RESS_Msk (_Ul(0xFFFF) << ADC_RESS_RESS_Pos) #define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos)) -#define ADC_RESS_MASK _U(0xFFFF) /**< \brief (ADC_RESS) MASK Register */ +#define ADC_RESS_MASK _Ul(0xFFFF) /**< \brief (ADC_RESS) MASK Register */ /* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -818,18 +818,18 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define ADC_CALIB_OFFSET 0x48 /**< \brief (ADC_CALIB offset) Calibration */ -#define ADC_CALIB_RESETVALUE _U(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ +#define ADC_CALIB_RESETVALUE _Ul(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ #define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ -#define ADC_CALIB_BIASCOMP_Msk (_U(0x7) << ADC_CALIB_BIASCOMP_Pos) +#define ADC_CALIB_BIASCOMP_Msk (_Ul(0x7) << ADC_CALIB_BIASCOMP_Pos) #define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) #define ADC_CALIB_BIASR2R_Pos 4 /**< \brief (ADC_CALIB) Bias R2R Ampli scaling */ -#define ADC_CALIB_BIASR2R_Msk (_U(0x7) << ADC_CALIB_BIASR2R_Pos) +#define ADC_CALIB_BIASR2R_Msk (_Ul(0x7) << ADC_CALIB_BIASR2R_Pos) #define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos)) #define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ -#define ADC_CALIB_BIASREFBUF_Msk (_U(0x7) << ADC_CALIB_BIASREFBUF_Pos) +#define ADC_CALIB_BIASREFBUF_Msk (_Ul(0x7) << ADC_CALIB_BIASREFBUF_Pos) #define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) -#define ADC_CALIB_MASK _U(0x0777) /**< \brief (ADC_CALIB) MASK Register */ +#define ADC_CALIB_MASK _Ul(0x0777) /**< \brief (ADC_CALIB) MASK Register */ /** \brief ADC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) diff --git a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/aes.h b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/aes.h index e1fb06b..1e5cf75 100644 --- a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/aes.h +++ b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/aes.h @@ -61,22 +61,22 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ -#define AES_CTRLA_RESETVALUE _U(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */ +#define AES_CTRLA_RESETVALUE _Ul(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */ #define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ -#define AES_CTRLA_SWRST (_U(0x1) << AES_CTRLA_SWRST_Pos) +#define AES_CTRLA_SWRST (_Ul(0x1) << AES_CTRLA_SWRST_Pos) #define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ -#define AES_CTRLA_ENABLE (_U(0x1) << AES_CTRLA_ENABLE_Pos) +#define AES_CTRLA_ENABLE (_Ul(0x1) << AES_CTRLA_ENABLE_Pos) #define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ -#define AES_CTRLA_AESMODE_Msk (_U(0x7) << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_Msk (_Ul(0x7) << AES_CTRLA_AESMODE_Pos) #define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) -#define AES_CTRLA_AESMODE_ECB_Val _U(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */ -#define AES_CTRLA_AESMODE_CBC_Val _U(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */ -#define AES_CTRLA_AESMODE_OFB_Val _U(0x2) /**< \brief (AES_CTRLA) Output feedback mode */ -#define AES_CTRLA_AESMODE_CFB_Val _U(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */ -#define AES_CTRLA_AESMODE_COUNTER_Val _U(0x4) /**< \brief (AES_CTRLA) Counter mode */ -#define AES_CTRLA_AESMODE_CCM_Val _U(0x5) /**< \brief (AES_CTRLA) CCM mode */ -#define AES_CTRLA_AESMODE_GCM_Val _U(0x6) /**< \brief (AES_CTRLA) Galois counter mode */ +#define AES_CTRLA_AESMODE_ECB_Val _Ul(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */ +#define AES_CTRLA_AESMODE_CBC_Val _Ul(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */ +#define AES_CTRLA_AESMODE_OFB_Val _Ul(0x2) /**< \brief (AES_CTRLA) Output feedback mode */ +#define AES_CTRLA_AESMODE_CFB_Val _Ul(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */ +#define AES_CTRLA_AESMODE_COUNTER_Val _Ul(0x4) /**< \brief (AES_CTRLA) Counter mode */ +#define AES_CTRLA_AESMODE_CCM_Val _Ul(0x5) /**< \brief (AES_CTRLA) CCM mode */ +#define AES_CTRLA_AESMODE_GCM_Val _Ul(0x6) /**< \brief (AES_CTRLA) Galois counter mode */ #define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos) #define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos) #define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos) @@ -85,61 +85,61 @@ typedef union { #define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos) #define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos) #define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */ -#define AES_CTRLA_CFBS_Msk (_U(0x7) << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_Msk (_Ul(0x7) << AES_CTRLA_CFBS_Pos) #define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) -#define AES_CTRLA_CFBS_128BIT_Val _U(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_64BIT_Val _U(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_32BIT_Val _U(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_16BIT_Val _U(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_8BIT_Val _U(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_128BIT_Val _Ul(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_64BIT_Val _Ul(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_32BIT_Val _Ul(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_16BIT_Val _Ul(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_8BIT_Val _Ul(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ #define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos) #define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos) #define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos) #define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos) #define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos) #define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */ -#define AES_CTRLA_KEYSIZE_Msk (_U(0x3) << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE_Msk (_Ul(0x3) << AES_CTRLA_KEYSIZE_Pos) #define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) -#define AES_CTRLA_KEYSIZE_128BIT_Val _U(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */ -#define AES_CTRLA_KEYSIZE_192BIT_Val _U(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */ -#define AES_CTRLA_KEYSIZE_256BIT_Val _U(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_128BIT_Val _Ul(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_192BIT_Val _Ul(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_256BIT_Val _Ul(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */ #define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos) #define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos) #define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos) #define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */ -#define AES_CTRLA_CIPHER (_U(0x1) << AES_CTRLA_CIPHER_Pos) -#define AES_CTRLA_CIPHER_DEC_Val _U(0x0) /**< \brief (AES_CTRLA) Decryption */ -#define AES_CTRLA_CIPHER_ENC_Val _U(0x1) /**< \brief (AES_CTRLA) Encryption */ +#define AES_CTRLA_CIPHER (_Ul(0x1) << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_CIPHER_DEC_Val _Ul(0x0) /**< \brief (AES_CTRLA) Decryption */ +#define AES_CTRLA_CIPHER_ENC_Val _Ul(0x1) /**< \brief (AES_CTRLA) Encryption */ #define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos) #define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos) #define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */ -#define AES_CTRLA_STARTMODE (_U(0x1) << AES_CTRLA_STARTMODE_Pos) -#define AES_CTRLA_STARTMODE_MANUAL_Val _U(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */ -#define AES_CTRLA_STARTMODE_AUTO_Val _U(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */ +#define AES_CTRLA_STARTMODE (_Ul(0x1) << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_STARTMODE_MANUAL_Val _Ul(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */ +#define AES_CTRLA_STARTMODE_AUTO_Val _Ul(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */ #define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos) #define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos) #define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */ -#define AES_CTRLA_LOD (_U(0x1) << AES_CTRLA_LOD_Pos) -#define AES_CTRLA_LOD_NONE_Val _U(0x0) /**< \brief (AES_CTRLA) No effect */ -#define AES_CTRLA_LOD_LAST_Val _U(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */ +#define AES_CTRLA_LOD (_Ul(0x1) << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_LOD_NONE_Val _Ul(0x0) /**< \brief (AES_CTRLA) No effect */ +#define AES_CTRLA_LOD_LAST_Val _Ul(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */ #define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos) #define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos) #define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */ -#define AES_CTRLA_KEYGEN (_U(0x1) << AES_CTRLA_KEYGEN_Pos) -#define AES_CTRLA_KEYGEN_NONE_Val _U(0x0) /**< \brief (AES_CTRLA) No effect */ -#define AES_CTRLA_KEYGEN_LAST_Val _U(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */ +#define AES_CTRLA_KEYGEN (_Ul(0x1) << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_KEYGEN_NONE_Val _Ul(0x0) /**< \brief (AES_CTRLA) No effect */ +#define AES_CTRLA_KEYGEN_LAST_Val _Ul(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */ #define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos) #define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos) #define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */ -#define AES_CTRLA_XORKEY (_U(0x1) << AES_CTRLA_XORKEY_Pos) -#define AES_CTRLA_XORKEY_NONE_Val _U(0x0) /**< \brief (AES_CTRLA) No effect */ -#define AES_CTRLA_XORKEY_XOR_Val _U(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */ +#define AES_CTRLA_XORKEY (_Ul(0x1) << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_XORKEY_NONE_Val _Ul(0x0) /**< \brief (AES_CTRLA) No effect */ +#define AES_CTRLA_XORKEY_XOR_Val _Ul(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */ #define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos) #define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos) #define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */ -#define AES_CTRLA_CTYPE_Msk (_U(0xF) << AES_CTRLA_CTYPE_Pos) +#define AES_CTRLA_CTYPE_Msk (_Ul(0xF) << AES_CTRLA_CTYPE_Pos) #define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) -#define AES_CTRLA_MASK _U(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */ +#define AES_CTRLA_MASK _Ul(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */ /* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -156,17 +156,17 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ -#define AES_CTRLB_RESETVALUE _U(0x00) /**< \brief (AES_CTRLB reset_value) Control B */ +#define AES_CTRLB_RESETVALUE _Ul(0x00) /**< \brief (AES_CTRLB reset_value) Control B */ #define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */ -#define AES_CTRLB_START (_U(0x1) << AES_CTRLB_START_Pos) +#define AES_CTRLB_START (_Ul(0x1) << AES_CTRLB_START_Pos) #define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ -#define AES_CTRLB_NEWMSG (_U(0x1) << AES_CTRLB_NEWMSG_Pos) +#define AES_CTRLB_NEWMSG (_Ul(0x1) << AES_CTRLB_NEWMSG_Pos) #define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ -#define AES_CTRLB_EOM (_U(0x1) << AES_CTRLB_EOM_Pos) +#define AES_CTRLB_EOM (_Ul(0x1) << AES_CTRLB_EOM_Pos) #define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ -#define AES_CTRLB_GFMUL (_U(0x1) << AES_CTRLB_GFMUL_Pos) -#define AES_CTRLB_MASK _U(0x0F) /**< \brief (AES_CTRLB) MASK Register */ +#define AES_CTRLB_GFMUL (_Ul(0x1) << AES_CTRLB_GFMUL_Pos) +#define AES_CTRLB_MASK _Ul(0x0F) /**< \brief (AES_CTRLB) MASK Register */ /* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -181,13 +181,13 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ -#define AES_INTENCLR_RESETVALUE _U(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ +#define AES_INTENCLR_RESETVALUE _Ul(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ #define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */ -#define AES_INTENCLR_ENCCMP (_U(0x1) << AES_INTENCLR_ENCCMP_Pos) +#define AES_INTENCLR_ENCCMP (_Ul(0x1) << AES_INTENCLR_ENCCMP_Pos) #define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */ -#define AES_INTENCLR_GFMCMP (_U(0x1) << AES_INTENCLR_GFMCMP_Pos) -#define AES_INTENCLR_MASK _U(0x03) /**< \brief (AES_INTENCLR) MASK Register */ +#define AES_INTENCLR_GFMCMP (_Ul(0x1) << AES_INTENCLR_GFMCMP_Pos) +#define AES_INTENCLR_MASK _Ul(0x03) /**< \brief (AES_INTENCLR) MASK Register */ /* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -202,13 +202,13 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ -#define AES_INTENSET_RESETVALUE _U(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ +#define AES_INTENSET_RESETVALUE _Ul(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ #define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */ -#define AES_INTENSET_ENCCMP (_U(0x1) << AES_INTENSET_ENCCMP_Pos) +#define AES_INTENSET_ENCCMP (_Ul(0x1) << AES_INTENSET_ENCCMP_Pos) #define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */ -#define AES_INTENSET_GFMCMP (_U(0x1) << AES_INTENSET_GFMCMP_Pos) -#define AES_INTENSET_MASK _U(0x03) /**< \brief (AES_INTENSET) MASK Register */ +#define AES_INTENSET_GFMCMP (_Ul(0x1) << AES_INTENSET_GFMCMP_Pos) +#define AES_INTENSET_MASK _Ul(0x03) /**< \brief (AES_INTENSET) MASK Register */ /* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -223,13 +223,13 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ -#define AES_INTFLAG_RESETVALUE _U(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ +#define AES_INTFLAG_RESETVALUE _Ul(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ #define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ -#define AES_INTFLAG_ENCCMP (_U(0x1) << AES_INTFLAG_ENCCMP_Pos) +#define AES_INTFLAG_ENCCMP (_Ul(0x1) << AES_INTFLAG_ENCCMP_Pos) #define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ -#define AES_INTFLAG_GFMCMP (_U(0x1) << AES_INTFLAG_GFMCMP_Pos) -#define AES_INTFLAG_MASK _U(0x03) /**< \brief (AES_INTFLAG) MASK Register */ +#define AES_INTFLAG_GFMCMP (_Ul(0x1) << AES_INTFLAG_GFMCMP_Pos) +#define AES_INTFLAG_MASK _Ul(0x03) /**< \brief (AES_INTFLAG) MASK Register */ /* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -243,12 +243,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ -#define AES_DATABUFPTR_RESETVALUE _U(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ +#define AES_DATABUFPTR_RESETVALUE _Ul(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ #define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ -#define AES_DATABUFPTR_INDATAPTR_Msk (_U(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) +#define AES_DATABUFPTR_INDATAPTR_Msk (_Ul(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) #define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) -#define AES_DATABUFPTR_MASK _U(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */ +#define AES_DATABUFPTR_MASK _Ul(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */ /* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -262,11 +262,11 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ -#define AES_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */ +#define AES_DBGCTRL_RESETVALUE _Ul(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */ #define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ -#define AES_DBGCTRL_DBGRUN (_U(0x1) << AES_DBGCTRL_DBGRUN_Pos) -#define AES_DBGCTRL_MASK _U(0x01) /**< \brief (AES_DBGCTRL) MASK Register */ +#define AES_DBGCTRL_DBGRUN (_Ul(0x1) << AES_DBGCTRL_DBGRUN_Pos) +#define AES_DBGCTRL_MASK _Ul(0x01) /**< \brief (AES_DBGCTRL) MASK Register */ /* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -276,8 +276,8 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ -#define AES_KEYWORD_RESETVALUE _U(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */ -#define AES_KEYWORD_MASK _U(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */ +#define AES_KEYWORD_RESETVALUE _Ul(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */ +#define AES_KEYWORD_MASK _Ul(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */ /* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -287,8 +287,8 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ -#define AES_INDATA_RESETVALUE _U(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */ -#define AES_INDATA_MASK _U(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */ +#define AES_INDATA_RESETVALUE _Ul(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */ +#define AES_INDATA_MASK _Ul(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */ /* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -298,8 +298,8 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ -#define AES_INTVECTV_RESETVALUE _U(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ -#define AES_INTVECTV_MASK _U(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */ +#define AES_INTVECTV_RESETVALUE _Ul(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ +#define AES_INTVECTV_MASK _Ul(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */ /* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -309,8 +309,8 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ -#define AES_HASHKEY_RESETVALUE _U(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */ -#define AES_HASHKEY_MASK _U(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */ +#define AES_HASHKEY_RESETVALUE _Ul(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */ +#define AES_HASHKEY_MASK _Ul(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */ /* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -320,8 +320,8 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ -#define AES_GHASH_RESETVALUE _U(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */ -#define AES_GHASH_MASK _U(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */ +#define AES_GHASH_RESETVALUE _Ul(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */ +#define AES_GHASH_MASK _Ul(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */ /* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -331,8 +331,8 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ -#define AES_CIPLEN_RESETVALUE _U(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */ -#define AES_CIPLEN_MASK _U(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */ +#define AES_CIPLEN_RESETVALUE _Ul(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */ +#define AES_CIPLEN_MASK _Ul(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */ /* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -342,8 +342,8 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ -#define AES_RANDSEED_RESETVALUE _U(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */ -#define AES_RANDSEED_MASK _U(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */ +#define AES_RANDSEED_RESETVALUE _Ul(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */ +#define AES_RANDSEED_MASK _Ul(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */ /** \brief AES hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) diff --git a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/ccl.h b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/ccl.h index 891c5ec..0e2ff28 100644 --- a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/ccl.h +++ b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/ccl.h @@ -53,15 +53,15 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ -#define CCL_CTRL_RESETVALUE _U(0x00) /**< \brief (CCL_CTRL reset_value) Control */ +#define CCL_CTRL_RESETVALUE _Ul(0x00) /**< \brief (CCL_CTRL reset_value) Control */ #define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ -#define CCL_CTRL_SWRST (_U(0x1) << CCL_CTRL_SWRST_Pos) +#define CCL_CTRL_SWRST (_Ul(0x1) << CCL_CTRL_SWRST_Pos) #define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ -#define CCL_CTRL_ENABLE (_U(0x1) << CCL_CTRL_ENABLE_Pos) +#define CCL_CTRL_ENABLE (_Ul(0x1) << CCL_CTRL_ENABLE_Pos) #define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run in Standby */ -#define CCL_CTRL_RUNSTDBY (_U(0x1) << CCL_CTRL_RUNSTDBY_Pos) -#define CCL_CTRL_MASK _U(0x43) /**< \brief (CCL_CTRL) MASK Register */ +#define CCL_CTRL_RUNSTDBY (_Ul(0x1) << CCL_CTRL_RUNSTDBY_Pos) +#define CCL_CTRL_MASK _Ul(0x43) /**< \brief (CCL_CTRL) MASK Register */ /* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -75,22 +75,22 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ -#define CCL_SEQCTRL_RESETVALUE _U(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ +#define CCL_SEQCTRL_RESETVALUE _Ul(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ #define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ -#define CCL_SEQCTRL_SEQSEL_Msk (_U(0xF) << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_Msk (_Ul(0xF) << CCL_SEQCTRL_SEQSEL_Pos) #define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) -#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ -#define CCL_SEQCTRL_SEQSEL_DFF_Val _U(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */ -#define CCL_SEQCTRL_SEQSEL_JK_Val _U(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */ -#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U(0x3) /**< \brief (CCL_SEQCTRL) D latch */ -#define CCL_SEQCTRL_SEQSEL_RS_Val _U(0x4) /**< \brief (CCL_SEQCTRL) RS latch */ +#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _Ul(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ +#define CCL_SEQCTRL_SEQSEL_DFF_Val _Ul(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */ +#define CCL_SEQCTRL_SEQSEL_JK_Val _Ul(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */ +#define CCL_SEQCTRL_SEQSEL_LATCH_Val _Ul(0x3) /**< \brief (CCL_SEQCTRL) D latch */ +#define CCL_SEQCTRL_SEQSEL_RS_Val _Ul(0x4) /**< \brief (CCL_SEQCTRL) RS latch */ #define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) #define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) #define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) #define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) #define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_MASK _U(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */ +#define CCL_SEQCTRL_MASK _Ul(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */ /* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -116,34 +116,34 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ -#define CCL_LUTCTRL_RESETVALUE _U(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ +#define CCL_LUTCTRL_RESETVALUE _Ul(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ #define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ -#define CCL_LUTCTRL_ENABLE (_U(0x1) << CCL_LUTCTRL_ENABLE_Pos) +#define CCL_LUTCTRL_ENABLE (_Ul(0x1) << CCL_LUTCTRL_ENABLE_Pos) #define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ -#define CCL_LUTCTRL_FILTSEL_Msk (_U(0x3) << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_Msk (_Ul(0x3) << CCL_LUTCTRL_FILTSEL_Pos) #define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) -#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */ -#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ -#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */ +#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _Ul(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */ +#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _Ul(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ +#define CCL_LUTCTRL_FILTSEL_FILTER_Val _Ul(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */ #define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) #define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) #define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) #define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ -#define CCL_LUTCTRL_EDGESEL (_U(0x1) << CCL_LUTCTRL_EDGESEL_Pos) +#define CCL_LUTCTRL_EDGESEL (_Ul(0x1) << CCL_LUTCTRL_EDGESEL_Pos) #define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ -#define CCL_LUTCTRL_INSEL0_Msk (_U(0xF) << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_Msk (_Ul(0xF) << CCL_LUTCTRL_INSEL0_Pos) #define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) -#define CCL_LUTCTRL_INSEL0_MASK_Val _U(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL0_LINK_Val _U(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL0_EVENT_Val _U(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL0_IO_Val _U(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL0_AC_Val _U(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL0_TC_Val _U(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL0_TCC_Val _U(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL0_MASK_Val _Ul(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _Ul(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL0_LINK_Val _Ul(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL0_EVENT_Val _Ul(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL0_IO_Val _Ul(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL0_AC_Val _Ul(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL0_TC_Val _Ul(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL0_ALTTC_Val _Ul(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL0_TCC_Val _Ul(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL0_SERCOM_Val _Ul(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ #define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) #define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) #define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) @@ -155,18 +155,18 @@ typedef union { #define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) #define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) #define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ -#define CCL_LUTCTRL_INSEL1_Msk (_U(0xF) << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_Msk (_Ul(0xF) << CCL_LUTCTRL_INSEL1_Pos) #define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) -#define CCL_LUTCTRL_INSEL1_MASK_Val _U(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL1_LINK_Val _U(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL1_EVENT_Val _U(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL1_IO_Val _U(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL1_AC_Val _U(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL1_TC_Val _U(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL1_TCC_Val _U(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL1_MASK_Val _Ul(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _Ul(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL1_LINK_Val _Ul(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL1_EVENT_Val _Ul(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL1_IO_Val _Ul(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL1_AC_Val _Ul(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL1_TC_Val _Ul(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL1_ALTTC_Val _Ul(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL1_TCC_Val _Ul(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL1_SERCOM_Val _Ul(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ #define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) #define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) #define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) @@ -178,18 +178,18 @@ typedef union { #define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos) #define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) #define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ -#define CCL_LUTCTRL_INSEL2_Msk (_U(0xF) << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_Msk (_Ul(0xF) << CCL_LUTCTRL_INSEL2_Pos) #define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) -#define CCL_LUTCTRL_INSEL2_MASK_Val _U(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL2_LINK_Val _U(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL2_EVENT_Val _U(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL2_IO_Val _U(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL2_AC_Val _U(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL2_TC_Val _U(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL2_TCC_Val _U(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL2_MASK_Val _Ul(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _Ul(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL2_LINK_Val _Ul(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL2_EVENT_Val _Ul(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL2_IO_Val _Ul(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL2_AC_Val _Ul(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL2_TC_Val _Ul(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL2_ALTTC_Val _Ul(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL2_TCC_Val _Ul(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL2_SERCOM_Val _Ul(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ #define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) #define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) #define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) @@ -201,15 +201,15 @@ typedef union { #define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos) #define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) #define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Inverted Event Input Enable */ -#define CCL_LUTCTRL_INVEI (_U(0x1) << CCL_LUTCTRL_INVEI_Pos) +#define CCL_LUTCTRL_INVEI (_Ul(0x1) << CCL_LUTCTRL_INVEI_Pos) #define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) LUT Event Input Enable */ -#define CCL_LUTCTRL_LUTEI (_U(0x1) << CCL_LUTCTRL_LUTEI_Pos) +#define CCL_LUTCTRL_LUTEI (_Ul(0x1) << CCL_LUTCTRL_LUTEI_Pos) #define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) LUT Event Output Enable */ -#define CCL_LUTCTRL_LUTEO (_U(0x1) << CCL_LUTCTRL_LUTEO_Pos) +#define CCL_LUTCTRL_LUTEO (_Ul(0x1) << CCL_LUTCTRL_LUTEO_Pos) #define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ -#define CCL_LUTCTRL_TRUTH_Msk (_U(0xFF) << CCL_LUTCTRL_TRUTH_Pos) +#define CCL_LUTCTRL_TRUTH_Msk (_Ul(0xFF) << CCL_LUTCTRL_TRUTH_Pos) #define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) -#define CCL_LUTCTRL_MASK _U(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */ +#define CCL_LUTCTRL_MASK _Ul(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */ /** \brief CCL hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) diff --git a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/cmcc.h b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/cmcc.h index eb2b08f..23532bf 100644 --- a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/cmcc.h +++ b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/cmcc.h @@ -57,33 +57,33 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define CMCC_TYPE_OFFSET 0x00 /**< \brief (CMCC_TYPE offset) Cache Type Register */ -#define CMCC_TYPE_RESETVALUE _U(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */ +#define CMCC_TYPE_RESETVALUE _Ul(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */ #define CMCC_TYPE_GCLK_Pos 1 /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */ -#define CMCC_TYPE_GCLK (_U(0x1) << CMCC_TYPE_GCLK_Pos) +#define CMCC_TYPE_GCLK (_Ul(0x1) << CMCC_TYPE_GCLK_Pos) #define CMCC_TYPE_RRP_Pos 4 /**< \brief (CMCC_TYPE) Round Robin Policy supported */ -#define CMCC_TYPE_RRP (_U(0x1) << CMCC_TYPE_RRP_Pos) +#define CMCC_TYPE_RRP (_Ul(0x1) << CMCC_TYPE_RRP_Pos) #define CMCC_TYPE_WAYNUM_Pos 5 /**< \brief (CMCC_TYPE) Number of Way */ -#define CMCC_TYPE_WAYNUM_Msk (_U(0x3) << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_WAYNUM_Msk (_Ul(0x3) << CMCC_TYPE_WAYNUM_Pos) #define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos)) -#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U(0x0) /**< \brief (CMCC_TYPE) Direct Mapped Cache */ -#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U(0x1) /**< \brief (CMCC_TYPE) 2-WAY set associative */ -#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U(0x2) /**< \brief (CMCC_TYPE) 4-WAY set associative */ +#define CMCC_TYPE_WAYNUM_DMAPPED_Val _Ul(0x0) /**< \brief (CMCC_TYPE) Direct Mapped Cache */ +#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _Ul(0x1) /**< \brief (CMCC_TYPE) 2-WAY set associative */ +#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _Ul(0x2) /**< \brief (CMCC_TYPE) 4-WAY set associative */ #define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos) #define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos) #define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos) #define CMCC_TYPE_LCKDOWN_Pos 7 /**< \brief (CMCC_TYPE) Lock Down supported */ -#define CMCC_TYPE_LCKDOWN (_U(0x1) << CMCC_TYPE_LCKDOWN_Pos) +#define CMCC_TYPE_LCKDOWN (_Ul(0x1) << CMCC_TYPE_LCKDOWN_Pos) #define CMCC_TYPE_CSIZE_Pos 8 /**< \brief (CMCC_TYPE) Cache Size */ -#define CMCC_TYPE_CSIZE_Msk (_U(0x7) << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_Msk (_Ul(0x7) << CMCC_TYPE_CSIZE_Pos) #define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos)) -#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U(0x0) /**< \brief (CMCC_TYPE) Cache Size is 1 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U(0x1) /**< \brief (CMCC_TYPE) Cache Size is 2 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U(0x2) /**< \brief (CMCC_TYPE) Cache Size is 4 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U(0x3) /**< \brief (CMCC_TYPE) Cache Size is 8 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U(0x4) /**< \brief (CMCC_TYPE) Cache Size is 16 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U(0x5) /**< \brief (CMCC_TYPE) Cache Size is 32 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U(0x6) /**< \brief (CMCC_TYPE) Cache Size is 64 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _Ul(0x0) /**< \brief (CMCC_TYPE) Cache Size is 1 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _Ul(0x1) /**< \brief (CMCC_TYPE) Cache Size is 2 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _Ul(0x2) /**< \brief (CMCC_TYPE) Cache Size is 4 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _Ul(0x3) /**< \brief (CMCC_TYPE) Cache Size is 8 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _Ul(0x4) /**< \brief (CMCC_TYPE) Cache Size is 16 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _Ul(0x5) /**< \brief (CMCC_TYPE) Cache Size is 32 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _Ul(0x6) /**< \brief (CMCC_TYPE) Cache Size is 64 KB */ #define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos) #define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos) #define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos) @@ -92,21 +92,21 @@ typedef union { #define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos) #define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos) #define CMCC_TYPE_CLSIZE_Pos 11 /**< \brief (CMCC_TYPE) Cache Line Size */ -#define CMCC_TYPE_CLSIZE_Msk (_U(0x7) << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_Msk (_Ul(0x7) << CMCC_TYPE_CLSIZE_Pos) #define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos)) -#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U(0x0) /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U(0x1) /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U(0x2) /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U(0x3) /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U(0x4) /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U(0x5) /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _Ul(0x0) /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _Ul(0x1) /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _Ul(0x2) /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _Ul(0x3) /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _Ul(0x4) /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _Ul(0x5) /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */ #define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos) #define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos) #define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos) #define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos) #define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos) #define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_MASK _U(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */ +#define CMCC_TYPE_MASK _Ul(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */ /* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -124,22 +124,22 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define CMCC_CFG_OFFSET 0x04 /**< \brief (CMCC_CFG offset) Cache Configuration Register */ -#define CMCC_CFG_RESETVALUE _U(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */ +#define CMCC_CFG_RESETVALUE _Ul(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */ #define CMCC_CFG_ICDIS_Pos 1 /**< \brief (CMCC_CFG) Instruction Cache Disable */ -#define CMCC_CFG_ICDIS (_U(0x1) << CMCC_CFG_ICDIS_Pos) +#define CMCC_CFG_ICDIS (_Ul(0x1) << CMCC_CFG_ICDIS_Pos) #define CMCC_CFG_DCDIS_Pos 2 /**< \brief (CMCC_CFG) Data Cache Disable */ -#define CMCC_CFG_DCDIS (_U(0x1) << CMCC_CFG_DCDIS_Pos) +#define CMCC_CFG_DCDIS (_Ul(0x1) << CMCC_CFG_DCDIS_Pos) #define CMCC_CFG_CSIZESW_Pos 4 /**< \brief (CMCC_CFG) Cache size configured by software */ -#define CMCC_CFG_CSIZESW_Msk (_U(0x7) << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_Msk (_Ul(0x7) << CMCC_CFG_CSIZESW_Pos) #define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos)) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U(0x0) /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U(0x1) /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U(0x2) /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U(0x3) /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U(0x4) /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U(0x5) /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U(0x6) /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _Ul(0x0) /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _Ul(0x1) /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _Ul(0x2) /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _Ul(0x3) /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _Ul(0x4) /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _Ul(0x5) /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _Ul(0x6) /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */ #define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos) #define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos) #define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos) @@ -147,7 +147,7 @@ typedef union { #define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos) #define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos) #define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_MASK _U(0x00000076) /**< \brief (CMCC_CFG) MASK Register */ +#define CMCC_CFG_MASK _Ul(0x00000076) /**< \brief (CMCC_CFG) MASK Register */ /* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -161,11 +161,11 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define CMCC_CTRL_OFFSET 0x08 /**< \brief (CMCC_CTRL offset) Cache Control Register */ -#define CMCC_CTRL_RESETVALUE _U(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */ +#define CMCC_CTRL_RESETVALUE _Ul(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */ #define CMCC_CTRL_CEN_Pos 0 /**< \brief (CMCC_CTRL) Cache Controller Enable */ -#define CMCC_CTRL_CEN (_U(0x1) << CMCC_CTRL_CEN_Pos) -#define CMCC_CTRL_MASK _U(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */ +#define CMCC_CTRL_CEN (_Ul(0x1) << CMCC_CTRL_CEN_Pos) +#define CMCC_CTRL_MASK _Ul(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */ /* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/ 32) Cache Status Register -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -179,11 +179,11 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define CMCC_SR_OFFSET 0x0C /**< \brief (CMCC_SR offset) Cache Status Register */ -#define CMCC_SR_RESETVALUE _U(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */ +#define CMCC_SR_RESETVALUE _Ul(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */ #define CMCC_SR_CSTS_Pos 0 /**< \brief (CMCC_SR) Cache Controller Status */ -#define CMCC_SR_CSTS (_U(0x1) << CMCC_SR_CSTS_Pos) -#define CMCC_SR_MASK _U(0x00000001) /**< \brief (CMCC_SR) MASK Register */ +#define CMCC_SR_CSTS (_Ul(0x1) << CMCC_SR_CSTS_Pos) +#define CMCC_SR_MASK _Ul(0x00000001) /**< \brief (CMCC_SR) MASK Register */ /* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -197,12 +197,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define CMCC_LCKWAY_OFFSET 0x10 /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */ -#define CMCC_LCKWAY_RESETVALUE _U(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */ +#define CMCC_LCKWAY_RESETVALUE _Ul(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */ #define CMCC_LCKWAY_LCKWAY_Pos 0 /**< \brief (CMCC_LCKWAY) Lockdown way Register */ -#define CMCC_LCKWAY_LCKWAY_Msk (_U(0xF) << CMCC_LCKWAY_LCKWAY_Pos) +#define CMCC_LCKWAY_LCKWAY_Msk (_Ul(0xF) << CMCC_LCKWAY_LCKWAY_Pos) #define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos)) -#define CMCC_LCKWAY_MASK _U(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */ +#define CMCC_LCKWAY_MASK _Ul(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */ /* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -216,11 +216,11 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define CMCC_MAINT0_OFFSET 0x20 /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */ -#define CMCC_MAINT0_RESETVALUE _U(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */ +#define CMCC_MAINT0_RESETVALUE _Ul(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */ #define CMCC_MAINT0_INVALL_Pos 0 /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */ -#define CMCC_MAINT0_INVALL (_U(0x1) << CMCC_MAINT0_INVALL_Pos) -#define CMCC_MAINT0_MASK _U(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */ +#define CMCC_MAINT0_INVALL (_Ul(0x1) << CMCC_MAINT0_INVALL_Pos) +#define CMCC_MAINT0_MASK _Ul(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */ /* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -236,23 +236,23 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define CMCC_MAINT1_OFFSET 0x24 /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */ -#define CMCC_MAINT1_RESETVALUE _U(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */ +#define CMCC_MAINT1_RESETVALUE _Ul(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */ #define CMCC_MAINT1_INDEX_Pos 4 /**< \brief (CMCC_MAINT1) Invalidate Index */ -#define CMCC_MAINT1_INDEX_Msk (_U(0xFF) << CMCC_MAINT1_INDEX_Pos) +#define CMCC_MAINT1_INDEX_Msk (_Ul(0xFF) << CMCC_MAINT1_INDEX_Pos) #define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos)) #define CMCC_MAINT1_WAY_Pos 28 /**< \brief (CMCC_MAINT1) Invalidate Way */ -#define CMCC_MAINT1_WAY_Msk (_U(0xF) << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY_Msk (_Ul(0xF) << CMCC_MAINT1_WAY_Pos) #define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos)) -#define CMCC_MAINT1_WAY_WAY0_Val _U(0x0) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY1_Val _U(0x1) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY2_Val _U(0x2) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY3_Val _U(0x3) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY0_Val _Ul(0x0) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY1_Val _Ul(0x1) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY2_Val _Ul(0x2) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY3_Val _Ul(0x3) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */ #define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos) #define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos) #define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos) #define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_MASK _U(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */ +#define CMCC_MAINT1_MASK _Ul(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */ /* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -266,18 +266,18 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define CMCC_MCFG_OFFSET 0x28 /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */ -#define CMCC_MCFG_RESETVALUE _U(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */ +#define CMCC_MCFG_RESETVALUE _Ul(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */ #define CMCC_MCFG_MODE_Pos 0 /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */ -#define CMCC_MCFG_MODE_Msk (_U(0x3) << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MODE_Msk (_Ul(0x3) << CMCC_MCFG_MODE_Pos) #define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos)) -#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U(0x0) /**< \brief (CMCC_MCFG) cycle counter */ -#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U(0x1) /**< \brief (CMCC_MCFG) instruction hit counter */ -#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U(0x2) /**< \brief (CMCC_MCFG) data hit counter */ +#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _Ul(0x0) /**< \brief (CMCC_MCFG) cycle counter */ +#define CMCC_MCFG_MODE_IHIT_COUNT_Val _Ul(0x1) /**< \brief (CMCC_MCFG) instruction hit counter */ +#define CMCC_MCFG_MODE_DHIT_COUNT_Val _Ul(0x2) /**< \brief (CMCC_MCFG) data hit counter */ #define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos) #define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) #define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) -#define CMCC_MCFG_MASK _U(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */ +#define CMCC_MCFG_MASK _Ul(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */ /* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -291,11 +291,11 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define CMCC_MEN_OFFSET 0x2C /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */ -#define CMCC_MEN_RESETVALUE _U(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */ +#define CMCC_MEN_RESETVALUE _Ul(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */ #define CMCC_MEN_MENABLE_Pos 0 /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */ -#define CMCC_MEN_MENABLE (_U(0x1) << CMCC_MEN_MENABLE_Pos) -#define CMCC_MEN_MASK _U(0x00000001) /**< \brief (CMCC_MEN) MASK Register */ +#define CMCC_MEN_MENABLE (_Ul(0x1) << CMCC_MEN_MENABLE_Pos) +#define CMCC_MEN_MASK _Ul(0x00000001) /**< \brief (CMCC_MEN) MASK Register */ /* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -309,11 +309,11 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define CMCC_MCTRL_OFFSET 0x30 /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */ -#define CMCC_MCTRL_RESETVALUE _U(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */ +#define CMCC_MCTRL_RESETVALUE _Ul(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */ #define CMCC_MCTRL_SWRST_Pos 0 /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */ -#define CMCC_MCTRL_SWRST (_U(0x1) << CMCC_MCTRL_SWRST_Pos) -#define CMCC_MCTRL_MASK _U(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */ +#define CMCC_MCTRL_SWRST (_Ul(0x1) << CMCC_MCTRL_SWRST_Pos) +#define CMCC_MCTRL_MASK _Ul(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */ /* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/ 32) Cache Monitor Status Register -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -326,12 +326,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define CMCC_MSR_OFFSET 0x34 /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */ -#define CMCC_MSR_RESETVALUE _U(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */ +#define CMCC_MSR_RESETVALUE _Ul(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */ #define CMCC_MSR_EVENT_CNT_Pos 0 /**< \brief (CMCC_MSR) Monitor Event Counter */ -#define CMCC_MSR_EVENT_CNT_Msk (_U(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos) +#define CMCC_MSR_EVENT_CNT_Msk (_Ul(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos) #define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos)) -#define CMCC_MSR_MASK _U(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */ +#define CMCC_MSR_MASK _Ul(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */ /** \brief CMCC APB hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) diff --git a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/dac.h b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/dac.h index 32a4a83..ea5988f 100644 --- a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/dac.h +++ b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/dac.h @@ -51,13 +51,13 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */ -#define DAC_CTRLA_RESETVALUE _U(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ +#define DAC_CTRLA_RESETVALUE _Ul(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ #define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ -#define DAC_CTRLA_SWRST (_U(0x1) << DAC_CTRLA_SWRST_Pos) +#define DAC_CTRLA_SWRST (_Ul(0x1) << DAC_CTRLA_SWRST_Pos) #define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */ -#define DAC_CTRLA_ENABLE (_U(0x1) << DAC_CTRLA_ENABLE_Pos) -#define DAC_CTRLA_MASK _U(0x03) /**< \brief (DAC_CTRLA) MASK Register */ +#define DAC_CTRLA_ENABLE (_Ul(0x1) << DAC_CTRLA_ENABLE_Pos) +#define DAC_CTRLA_MASK _Ul(0x03) /**< \brief (DAC_CTRLA) MASK Register */ /* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -72,22 +72,22 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */ -#define DAC_CTRLB_RESETVALUE _U(0x02) /**< \brief (DAC_CTRLB reset_value) Control B */ +#define DAC_CTRLB_RESETVALUE _Ul(0x02) /**< \brief (DAC_CTRLB reset_value) Control B */ #define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */ -#define DAC_CTRLB_DIFF (_U(0x1) << DAC_CTRLB_DIFF_Pos) +#define DAC_CTRLB_DIFF (_Ul(0x1) << DAC_CTRLB_DIFF_Pos) #define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */ -#define DAC_CTRLB_REFSEL_Msk (_U(0x3) << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_Msk (_Ul(0x3) << DAC_CTRLB_REFSEL_Pos) #define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) -#define DAC_CTRLB_REFSEL_VREFPU_Val _U(0x0) /**< \brief (DAC_CTRLB) External reference unbuffered */ -#define DAC_CTRLB_REFSEL_VDDANA_Val _U(0x1) /**< \brief (DAC_CTRLB) Analog supply */ -#define DAC_CTRLB_REFSEL_VREFPB_Val _U(0x2) /**< \brief (DAC_CTRLB) External reference buffered */ -#define DAC_CTRLB_REFSEL_INTREF_Val _U(0x3) /**< \brief (DAC_CTRLB) Internal bandgap reference */ +#define DAC_CTRLB_REFSEL_VREFPU_Val _Ul(0x0) /**< \brief (DAC_CTRLB) External reference unbuffered */ +#define DAC_CTRLB_REFSEL_VDDANA_Val _Ul(0x1) /**< \brief (DAC_CTRLB) Analog supply */ +#define DAC_CTRLB_REFSEL_VREFPB_Val _Ul(0x2) /**< \brief (DAC_CTRLB) External reference buffered */ +#define DAC_CTRLB_REFSEL_INTREF_Val _Ul(0x3) /**< \brief (DAC_CTRLB) Internal bandgap reference */ #define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) #define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) #define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) #define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_MASK _U(0x07) /**< \brief (DAC_CTRLB) MASK Register */ +#define DAC_CTRLB_MASK _Ul(0x07) /**< \brief (DAC_CTRLB) MASK Register */ /* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -113,37 +113,37 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */ -#define DAC_EVCTRL_RESETVALUE _U(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ +#define DAC_EVCTRL_RESETVALUE _Ul(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ #define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */ #define DAC_EVCTRL_STARTEI0 (1 << DAC_EVCTRL_STARTEI0_Pos) #define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */ #define DAC_EVCTRL_STARTEI1 (1 << DAC_EVCTRL_STARTEI1_Pos) #define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */ -#define DAC_EVCTRL_STARTEI_Msk (_U(0x3) << DAC_EVCTRL_STARTEI_Pos) +#define DAC_EVCTRL_STARTEI_Msk (_Ul(0x3) << DAC_EVCTRL_STARTEI_Pos) #define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos)) #define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */ #define DAC_EVCTRL_EMPTYEO0 (1 << DAC_EVCTRL_EMPTYEO0_Pos) #define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */ #define DAC_EVCTRL_EMPTYEO1 (1 << DAC_EVCTRL_EMPTYEO1_Pos) #define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */ -#define DAC_EVCTRL_EMPTYEO_Msk (_U(0x3) << DAC_EVCTRL_EMPTYEO_Pos) +#define DAC_EVCTRL_EMPTYEO_Msk (_Ul(0x3) << DAC_EVCTRL_EMPTYEO_Pos) #define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos)) #define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */ #define DAC_EVCTRL_INVEI0 (1 << DAC_EVCTRL_INVEI0_Pos) #define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */ #define DAC_EVCTRL_INVEI1 (1 << DAC_EVCTRL_INVEI1_Pos) #define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */ -#define DAC_EVCTRL_INVEI_Msk (_U(0x3) << DAC_EVCTRL_INVEI_Pos) +#define DAC_EVCTRL_INVEI_Msk (_Ul(0x3) << DAC_EVCTRL_INVEI_Pos) #define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos)) #define DAC_EVCTRL_RESRDYEO0_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output 0 */ #define DAC_EVCTRL_RESRDYEO0 (1 << DAC_EVCTRL_RESRDYEO0_Pos) #define DAC_EVCTRL_RESRDYEO1_Pos 7 /**< \brief (DAC_EVCTRL) Result Ready Event Output 1 */ #define DAC_EVCTRL_RESRDYEO1 (1 << DAC_EVCTRL_RESRDYEO1_Pos) #define DAC_EVCTRL_RESRDYEO_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output x */ -#define DAC_EVCTRL_RESRDYEO_Msk (_U(0x3) << DAC_EVCTRL_RESRDYEO_Pos) +#define DAC_EVCTRL_RESRDYEO_Msk (_Ul(0x3) << DAC_EVCTRL_RESRDYEO_Pos) #define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos)) -#define DAC_EVCTRL_MASK _U(0xFF) /**< \brief (DAC_EVCTRL) MASK Register */ +#define DAC_EVCTRL_MASK _Ul(0xFF) /**< \brief (DAC_EVCTRL) MASK Register */ /* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -169,37 +169,37 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ -#define DAC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ +#define DAC_INTENCLR_RESETVALUE _Ul(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ #define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun 0 Interrupt Enable */ #define DAC_INTENCLR_UNDERRUN0 (1 << DAC_INTENCLR_UNDERRUN0_Pos) #define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun 1 Interrupt Enable */ #define DAC_INTENCLR_UNDERRUN1 (1 << DAC_INTENCLR_UNDERRUN1_Pos) #define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun x Interrupt Enable */ -#define DAC_INTENCLR_UNDERRUN_Msk (_U(0x3) << DAC_INTENCLR_UNDERRUN_Pos) +#define DAC_INTENCLR_UNDERRUN_Msk (_Ul(0x3) << DAC_INTENCLR_UNDERRUN_Pos) #define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos)) #define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */ #define DAC_INTENCLR_EMPTY0 (1 << DAC_INTENCLR_EMPTY0_Pos) #define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */ #define DAC_INTENCLR_EMPTY1 (1 << DAC_INTENCLR_EMPTY1_Pos) #define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY_Msk (_U(0x3) << DAC_INTENCLR_EMPTY_Pos) +#define DAC_INTENCLR_EMPTY_Msk (_Ul(0x3) << DAC_INTENCLR_EMPTY_Pos) #define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos)) #define DAC_INTENCLR_RESRDY0_Pos 4 /**< \brief (DAC_INTENCLR) Result 0 Ready Interrupt Enable */ #define DAC_INTENCLR_RESRDY0 (1 << DAC_INTENCLR_RESRDY0_Pos) #define DAC_INTENCLR_RESRDY1_Pos 5 /**< \brief (DAC_INTENCLR) Result 1 Ready Interrupt Enable */ #define DAC_INTENCLR_RESRDY1 (1 << DAC_INTENCLR_RESRDY1_Pos) #define DAC_INTENCLR_RESRDY_Pos 4 /**< \brief (DAC_INTENCLR) Result x Ready Interrupt Enable */ -#define DAC_INTENCLR_RESRDY_Msk (_U(0x3) << DAC_INTENCLR_RESRDY_Pos) +#define DAC_INTENCLR_RESRDY_Msk (_Ul(0x3) << DAC_INTENCLR_RESRDY_Pos) #define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos)) #define DAC_INTENCLR_OVERRUN0_Pos 6 /**< \brief (DAC_INTENCLR) Overrun 0 Interrupt Enable */ #define DAC_INTENCLR_OVERRUN0 (1 << DAC_INTENCLR_OVERRUN0_Pos) #define DAC_INTENCLR_OVERRUN1_Pos 7 /**< \brief (DAC_INTENCLR) Overrun 1 Interrupt Enable */ #define DAC_INTENCLR_OVERRUN1 (1 << DAC_INTENCLR_OVERRUN1_Pos) #define DAC_INTENCLR_OVERRUN_Pos 6 /**< \brief (DAC_INTENCLR) Overrun x Interrupt Enable */ -#define DAC_INTENCLR_OVERRUN_Msk (_U(0x3) << DAC_INTENCLR_OVERRUN_Pos) +#define DAC_INTENCLR_OVERRUN_Msk (_Ul(0x3) << DAC_INTENCLR_OVERRUN_Pos) #define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos)) -#define DAC_INTENCLR_MASK _U(0xFF) /**< \brief (DAC_INTENCLR) MASK Register */ +#define DAC_INTENCLR_MASK _Ul(0xFF) /**< \brief (DAC_INTENCLR) MASK Register */ /* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -225,37 +225,37 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ -#define DAC_INTENSET_RESETVALUE _U(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ +#define DAC_INTENSET_RESETVALUE _Ul(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ #define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun 0 Interrupt Enable */ #define DAC_INTENSET_UNDERRUN0 (1 << DAC_INTENSET_UNDERRUN0_Pos) #define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun 1 Interrupt Enable */ #define DAC_INTENSET_UNDERRUN1 (1 << DAC_INTENSET_UNDERRUN1_Pos) #define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun x Interrupt Enable */ -#define DAC_INTENSET_UNDERRUN_Msk (_U(0x3) << DAC_INTENSET_UNDERRUN_Pos) +#define DAC_INTENSET_UNDERRUN_Msk (_Ul(0x3) << DAC_INTENSET_UNDERRUN_Pos) #define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos)) #define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */ #define DAC_INTENSET_EMPTY0 (1 << DAC_INTENSET_EMPTY0_Pos) #define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */ #define DAC_INTENSET_EMPTY1 (1 << DAC_INTENSET_EMPTY1_Pos) #define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY_Msk (_U(0x3) << DAC_INTENSET_EMPTY_Pos) +#define DAC_INTENSET_EMPTY_Msk (_Ul(0x3) << DAC_INTENSET_EMPTY_Pos) #define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos)) #define DAC_INTENSET_RESRDY0_Pos 4 /**< \brief (DAC_INTENSET) Result 0 Ready Interrupt Enable */ #define DAC_INTENSET_RESRDY0 (1 << DAC_INTENSET_RESRDY0_Pos) #define DAC_INTENSET_RESRDY1_Pos 5 /**< \brief (DAC_INTENSET) Result 1 Ready Interrupt Enable */ #define DAC_INTENSET_RESRDY1 (1 << DAC_INTENSET_RESRDY1_Pos) #define DAC_INTENSET_RESRDY_Pos 4 /**< \brief (DAC_INTENSET) Result x Ready Interrupt Enable */ -#define DAC_INTENSET_RESRDY_Msk (_U(0x3) << DAC_INTENSET_RESRDY_Pos) +#define DAC_INTENSET_RESRDY_Msk (_Ul(0x3) << DAC_INTENSET_RESRDY_Pos) #define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos)) #define DAC_INTENSET_OVERRUN0_Pos 6 /**< \brief (DAC_INTENSET) Overrun 0 Interrupt Enable */ #define DAC_INTENSET_OVERRUN0 (1 << DAC_INTENSET_OVERRUN0_Pos) #define DAC_INTENSET_OVERRUN1_Pos 7 /**< \brief (DAC_INTENSET) Overrun 1 Interrupt Enable */ #define DAC_INTENSET_OVERRUN1 (1 << DAC_INTENSET_OVERRUN1_Pos) #define DAC_INTENSET_OVERRUN_Pos 6 /**< \brief (DAC_INTENSET) Overrun x Interrupt Enable */ -#define DAC_INTENSET_OVERRUN_Msk (_U(0x3) << DAC_INTENSET_OVERRUN_Pos) +#define DAC_INTENSET_OVERRUN_Msk (_Ul(0x3) << DAC_INTENSET_OVERRUN_Pos) #define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos)) -#define DAC_INTENSET_MASK _U(0xFF) /**< \brief (DAC_INTENSET) MASK Register */ +#define DAC_INTENSET_MASK _Ul(0xFF) /**< \brief (DAC_INTENSET) MASK Register */ /* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -281,37 +281,37 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define DAC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ +#define DAC_INTFLAG_RESETVALUE _Ul(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ #define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) Result 0 Underrun */ #define DAC_INTFLAG_UNDERRUN0 (1 << DAC_INTFLAG_UNDERRUN0_Pos) #define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) Result 1 Underrun */ #define DAC_INTFLAG_UNDERRUN1 (1 << DAC_INTFLAG_UNDERRUN1_Pos) #define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Result x Underrun */ -#define DAC_INTFLAG_UNDERRUN_Msk (_U(0x3) << DAC_INTFLAG_UNDERRUN_Pos) +#define DAC_INTFLAG_UNDERRUN_Msk (_Ul(0x3) << DAC_INTFLAG_UNDERRUN_Pos) #define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos)) #define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */ #define DAC_INTFLAG_EMPTY0 (1 << DAC_INTFLAG_EMPTY0_Pos) #define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */ #define DAC_INTFLAG_EMPTY1 (1 << DAC_INTFLAG_EMPTY1_Pos) #define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */ -#define DAC_INTFLAG_EMPTY_Msk (_U(0x3) << DAC_INTFLAG_EMPTY_Pos) +#define DAC_INTFLAG_EMPTY_Msk (_Ul(0x3) << DAC_INTFLAG_EMPTY_Pos) #define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos)) #define DAC_INTFLAG_RESRDY0_Pos 4 /**< \brief (DAC_INTFLAG) Result 0 Ready */ #define DAC_INTFLAG_RESRDY0 (1 << DAC_INTFLAG_RESRDY0_Pos) #define DAC_INTFLAG_RESRDY1_Pos 5 /**< \brief (DAC_INTFLAG) Result 1 Ready */ #define DAC_INTFLAG_RESRDY1 (1 << DAC_INTFLAG_RESRDY1_Pos) #define DAC_INTFLAG_RESRDY_Pos 4 /**< \brief (DAC_INTFLAG) Result x Ready */ -#define DAC_INTFLAG_RESRDY_Msk (_U(0x3) << DAC_INTFLAG_RESRDY_Pos) +#define DAC_INTFLAG_RESRDY_Msk (_Ul(0x3) << DAC_INTFLAG_RESRDY_Pos) #define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos)) #define DAC_INTFLAG_OVERRUN0_Pos 6 /**< \brief (DAC_INTFLAG) Result 0 Overrun */ #define DAC_INTFLAG_OVERRUN0 (1 << DAC_INTFLAG_OVERRUN0_Pos) #define DAC_INTFLAG_OVERRUN1_Pos 7 /**< \brief (DAC_INTFLAG) Result 1 Overrun */ #define DAC_INTFLAG_OVERRUN1 (1 << DAC_INTFLAG_OVERRUN1_Pos) #define DAC_INTFLAG_OVERRUN_Pos 6 /**< \brief (DAC_INTFLAG) Result x Overrun */ -#define DAC_INTFLAG_OVERRUN_Msk (_U(0x3) << DAC_INTFLAG_OVERRUN_Pos) +#define DAC_INTFLAG_OVERRUN_Msk (_Ul(0x3) << DAC_INTFLAG_OVERRUN_Pos) #define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos)) -#define DAC_INTFLAG_MASK _U(0xFF) /**< \brief (DAC_INTFLAG) MASK Register */ +#define DAC_INTFLAG_MASK _Ul(0xFF) /**< \brief (DAC_INTFLAG) MASK Register */ /* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -333,23 +333,23 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */ -#define DAC_STATUS_RESETVALUE _U(0x00) /**< \brief (DAC_STATUS reset_value) Status */ +#define DAC_STATUS_RESETVALUE _Ul(0x00) /**< \brief (DAC_STATUS reset_value) Status */ #define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */ #define DAC_STATUS_READY0 (1 << DAC_STATUS_READY0_Pos) #define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */ #define DAC_STATUS_READY1 (1 << DAC_STATUS_READY1_Pos) #define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */ -#define DAC_STATUS_READY_Msk (_U(0x3) << DAC_STATUS_READY_Pos) +#define DAC_STATUS_READY_Msk (_Ul(0x3) << DAC_STATUS_READY_Pos) #define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos)) #define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */ #define DAC_STATUS_EOC0 (1 << DAC_STATUS_EOC0_Pos) #define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */ #define DAC_STATUS_EOC1 (1 << DAC_STATUS_EOC1_Pos) #define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */ -#define DAC_STATUS_EOC_Msk (_U(0x3) << DAC_STATUS_EOC_Pos) +#define DAC_STATUS_EOC_Msk (_Ul(0x3) << DAC_STATUS_EOC_Pos) #define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos)) -#define DAC_STATUS_MASK _U(0x0F) /**< \brief (DAC_STATUS) MASK Register */ +#define DAC_STATUS_MASK _Ul(0x0F) /**< \brief (DAC_STATUS) MASK Register */ /* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -374,27 +374,27 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */ -#define DAC_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ +#define DAC_SYNCBUSY_RESETVALUE _Ul(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ #define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */ -#define DAC_SYNCBUSY_SWRST (_U(0x1) << DAC_SYNCBUSY_SWRST_Pos) +#define DAC_SYNCBUSY_SWRST (_Ul(0x1) << DAC_SYNCBUSY_SWRST_Pos) #define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */ -#define DAC_SYNCBUSY_ENABLE (_U(0x1) << DAC_SYNCBUSY_ENABLE_Pos) +#define DAC_SYNCBUSY_ENABLE (_Ul(0x1) << DAC_SYNCBUSY_ENABLE_Pos) #define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */ #define DAC_SYNCBUSY_DATA0 (1 << DAC_SYNCBUSY_DATA0_Pos) #define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */ #define DAC_SYNCBUSY_DATA1 (1 << DAC_SYNCBUSY_DATA1_Pos) #define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */ -#define DAC_SYNCBUSY_DATA_Msk (_U(0x3) << DAC_SYNCBUSY_DATA_Pos) +#define DAC_SYNCBUSY_DATA_Msk (_Ul(0x3) << DAC_SYNCBUSY_DATA_Pos) #define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos)) #define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */ #define DAC_SYNCBUSY_DATABUF0 (1 << DAC_SYNCBUSY_DATABUF0_Pos) #define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */ #define DAC_SYNCBUSY_DATABUF1 (1 << DAC_SYNCBUSY_DATABUF1_Pos) #define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */ -#define DAC_SYNCBUSY_DATABUF_Msk (_U(0x3) << DAC_SYNCBUSY_DATABUF_Pos) +#define DAC_SYNCBUSY_DATABUF_Msk (_Ul(0x3) << DAC_SYNCBUSY_DATABUF_Pos) #define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos)) -#define DAC_SYNCBUSY_MASK _U(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */ +#define DAC_SYNCBUSY_MASK _Ul(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */ /* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -416,34 +416,34 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */ -#define DAC_DACCTRL_RESETVALUE _U(0x0000) /**< \brief (DAC_DACCTRL reset_value) DAC n Control */ +#define DAC_DACCTRL_RESETVALUE _Ul(0x0000) /**< \brief (DAC_DACCTRL reset_value) DAC n Control */ #define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */ -#define DAC_DACCTRL_LEFTADJ (_U(0x1) << DAC_DACCTRL_LEFTADJ_Pos) +#define DAC_DACCTRL_LEFTADJ (_Ul(0x1) << DAC_DACCTRL_LEFTADJ_Pos) #define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */ -#define DAC_DACCTRL_ENABLE (_U(0x1) << DAC_DACCTRL_ENABLE_Pos) +#define DAC_DACCTRL_ENABLE (_Ul(0x1) << DAC_DACCTRL_ENABLE_Pos) #define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */ -#define DAC_DACCTRL_CCTRL_Msk (_U(0x3) << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_CCTRL_Msk (_Ul(0x3) << DAC_DACCTRL_CCTRL_Pos) #define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos)) -#define DAC_DACCTRL_CCTRL_CC100K_Val _U(0x0) /**< \brief (DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS) */ -#define DAC_DACCTRL_CCTRL_CC1M_Val _U(0x1) /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS) */ -#define DAC_DACCTRL_CCTRL_CC12M_Val _U(0x2) /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) */ +#define DAC_DACCTRL_CCTRL_CC100K_Val _Ul(0x0) /**< \brief (DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS) */ +#define DAC_DACCTRL_CCTRL_CC1M_Val _Ul(0x1) /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS) */ +#define DAC_DACCTRL_CCTRL_CC12M_Val _Ul(0x2) /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) */ #define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) #define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) #define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) #define DAC_DACCTRL_FEXT_Pos 5 /**< \brief (DAC_DACCTRL) Standalone Filter */ -#define DAC_DACCTRL_FEXT (_U(0x1) << DAC_DACCTRL_FEXT_Pos) +#define DAC_DACCTRL_FEXT (_Ul(0x1) << DAC_DACCTRL_FEXT_Pos) #define DAC_DACCTRL_RUNSTDBY_Pos 6 /**< \brief (DAC_DACCTRL) Run in Standby */ -#define DAC_DACCTRL_RUNSTDBY (_U(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) +#define DAC_DACCTRL_RUNSTDBY (_Ul(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) #define DAC_DACCTRL_DITHER_Pos 7 /**< \brief (DAC_DACCTRL) Dithering Mode */ -#define DAC_DACCTRL_DITHER (_U(0x1) << DAC_DACCTRL_DITHER_Pos) +#define DAC_DACCTRL_DITHER (_Ul(0x1) << DAC_DACCTRL_DITHER_Pos) #define DAC_DACCTRL_REFRESH_Pos 8 /**< \brief (DAC_DACCTRL) Refresh period */ -#define DAC_DACCTRL_REFRESH_Msk (_U(0xF) << DAC_DACCTRL_REFRESH_Pos) +#define DAC_DACCTRL_REFRESH_Msk (_Ul(0xF) << DAC_DACCTRL_REFRESH_Pos) #define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos)) #define DAC_DACCTRL_OSR_Pos 13 /**< \brief (DAC_DACCTRL) Sampling Rate */ -#define DAC_DACCTRL_OSR_Msk (_U(0x7) << DAC_DACCTRL_OSR_Pos) +#define DAC_DACCTRL_OSR_Msk (_Ul(0x7) << DAC_DACCTRL_OSR_Pos) #define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos)) -#define DAC_DACCTRL_MASK _U(0xEFEF) /**< \brief (DAC_DACCTRL) MASK Register */ +#define DAC_DACCTRL_MASK _Ul(0xEFEF) /**< \brief (DAC_DACCTRL) MASK Register */ /* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -456,12 +456,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DAC_DATA_OFFSET 0x10 /**< \brief (DAC_DATA offset) DAC n Data */ -#define DAC_DATA_RESETVALUE _U(0x0000) /**< \brief (DAC_DATA reset_value) DAC n Data */ +#define DAC_DATA_RESETVALUE _Ul(0x0000) /**< \brief (DAC_DATA reset_value) DAC n Data */ #define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) DAC0 Data */ -#define DAC_DATA_DATA_Msk (_U(0xFFFF) << DAC_DATA_DATA_Pos) +#define DAC_DATA_DATA_Msk (_Ul(0xFFFF) << DAC_DATA_DATA_Pos) #define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) -#define DAC_DATA_MASK _U(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ +#define DAC_DATA_MASK _Ul(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ /* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -474,12 +474,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DAC_DATABUF_OFFSET 0x14 /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */ -#define DAC_DATABUF_RESETVALUE _U(0x0000) /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */ +#define DAC_DATABUF_RESETVALUE _Ul(0x0000) /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */ #define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) DAC0 Data Buffer */ -#define DAC_DATABUF_DATABUF_Msk (_U(0xFFFF) << DAC_DATABUF_DATABUF_Pos) +#define DAC_DATABUF_DATABUF_Msk (_Ul(0xFFFF) << DAC_DATABUF_DATABUF_Pos) #define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) -#define DAC_DATABUF_MASK _U(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ +#define DAC_DATABUF_MASK _Ul(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ /* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -493,11 +493,11 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DAC_DBGCTRL_OFFSET 0x18 /**< \brief (DAC_DBGCTRL offset) Debug Control */ -#define DAC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */ +#define DAC_DBGCTRL_RESETVALUE _Ul(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */ #define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */ -#define DAC_DBGCTRL_DBGRUN (_U(0x1) << DAC_DBGCTRL_DBGRUN_Pos) -#define DAC_DBGCTRL_MASK _U(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */ +#define DAC_DBGCTRL_DBGRUN (_Ul(0x1) << DAC_DBGCTRL_DBGRUN_Pos) +#define DAC_DBGCTRL_MASK _Ul(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */ /* -------- DAC_RESULT : (DAC Offset: 0x1C) (R/ 16) Filter Result -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -510,12 +510,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DAC_RESULT_OFFSET 0x1C /**< \brief (DAC_RESULT offset) Filter Result */ -#define DAC_RESULT_RESETVALUE _U(0x0000) /**< \brief (DAC_RESULT reset_value) Filter Result */ +#define DAC_RESULT_RESETVALUE _Ul(0x0000) /**< \brief (DAC_RESULT reset_value) Filter Result */ #define DAC_RESULT_RESULT_Pos 0 /**< \brief (DAC_RESULT) Filter Result */ -#define DAC_RESULT_RESULT_Msk (_U(0xFFFF) << DAC_RESULT_RESULT_Pos) +#define DAC_RESULT_RESULT_Msk (_Ul(0xFFFF) << DAC_RESULT_RESULT_Pos) #define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos)) -#define DAC_RESULT_MASK _U(0xFFFF) /**< \brief (DAC_RESULT) MASK Register */ +#define DAC_RESULT_MASK _Ul(0xFFFF) /**< \brief (DAC_RESULT) MASK Register */ /** \brief DAC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) diff --git a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/dmac.h b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/dmac.h index f97a4d3..0e07690 100644 --- a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/dmac.h +++ b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/dmac.h @@ -61,12 +61,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ -#define DMAC_CTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */ +#define DMAC_CTRL_RESETVALUE _Ul(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */ #define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ -#define DMAC_CTRL_SWRST (_U(0x1) << DMAC_CTRL_SWRST_Pos) +#define DMAC_CTRL_SWRST (_Ul(0x1) << DMAC_CTRL_SWRST_Pos) #define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ -#define DMAC_CTRL_DMAENABLE (_U(0x1) << DMAC_CTRL_DMAENABLE_Pos) +#define DMAC_CTRL_DMAENABLE (_Ul(0x1) << DMAC_CTRL_DMAENABLE_Pos) #define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ #define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos) #define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ @@ -76,9 +76,9 @@ typedef union { #define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ #define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos) #define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ -#define DMAC_CTRL_LVLEN_Msk (_U(0xF) << DMAC_CTRL_LVLEN_Pos) +#define DMAC_CTRL_LVLEN_Msk (_Ul(0xF) << DMAC_CTRL_LVLEN_Pos) #define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) -#define DMAC_CTRL_MASK _U(0x0F03) /**< \brief (DMAC_CTRL) MASK Register */ +#define DMAC_CTRL_MASK _Ul(0x0F03) /**< \brief (DMAC_CTRL) MASK Register */ /* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -95,41 +95,41 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ -#define DMAC_CRCCTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ +#define DMAC_CRCCTRL_RESETVALUE _Ul(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ #define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ -#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_Ul(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) #define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _Ul(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _Ul(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _Ul(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) #define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) #define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ -#define DMAC_CRCCTRL_CRCPOLY_Msk (_U(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY_Msk (_Ul(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) #define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) -#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _Ul(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _Ul(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ #define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) #define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) #define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ -#define DMAC_CRCCTRL_CRCSRC_Msk (_U(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC_Msk (_Ul(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) #define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) -#define DMAC_CRCCTRL_CRCSRC_DISABLE_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) CRC Disabled */ -#define DMAC_CRCCTRL_CRCSRC_IO_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */ +#define DMAC_CRCCTRL_CRCSRC_DISABLE_Val _Ul(0x0) /**< \brief (DMAC_CRCCTRL) CRC Disabled */ +#define DMAC_CRCCTRL_CRCSRC_IO_Val _Ul(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */ #define DMAC_CRCCTRL_CRCSRC_DISABLE (DMAC_CRCCTRL_CRCSRC_DISABLE_Val << DMAC_CRCCTRL_CRCSRC_Pos) #define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) #define DMAC_CRCCTRL_CRCMODE_Pos 14 /**< \brief (DMAC_CRCCTRL) CRC Operating Mode */ -#define DMAC_CRCCTRL_CRCMODE_Msk (_U(0x3) << DMAC_CRCCTRL_CRCMODE_Pos) +#define DMAC_CRCCTRL_CRCMODE_Msk (_Ul(0x3) << DMAC_CRCCTRL_CRCMODE_Pos) #define DMAC_CRCCTRL_CRCMODE(value) (DMAC_CRCCTRL_CRCMODE_Msk & ((value) << DMAC_CRCCTRL_CRCMODE_Pos)) -#define DMAC_CRCCTRL_CRCMODE_DEFAULT_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) Default operating mode */ -#define DMAC_CRCCTRL_CRCMODE_CRCMON_Val _U(0x2) /**< \brief (DMAC_CRCCTRL) Memory CRC monitor operating mode */ -#define DMAC_CRCCTRL_CRCMODE_CRCGEN_Val _U(0x3) /**< \brief (DMAC_CRCCTRL) Memory CRC generation operating mode */ +#define DMAC_CRCCTRL_CRCMODE_DEFAULT_Val _Ul(0x0) /**< \brief (DMAC_CRCCTRL) Default operating mode */ +#define DMAC_CRCCTRL_CRCMODE_CRCMON_Val _Ul(0x2) /**< \brief (DMAC_CRCCTRL) Memory CRC monitor operating mode */ +#define DMAC_CRCCTRL_CRCMODE_CRCGEN_Val _Ul(0x3) /**< \brief (DMAC_CRCCTRL) Memory CRC generation operating mode */ #define DMAC_CRCCTRL_CRCMODE_DEFAULT (DMAC_CRCCTRL_CRCMODE_DEFAULT_Val << DMAC_CRCCTRL_CRCMODE_Pos) #define DMAC_CRCCTRL_CRCMODE_CRCMON (DMAC_CRCCTRL_CRCMODE_CRCMON_Val << DMAC_CRCCTRL_CRCMODE_Pos) #define DMAC_CRCCTRL_CRCMODE_CRCGEN (DMAC_CRCCTRL_CRCMODE_CRCGEN_Val << DMAC_CRCCTRL_CRCMODE_Pos) -#define DMAC_CRCCTRL_MASK _U(0xFF0F) /**< \brief (DMAC_CRCCTRL) MASK Register */ +#define DMAC_CRCCTRL_MASK _Ul(0xFF0F) /**< \brief (DMAC_CRCCTRL) MASK Register */ /* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -142,12 +142,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ -#define DMAC_CRCDATAIN_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ +#define DMAC_CRCDATAIN_RESETVALUE _Ul(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ #define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ -#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) +#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_Ul(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) #define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) -#define DMAC_CRCDATAIN_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */ +#define DMAC_CRCDATAIN_MASK _Ul(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */ /* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -160,12 +160,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ -#define DMAC_CRCCHKSUM_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ +#define DMAC_CRCCHKSUM_RESETVALUE _Ul(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ #define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ -#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) +#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_Ul(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) #define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) -#define DMAC_CRCCHKSUM_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */ +#define DMAC_CRCCHKSUM_MASK _Ul(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */ /* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -181,15 +181,15 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ -#define DMAC_CRCSTATUS_RESETVALUE _U(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ +#define DMAC_CRCSTATUS_RESETVALUE _Ul(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ #define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ -#define DMAC_CRCSTATUS_CRCBUSY (_U(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) +#define DMAC_CRCSTATUS_CRCBUSY (_Ul(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) #define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ -#define DMAC_CRCSTATUS_CRCZERO (_U(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) +#define DMAC_CRCSTATUS_CRCZERO (_Ul(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) #define DMAC_CRCSTATUS_CRCERR_Pos 2 /**< \brief (DMAC_CRCSTATUS) CRC Error */ -#define DMAC_CRCSTATUS_CRCERR (_U(0x1) << DMAC_CRCSTATUS_CRCERR_Pos) -#define DMAC_CRCSTATUS_MASK _U(0x07) /**< \brief (DMAC_CRCSTATUS) MASK Register */ +#define DMAC_CRCSTATUS_CRCERR (_Ul(0x1) << DMAC_CRCSTATUS_CRCERR_Pos) +#define DMAC_CRCSTATUS_MASK _Ul(0x07) /**< \brief (DMAC_CRCSTATUS) MASK Register */ /* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -203,11 +203,11 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ -#define DMAC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ +#define DMAC_DBGCTRL_RESETVALUE _Ul(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ #define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ -#define DMAC_DBGCTRL_DBGRUN (_U(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) -#define DMAC_DBGCTRL_MASK _U(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */ +#define DMAC_DBGCTRL_DBGRUN (_Ul(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) +#define DMAC_DBGCTRL_MASK _Ul(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */ /* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -254,7 +254,7 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ -#define DMAC_SWTRIGCTRL_RESETVALUE _U(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ +#define DMAC_SWTRIGCTRL_RESETVALUE _Ul(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ #define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ #define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos) @@ -321,9 +321,9 @@ typedef union { #define DMAC_SWTRIGCTRL_SWTRIG31_Pos 31 /**< \brief (DMAC_SWTRIGCTRL) Channel 31 Software Trigger */ #define DMAC_SWTRIGCTRL_SWTRIG31 (1 << DMAC_SWTRIGCTRL_SWTRIG31_Pos) #define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U(0xFFFFFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_Ul(0xFFFFFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) #define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) -#define DMAC_SWTRIGCTRL_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ +#define DMAC_SWTRIGCTRL_MASK _Ul(0xFFFFFFFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ /* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -347,73 +347,73 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ -#define DMAC_PRICTRL0_RESETVALUE _U(0x40404040) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ +#define DMAC_PRICTRL0_RESETVALUE _Ul(0x40404040) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ #define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI0_Msk (_U(0x1F) << DMAC_PRICTRL0_LVLPRI0_Pos) +#define DMAC_PRICTRL0_LVLPRI0_Msk (_Ul(0x1F) << DMAC_PRICTRL0_LVLPRI0_Pos) #define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) #define DMAC_PRICTRL0_QOS0_Pos 5 /**< \brief (DMAC_PRICTRL0) Level 0 Quality of Service */ -#define DMAC_PRICTRL0_QOS0_Msk (_U(0x3) << DMAC_PRICTRL0_QOS0_Pos) +#define DMAC_PRICTRL0_QOS0_Msk (_Ul(0x3) << DMAC_PRICTRL0_QOS0_Pos) #define DMAC_PRICTRL0_QOS0(value) (DMAC_PRICTRL0_QOS0_Msk & ((value) << DMAC_PRICTRL0_QOS0_Pos)) -#define DMAC_PRICTRL0_QOS0_REGULAR_Val _U(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS0_SHORTAGE_Val _U(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS0_SENSITIVE_Val _U(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS0_CRITICAL_Val _U(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ +#define DMAC_PRICTRL0_QOS0_REGULAR_Val _Ul(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ +#define DMAC_PRICTRL0_QOS0_SHORTAGE_Val _Ul(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ +#define DMAC_PRICTRL0_QOS0_SENSITIVE_Val _Ul(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ +#define DMAC_PRICTRL0_QOS0_CRITICAL_Val _Ul(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ #define DMAC_PRICTRL0_QOS0_REGULAR (DMAC_PRICTRL0_QOS0_REGULAR_Val << DMAC_PRICTRL0_QOS0_Pos) #define DMAC_PRICTRL0_QOS0_SHORTAGE (DMAC_PRICTRL0_QOS0_SHORTAGE_Val << DMAC_PRICTRL0_QOS0_Pos) #define DMAC_PRICTRL0_QOS0_SENSITIVE (DMAC_PRICTRL0_QOS0_SENSITIVE_Val << DMAC_PRICTRL0_QOS0_Pos) #define DMAC_PRICTRL0_QOS0_CRITICAL (DMAC_PRICTRL0_QOS0_CRITICAL_Val << DMAC_PRICTRL0_QOS0_Pos) #define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN0 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) +#define DMAC_PRICTRL0_RRLVLEN0 (_Ul(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) #define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI1_Msk (_U(0x1F) << DMAC_PRICTRL0_LVLPRI1_Pos) +#define DMAC_PRICTRL0_LVLPRI1_Msk (_Ul(0x1F) << DMAC_PRICTRL0_LVLPRI1_Pos) #define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) #define DMAC_PRICTRL0_QOS1_Pos 13 /**< \brief (DMAC_PRICTRL0) Level 1 Quality of Service */ -#define DMAC_PRICTRL0_QOS1_Msk (_U(0x3) << DMAC_PRICTRL0_QOS1_Pos) +#define DMAC_PRICTRL0_QOS1_Msk (_Ul(0x3) << DMAC_PRICTRL0_QOS1_Pos) #define DMAC_PRICTRL0_QOS1(value) (DMAC_PRICTRL0_QOS1_Msk & ((value) << DMAC_PRICTRL0_QOS1_Pos)) -#define DMAC_PRICTRL0_QOS1_REGULAR_Val _U(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS1_SHORTAGE_Val _U(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS1_SENSITIVE_Val _U(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS1_CRITICAL_Val _U(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ +#define DMAC_PRICTRL0_QOS1_REGULAR_Val _Ul(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ +#define DMAC_PRICTRL0_QOS1_SHORTAGE_Val _Ul(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ +#define DMAC_PRICTRL0_QOS1_SENSITIVE_Val _Ul(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ +#define DMAC_PRICTRL0_QOS1_CRITICAL_Val _Ul(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ #define DMAC_PRICTRL0_QOS1_REGULAR (DMAC_PRICTRL0_QOS1_REGULAR_Val << DMAC_PRICTRL0_QOS1_Pos) #define DMAC_PRICTRL0_QOS1_SHORTAGE (DMAC_PRICTRL0_QOS1_SHORTAGE_Val << DMAC_PRICTRL0_QOS1_Pos) #define DMAC_PRICTRL0_QOS1_SENSITIVE (DMAC_PRICTRL0_QOS1_SENSITIVE_Val << DMAC_PRICTRL0_QOS1_Pos) #define DMAC_PRICTRL0_QOS1_CRITICAL (DMAC_PRICTRL0_QOS1_CRITICAL_Val << DMAC_PRICTRL0_QOS1_Pos) #define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN1 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) +#define DMAC_PRICTRL0_RRLVLEN1 (_Ul(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) #define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI2_Msk (_U(0x1F) << DMAC_PRICTRL0_LVLPRI2_Pos) +#define DMAC_PRICTRL0_LVLPRI2_Msk (_Ul(0x1F) << DMAC_PRICTRL0_LVLPRI2_Pos) #define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) #define DMAC_PRICTRL0_QOS2_Pos 21 /**< \brief (DMAC_PRICTRL0) Level 2 Quality of Service */ -#define DMAC_PRICTRL0_QOS2_Msk (_U(0x3) << DMAC_PRICTRL0_QOS2_Pos) +#define DMAC_PRICTRL0_QOS2_Msk (_Ul(0x3) << DMAC_PRICTRL0_QOS2_Pos) #define DMAC_PRICTRL0_QOS2(value) (DMAC_PRICTRL0_QOS2_Msk & ((value) << DMAC_PRICTRL0_QOS2_Pos)) -#define DMAC_PRICTRL0_QOS2_REGULAR_Val _U(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS2_SHORTAGE_Val _U(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS2_SENSITIVE_Val _U(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS2_CRITICAL_Val _U(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ +#define DMAC_PRICTRL0_QOS2_REGULAR_Val _Ul(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ +#define DMAC_PRICTRL0_QOS2_SHORTAGE_Val _Ul(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ +#define DMAC_PRICTRL0_QOS2_SENSITIVE_Val _Ul(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ +#define DMAC_PRICTRL0_QOS2_CRITICAL_Val _Ul(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ #define DMAC_PRICTRL0_QOS2_REGULAR (DMAC_PRICTRL0_QOS2_REGULAR_Val << DMAC_PRICTRL0_QOS2_Pos) #define DMAC_PRICTRL0_QOS2_SHORTAGE (DMAC_PRICTRL0_QOS2_SHORTAGE_Val << DMAC_PRICTRL0_QOS2_Pos) #define DMAC_PRICTRL0_QOS2_SENSITIVE (DMAC_PRICTRL0_QOS2_SENSITIVE_Val << DMAC_PRICTRL0_QOS2_Pos) #define DMAC_PRICTRL0_QOS2_CRITICAL (DMAC_PRICTRL0_QOS2_CRITICAL_Val << DMAC_PRICTRL0_QOS2_Pos) #define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN2 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) +#define DMAC_PRICTRL0_RRLVLEN2 (_Ul(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) #define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI3_Msk (_U(0x1F) << DMAC_PRICTRL0_LVLPRI3_Pos) +#define DMAC_PRICTRL0_LVLPRI3_Msk (_Ul(0x1F) << DMAC_PRICTRL0_LVLPRI3_Pos) #define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) #define DMAC_PRICTRL0_QOS3_Pos 29 /**< \brief (DMAC_PRICTRL0) Level 3 Quality of Service */ -#define DMAC_PRICTRL0_QOS3_Msk (_U(0x3) << DMAC_PRICTRL0_QOS3_Pos) +#define DMAC_PRICTRL0_QOS3_Msk (_Ul(0x3) << DMAC_PRICTRL0_QOS3_Pos) #define DMAC_PRICTRL0_QOS3(value) (DMAC_PRICTRL0_QOS3_Msk & ((value) << DMAC_PRICTRL0_QOS3_Pos)) -#define DMAC_PRICTRL0_QOS3_REGULAR_Val _U(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS3_SHORTAGE_Val _U(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS3_SENSITIVE_Val _U(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS3_CRITICAL_Val _U(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ +#define DMAC_PRICTRL0_QOS3_REGULAR_Val _Ul(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ +#define DMAC_PRICTRL0_QOS3_SHORTAGE_Val _Ul(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ +#define DMAC_PRICTRL0_QOS3_SENSITIVE_Val _Ul(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ +#define DMAC_PRICTRL0_QOS3_CRITICAL_Val _Ul(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ #define DMAC_PRICTRL0_QOS3_REGULAR (DMAC_PRICTRL0_QOS3_REGULAR_Val << DMAC_PRICTRL0_QOS3_Pos) #define DMAC_PRICTRL0_QOS3_SHORTAGE (DMAC_PRICTRL0_QOS3_SHORTAGE_Val << DMAC_PRICTRL0_QOS3_Pos) #define DMAC_PRICTRL0_QOS3_SENSITIVE (DMAC_PRICTRL0_QOS3_SENSITIVE_Val << DMAC_PRICTRL0_QOS3_Pos) #define DMAC_PRICTRL0_QOS3_CRITICAL (DMAC_PRICTRL0_QOS3_CRITICAL_Val << DMAC_PRICTRL0_QOS3_Pos) #define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN3 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) -#define DMAC_PRICTRL0_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_PRICTRL0) MASK Register */ +#define DMAC_PRICTRL0_RRLVLEN3 (_Ul(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) +#define DMAC_PRICTRL0_MASK _Ul(0xFFFFFFFF) /**< \brief (DMAC_PRICTRL0) MASK Register */ /* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -435,26 +435,26 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ -#define DMAC_INTPEND_RESETVALUE _U(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ +#define DMAC_INTPEND_RESETVALUE _Ul(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ #define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ -#define DMAC_INTPEND_ID_Msk (_U(0x1F) << DMAC_INTPEND_ID_Pos) +#define DMAC_INTPEND_ID_Msk (_Ul(0x1F) << DMAC_INTPEND_ID_Pos) #define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) #define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ -#define DMAC_INTPEND_TERR (_U(0x1) << DMAC_INTPEND_TERR_Pos) +#define DMAC_INTPEND_TERR (_Ul(0x1) << DMAC_INTPEND_TERR_Pos) #define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ -#define DMAC_INTPEND_TCMPL (_U(0x1) << DMAC_INTPEND_TCMPL_Pos) +#define DMAC_INTPEND_TCMPL (_Ul(0x1) << DMAC_INTPEND_TCMPL_Pos) #define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ -#define DMAC_INTPEND_SUSP (_U(0x1) << DMAC_INTPEND_SUSP_Pos) +#define DMAC_INTPEND_SUSP (_Ul(0x1) << DMAC_INTPEND_SUSP_Pos) #define DMAC_INTPEND_CRCERR_Pos 12 /**< \brief (DMAC_INTPEND) CRC Error */ -#define DMAC_INTPEND_CRCERR (_U(0x1) << DMAC_INTPEND_CRCERR_Pos) +#define DMAC_INTPEND_CRCERR (_Ul(0x1) << DMAC_INTPEND_CRCERR_Pos) #define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ -#define DMAC_INTPEND_FERR (_U(0x1) << DMAC_INTPEND_FERR_Pos) +#define DMAC_INTPEND_FERR (_Ul(0x1) << DMAC_INTPEND_FERR_Pos) #define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ -#define DMAC_INTPEND_BUSY (_U(0x1) << DMAC_INTPEND_BUSY_Pos) +#define DMAC_INTPEND_BUSY (_Ul(0x1) << DMAC_INTPEND_BUSY_Pos) #define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ -#define DMAC_INTPEND_PEND (_U(0x1) << DMAC_INTPEND_PEND_Pos) -#define DMAC_INTPEND_MASK _U(0xF71F) /**< \brief (DMAC_INTPEND) MASK Register */ +#define DMAC_INTPEND_PEND (_Ul(0x1) << DMAC_INTPEND_PEND_Pos) +#define DMAC_INTPEND_MASK _Ul(0xF71F) /**< \brief (DMAC_INTPEND) MASK Register */ /* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -501,7 +501,7 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ -#define DMAC_INTSTATUS_RESETVALUE _U(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ +#define DMAC_INTSTATUS_RESETVALUE _Ul(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ #define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ #define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos) @@ -568,9 +568,9 @@ typedef union { #define DMAC_INTSTATUS_CHINT31_Pos 31 /**< \brief (DMAC_INTSTATUS) Channel 31 Pending Interrupt */ #define DMAC_INTSTATUS_CHINT31 (1 << DMAC_INTSTATUS_CHINT31_Pos) #define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT_Msk (_U(0xFFFFFFFF) << DMAC_INTSTATUS_CHINT_Pos) +#define DMAC_INTSTATUS_CHINT_Msk (_Ul(0xFFFFFFFF) << DMAC_INTSTATUS_CHINT_Pos) #define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) -#define DMAC_INTSTATUS_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_INTSTATUS) MASK Register */ +#define DMAC_INTSTATUS_MASK _Ul(0xFFFFFFFF) /**< \brief (DMAC_INTSTATUS) MASK Register */ /* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -617,7 +617,7 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ -#define DMAC_BUSYCH_RESETVALUE _U(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ +#define DMAC_BUSYCH_RESETVALUE _Ul(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ #define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ #define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos) @@ -684,9 +684,9 @@ typedef union { #define DMAC_BUSYCH_BUSYCH31_Pos 31 /**< \brief (DMAC_BUSYCH) Busy Channel 31 */ #define DMAC_BUSYCH_BUSYCH31 (1 << DMAC_BUSYCH_BUSYCH31_Pos) #define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ -#define DMAC_BUSYCH_BUSYCH_Msk (_U(0xFFFFFFFF) << DMAC_BUSYCH_BUSYCH_Pos) +#define DMAC_BUSYCH_BUSYCH_Msk (_Ul(0xFFFFFFFF) << DMAC_BUSYCH_BUSYCH_Pos) #define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) -#define DMAC_BUSYCH_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_BUSYCH) MASK Register */ +#define DMAC_BUSYCH_MASK _Ul(0xFFFFFFFF) /**< \brief (DMAC_BUSYCH) MASK Register */ /* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -733,7 +733,7 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ -#define DMAC_PENDCH_RESETVALUE _U(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ +#define DMAC_PENDCH_RESETVALUE _Ul(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ #define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ #define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos) @@ -800,9 +800,9 @@ typedef union { #define DMAC_PENDCH_PENDCH31_Pos 31 /**< \brief (DMAC_PENDCH) Pending Channel 31 */ #define DMAC_PENDCH_PENDCH31 (1 << DMAC_PENDCH_PENDCH31_Pos) #define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ -#define DMAC_PENDCH_PENDCH_Msk (_U(0xFFFFFFFF) << DMAC_PENDCH_PENDCH_Pos) +#define DMAC_PENDCH_PENDCH_Msk (_Ul(0xFFFFFFFF) << DMAC_PENDCH_PENDCH_Pos) #define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) -#define DMAC_PENDCH_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_PENDCH) MASK Register */ +#define DMAC_PENDCH_MASK _Ul(0xFFFFFFFF) /**< \brief (DMAC_PENDCH) MASK Register */ /* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -827,7 +827,7 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ -#define DMAC_ACTIVE_RESETVALUE _U(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ +#define DMAC_ACTIVE_RESETVALUE _Ul(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ #define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ #define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos) @@ -838,17 +838,17 @@ typedef union { #define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ #define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos) #define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX_Msk (_U(0xF) << DMAC_ACTIVE_LVLEX_Pos) +#define DMAC_ACTIVE_LVLEX_Msk (_Ul(0xF) << DMAC_ACTIVE_LVLEX_Pos) #define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) #define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ -#define DMAC_ACTIVE_ID_Msk (_U(0x1F) << DMAC_ACTIVE_ID_Pos) +#define DMAC_ACTIVE_ID_Msk (_Ul(0x1F) << DMAC_ACTIVE_ID_Pos) #define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) #define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ -#define DMAC_ACTIVE_ABUSY (_U(0x1) << DMAC_ACTIVE_ABUSY_Pos) +#define DMAC_ACTIVE_ABUSY (_Ul(0x1) << DMAC_ACTIVE_ABUSY_Pos) #define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ -#define DMAC_ACTIVE_BTCNT_Msk (_U(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) +#define DMAC_ACTIVE_BTCNT_Msk (_Ul(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) #define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) -#define DMAC_ACTIVE_MASK _U(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */ +#define DMAC_ACTIVE_MASK _Ul(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */ /* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -861,12 +861,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ -#define DMAC_BASEADDR_RESETVALUE _U(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ +#define DMAC_BASEADDR_RESETVALUE _Ul(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ #define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ -#define DMAC_BASEADDR_BASEADDR_Msk (_U(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) +#define DMAC_BASEADDR_BASEADDR_Msk (_Ul(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) #define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) -#define DMAC_BASEADDR_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */ +#define DMAC_BASEADDR_MASK _Ul(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */ /* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -879,12 +879,12 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ -#define DMAC_WRBADDR_RESETVALUE _U(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ +#define DMAC_WRBADDR_RESETVALUE _Ul(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ #define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ -#define DMAC_WRBADDR_WRBADDR_Msk (_U(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) +#define DMAC_WRBADDR_WRBADDR_Msk (_Ul(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) #define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) -#define DMAC_WRBADDR_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */ +#define DMAC_WRBADDR_MASK _Ul(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */ /* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 32) CHANNEL Channel n Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -908,47 +908,47 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel n Control A */ -#define DMAC_CHCTRLA_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CHCTRLA reset_value) Channel n Control A */ +#define DMAC_CHCTRLA_RESETVALUE _Ul(0x00000000) /**< \brief (DMAC_CHCTRLA reset_value) Channel n Control A */ #define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ -#define DMAC_CHCTRLA_SWRST (_U(0x1) << DMAC_CHCTRLA_SWRST_Pos) +#define DMAC_CHCTRLA_SWRST (_Ul(0x1) << DMAC_CHCTRLA_SWRST_Pos) #define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ -#define DMAC_CHCTRLA_ENABLE (_U(0x1) << DMAC_CHCTRLA_ENABLE_Pos) +#define DMAC_CHCTRLA_ENABLE (_Ul(0x1) << DMAC_CHCTRLA_ENABLE_Pos) #define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel Run in Standby */ -#define DMAC_CHCTRLA_RUNSTDBY (_U(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos) +#define DMAC_CHCTRLA_RUNSTDBY (_Ul(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos) #define DMAC_CHCTRLA_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLA) Trigger Source */ -#define DMAC_CHCTRLA_TRIGSRC_Msk (_U(0x7F) << DMAC_CHCTRLA_TRIGSRC_Pos) +#define DMAC_CHCTRLA_TRIGSRC_Msk (_Ul(0x7F) << DMAC_CHCTRLA_TRIGSRC_Pos) #define DMAC_CHCTRLA_TRIGSRC(value) (DMAC_CHCTRLA_TRIGSRC_Msk & ((value) << DMAC_CHCTRLA_TRIGSRC_Pos)) -#define DMAC_CHCTRLA_TRIGSRC_DISABLE_Val _U(0x0) /**< \brief (DMAC_CHCTRLA) Only software/event triggers */ +#define DMAC_CHCTRLA_TRIGSRC_DISABLE_Val _Ul(0x0) /**< \brief (DMAC_CHCTRLA) Only software/event triggers */ #define DMAC_CHCTRLA_TRIGSRC_DISABLE (DMAC_CHCTRLA_TRIGSRC_DISABLE_Val << DMAC_CHCTRLA_TRIGSRC_Pos) #define DMAC_CHCTRLA_TRIGACT_Pos 20 /**< \brief (DMAC_CHCTRLA) Trigger Action */ -#define DMAC_CHCTRLA_TRIGACT_Msk (_U(0x3) << DMAC_CHCTRLA_TRIGACT_Pos) +#define DMAC_CHCTRLA_TRIGACT_Msk (_Ul(0x3) << DMAC_CHCTRLA_TRIGACT_Pos) #define DMAC_CHCTRLA_TRIGACT(value) (DMAC_CHCTRLA_TRIGACT_Msk & ((value) << DMAC_CHCTRLA_TRIGACT_Pos)) -#define DMAC_CHCTRLA_TRIGACT_BLOCK_Val _U(0x0) /**< \brief (DMAC_CHCTRLA) One trigger required for each block transfer */ -#define DMAC_CHCTRLA_TRIGACT_BURST_Val _U(0x2) /**< \brief (DMAC_CHCTRLA) One trigger required for each burst transfer */ -#define DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val _U(0x3) /**< \brief (DMAC_CHCTRLA) One trigger required for each transaction */ +#define DMAC_CHCTRLA_TRIGACT_BLOCK_Val _Ul(0x0) /**< \brief (DMAC_CHCTRLA) One trigger required for each block transfer */ +#define DMAC_CHCTRLA_TRIGACT_BURST_Val _Ul(0x2) /**< \brief (DMAC_CHCTRLA) One trigger required for each burst transfer */ +#define DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val _Ul(0x3) /**< \brief (DMAC_CHCTRLA) One trigger required for each transaction */ #define DMAC_CHCTRLA_TRIGACT_BLOCK (DMAC_CHCTRLA_TRIGACT_BLOCK_Val << DMAC_CHCTRLA_TRIGACT_Pos) #define DMAC_CHCTRLA_TRIGACT_BURST (DMAC_CHCTRLA_TRIGACT_BURST_Val << DMAC_CHCTRLA_TRIGACT_Pos) #define DMAC_CHCTRLA_TRIGACT_TRANSACTION (DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLA_TRIGACT_Pos) #define DMAC_CHCTRLA_BURSTLEN_Pos 24 /**< \brief (DMAC_CHCTRLA) Burst Length */ -#define DMAC_CHCTRLA_BURSTLEN_Msk (_U(0xF) << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_Msk (_Ul(0xF) << DMAC_CHCTRLA_BURSTLEN_Pos) #define DMAC_CHCTRLA_BURSTLEN(value) (DMAC_CHCTRLA_BURSTLEN_Msk & ((value) << DMAC_CHCTRLA_BURSTLEN_Pos)) -#define DMAC_CHCTRLA_BURSTLEN_SINGLE_Val _U(0x0) /**< \brief (DMAC_CHCTRLA) Single-beat burst length */ -#define DMAC_CHCTRLA_BURSTLEN_2BEAT_Val _U(0x1) /**< \brief (DMAC_CHCTRLA) 2-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_3BEAT_Val _U(0x2) /**< \brief (DMAC_CHCTRLA) 3-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_4BEAT_Val _U(0x3) /**< \brief (DMAC_CHCTRLA) 4-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_5BEAT_Val _U(0x4) /**< \brief (DMAC_CHCTRLA) 5-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_6BEAT_Val _U(0x5) /**< \brief (DMAC_CHCTRLA) 6-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_7BEAT_Val _U(0x6) /**< \brief (DMAC_CHCTRLA) 7-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_8BEAT_Val _U(0x7) /**< \brief (DMAC_CHCTRLA) 8-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_9BEAT_Val _U(0x8) /**< \brief (DMAC_CHCTRLA) 9-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_10BEAT_Val _U(0x9) /**< \brief (DMAC_CHCTRLA) 10-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_11BEAT_Val _U(0xA) /**< \brief (DMAC_CHCTRLA) 11-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_12BEAT_Val _U(0xB) /**< \brief (DMAC_CHCTRLA) 12-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_13BEAT_Val _U(0xC) /**< \brief (DMAC_CHCTRLA) 13-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_14BEAT_Val _U(0xD) /**< \brief (DMAC_CHCTRLA) 14-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_15BEAT_Val _U(0xE) /**< \brief (DMAC_CHCTRLA) 15-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_16BEAT_Val _U(0xF) /**< \brief (DMAC_CHCTRLA) 16-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_SINGLE_Val _Ul(0x0) /**< \brief (DMAC_CHCTRLA) Single-beat burst length */ +#define DMAC_CHCTRLA_BURSTLEN_2BEAT_Val _Ul(0x1) /**< \brief (DMAC_CHCTRLA) 2-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_3BEAT_Val _Ul(0x2) /**< \brief (DMAC_CHCTRLA) 3-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_4BEAT_Val _Ul(0x3) /**< \brief (DMAC_CHCTRLA) 4-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_5BEAT_Val _Ul(0x4) /**< \brief (DMAC_CHCTRLA) 5-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_6BEAT_Val _Ul(0x5) /**< \brief (DMAC_CHCTRLA) 6-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_7BEAT_Val _Ul(0x6) /**< \brief (DMAC_CHCTRLA) 7-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_8BEAT_Val _Ul(0x7) /**< \brief (DMAC_CHCTRLA) 8-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_9BEAT_Val _Ul(0x8) /**< \brief (DMAC_CHCTRLA) 9-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_10BEAT_Val _Ul(0x9) /**< \brief (DMAC_CHCTRLA) 10-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_11BEAT_Val _Ul(0xA) /**< \brief (DMAC_CHCTRLA) 11-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_12BEAT_Val _Ul(0xB) /**< \brief (DMAC_CHCTRLA) 12-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_13BEAT_Val _Ul(0xC) /**< \brief (DMAC_CHCTRLA) 13-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_14BEAT_Val _Ul(0xD) /**< \brief (DMAC_CHCTRLA) 14-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_15BEAT_Val _Ul(0xE) /**< \brief (DMAC_CHCTRLA) 15-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_16BEAT_Val _Ul(0xF) /**< \brief (DMAC_CHCTRLA) 16-beats burst length */ #define DMAC_CHCTRLA_BURSTLEN_SINGLE (DMAC_CHCTRLA_BURSTLEN_SINGLE_Val << DMAC_CHCTRLA_BURSTLEN_Pos) #define DMAC_CHCTRLA_BURSTLEN_2BEAT (DMAC_CHCTRLA_BURSTLEN_2BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) #define DMAC_CHCTRLA_BURSTLEN_3BEAT (DMAC_CHCTRLA_BURSTLEN_3BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) @@ -966,17 +966,17 @@ typedef union { #define DMAC_CHCTRLA_BURSTLEN_15BEAT (DMAC_CHCTRLA_BURSTLEN_15BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) #define DMAC_CHCTRLA_BURSTLEN_16BEAT (DMAC_CHCTRLA_BURSTLEN_16BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) #define DMAC_CHCTRLA_THRESHOLD_Pos 28 /**< \brief (DMAC_CHCTRLA) FIFO Threshold */ -#define DMAC_CHCTRLA_THRESHOLD_Msk (_U(0x3) << DMAC_CHCTRLA_THRESHOLD_Pos) +#define DMAC_CHCTRLA_THRESHOLD_Msk (_Ul(0x3) << DMAC_CHCTRLA_THRESHOLD_Pos) #define DMAC_CHCTRLA_THRESHOLD(value) (DMAC_CHCTRLA_THRESHOLD_Msk & ((value) << DMAC_CHCTRLA_THRESHOLD_Pos)) -#define DMAC_CHCTRLA_THRESHOLD_1BEAT_Val _U(0x0) /**< \brief (DMAC_CHCTRLA) Destination write starts after each beat source address read */ -#define DMAC_CHCTRLA_THRESHOLD_2BEATS_Val _U(0x1) /**< \brief (DMAC_CHCTRLA) Destination write starts after 2-beats source address read */ -#define DMAC_CHCTRLA_THRESHOLD_4BEATS_Val _U(0x2) /**< \brief (DMAC_CHCTRLA) Destination write starts after 4-beats source address read */ -#define DMAC_CHCTRLA_THRESHOLD_8BEATS_Val _U(0x3) /**< \brief (DMAC_CHCTRLA) Destination write starts after 8-beats source address read */ +#define DMAC_CHCTRLA_THRESHOLD_1BEAT_Val _Ul(0x0) /**< \brief (DMAC_CHCTRLA) Destination write starts after each beat source address read */ +#define DMAC_CHCTRLA_THRESHOLD_2BEATS_Val _Ul(0x1) /**< \brief (DMAC_CHCTRLA) Destination write starts after 2-beats source address read */ +#define DMAC_CHCTRLA_THRESHOLD_4BEATS_Val _Ul(0x2) /**< \brief (DMAC_CHCTRLA) Destination write starts after 4-beats source address read */ +#define DMAC_CHCTRLA_THRESHOLD_8BEATS_Val _Ul(0x3) /**< \brief (DMAC_CHCTRLA) Destination write starts after 8-beats source address read */ #define DMAC_CHCTRLA_THRESHOLD_1BEAT (DMAC_CHCTRLA_THRESHOLD_1BEAT_Val << DMAC_CHCTRLA_THRESHOLD_Pos) #define DMAC_CHCTRLA_THRESHOLD_2BEATS (DMAC_CHCTRLA_THRESHOLD_2BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) #define DMAC_CHCTRLA_THRESHOLD_4BEATS (DMAC_CHCTRLA_THRESHOLD_4BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) #define DMAC_CHCTRLA_THRESHOLD_8BEATS (DMAC_CHCTRLA_THRESHOLD_8BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_MASK _U(0x3F307F43) /**< \brief (DMAC_CHCTRLA) MASK Register */ +#define DMAC_CHCTRLA_MASK _Ul(0x3F307F43) /**< \brief (DMAC_CHCTRLA) MASK Register */ /* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 8) CHANNEL Channel n Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -990,18 +990,18 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel n Control B */ -#define DMAC_CHCTRLB_RESETVALUE _U(0x00) /**< \brief (DMAC_CHCTRLB reset_value) Channel n Control B */ +#define DMAC_CHCTRLB_RESETVALUE _Ul(0x00) /**< \brief (DMAC_CHCTRLB reset_value) Channel n Control B */ #define DMAC_CHCTRLB_CMD_Pos 0 /**< \brief (DMAC_CHCTRLB) Software Command */ -#define DMAC_CHCTRLB_CMD_Msk (_U(0x3) << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_Msk (_Ul(0x3) << DMAC_CHCTRLB_CMD_Pos) #define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) -#define DMAC_CHCTRLB_CMD_NOACT_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_CMD_RESUME_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ +#define DMAC_CHCTRLB_CMD_NOACT_Val _Ul(0x0) /**< \brief (DMAC_CHCTRLB) No action */ +#define DMAC_CHCTRLB_CMD_SUSPEND_Val _Ul(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ +#define DMAC_CHCTRLB_CMD_RESUME_Val _Ul(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ #define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) #define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) #define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_MASK _U(0x03) /**< \brief (DMAC_CHCTRLB) MASK Register */ +#define DMAC_CHCTRLB_MASK _Ul(0x03) /**< \brief (DMAC_CHCTRLB) MASK Register */ /* -------- DMAC_CHPRILVL : (DMAC Offset: 0x45) (R/W 8) CHANNEL Channel n Priority Level -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -1015,19 +1015,19 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_CHPRILVL_OFFSET 0x45 /**< \brief (DMAC_CHPRILVL offset) Channel n Priority Level */ -#define DMAC_CHPRILVL_RESETVALUE _U(0x00) /**< \brief (DMAC_CHPRILVL reset_value) Channel n Priority Level */ +#define DMAC_CHPRILVL_RESETVALUE _Ul(0x00) /**< \brief (DMAC_CHPRILVL reset_value) Channel n Priority Level */ #define DMAC_CHPRILVL_PRILVL_Pos 0 /**< \brief (DMAC_CHPRILVL) Channel Priority Level */ -#define DMAC_CHPRILVL_PRILVL_Msk (_U(0x3) << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_Msk (_Ul(0x3) << DMAC_CHPRILVL_PRILVL_Pos) #define DMAC_CHPRILVL_PRILVL(value) (DMAC_CHPRILVL_PRILVL_Msk & ((value) << DMAC_CHPRILVL_PRILVL_Pos)) -#define DMAC_CHPRILVL_PRILVL_LVL0_Val _U(0x0) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 0 (Lowest Level) */ -#define DMAC_CHPRILVL_PRILVL_LVL1_Val _U(0x1) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 1 */ -#define DMAC_CHPRILVL_PRILVL_LVL2_Val _U(0x2) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 2 */ -#define DMAC_CHPRILVL_PRILVL_LVL3_Val _U(0x3) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 3 */ -#define DMAC_CHPRILVL_PRILVL_LVL4_Val _U(0x4) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 4 */ -#define DMAC_CHPRILVL_PRILVL_LVL5_Val _U(0x5) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 5 */ -#define DMAC_CHPRILVL_PRILVL_LVL6_Val _U(0x6) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 6 */ -#define DMAC_CHPRILVL_PRILVL_LVL7_Val _U(0x7) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 7 (Highest Level) */ +#define DMAC_CHPRILVL_PRILVL_LVL0_Val _Ul(0x0) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 0 (Lowest Level) */ +#define DMAC_CHPRILVL_PRILVL_LVL1_Val _Ul(0x1) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 1 */ +#define DMAC_CHPRILVL_PRILVL_LVL2_Val _Ul(0x2) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 2 */ +#define DMAC_CHPRILVL_PRILVL_LVL3_Val _Ul(0x3) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 3 */ +#define DMAC_CHPRILVL_PRILVL_LVL4_Val _Ul(0x4) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 4 */ +#define DMAC_CHPRILVL_PRILVL_LVL5_Val _Ul(0x5) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 5 */ +#define DMAC_CHPRILVL_PRILVL_LVL6_Val _Ul(0x6) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 6 */ +#define DMAC_CHPRILVL_PRILVL_LVL7_Val _Ul(0x7) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 7 (Highest Level) */ #define DMAC_CHPRILVL_PRILVL_LVL0 (DMAC_CHPRILVL_PRILVL_LVL0_Val << DMAC_CHPRILVL_PRILVL_Pos) #define DMAC_CHPRILVL_PRILVL_LVL1 (DMAC_CHPRILVL_PRILVL_LVL1_Val << DMAC_CHPRILVL_PRILVL_Pos) #define DMAC_CHPRILVL_PRILVL_LVL2 (DMAC_CHPRILVL_PRILVL_LVL2_Val << DMAC_CHPRILVL_PRILVL_Pos) @@ -1036,7 +1036,7 @@ typedef union { #define DMAC_CHPRILVL_PRILVL_LVL5 (DMAC_CHPRILVL_PRILVL_LVL5_Val << DMAC_CHPRILVL_PRILVL_Pos) #define DMAC_CHPRILVL_PRILVL_LVL6 (DMAC_CHPRILVL_PRILVL_LVL6_Val << DMAC_CHPRILVL_PRILVL_Pos) #define DMAC_CHPRILVL_PRILVL_LVL7 (DMAC_CHPRILVL_PRILVL_LVL7_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_MASK _U(0x03) /**< \brief (DMAC_CHPRILVL) MASK Register */ +#define DMAC_CHPRILVL_MASK _Ul(0x03) /**< \brief (DMAC_CHPRILVL) MASK Register */ /* -------- DMAC_CHEVCTRL : (DMAC Offset: 0x46) (R/W 8) CHANNEL Channel n Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -1053,19 +1053,19 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_CHEVCTRL_OFFSET 0x46 /**< \brief (DMAC_CHEVCTRL offset) Channel n Event Control */ -#define DMAC_CHEVCTRL_RESETVALUE _U(0x00) /**< \brief (DMAC_CHEVCTRL reset_value) Channel n Event Control */ +#define DMAC_CHEVCTRL_RESETVALUE _Ul(0x00) /**< \brief (DMAC_CHEVCTRL reset_value) Channel n Event Control */ #define DMAC_CHEVCTRL_EVACT_Pos 0 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Action */ -#define DMAC_CHEVCTRL_EVACT_Msk (_U(0x7) << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_Msk (_Ul(0x7) << DMAC_CHEVCTRL_EVACT_Pos) #define DMAC_CHEVCTRL_EVACT(value) (DMAC_CHEVCTRL_EVACT_Msk & ((value) << DMAC_CHEVCTRL_EVACT_Pos)) -#define DMAC_CHEVCTRL_EVACT_NOACT_Val _U(0x0) /**< \brief (DMAC_CHEVCTRL) No action */ -#define DMAC_CHEVCTRL_EVACT_TRIG_Val _U(0x1) /**< \brief (DMAC_CHEVCTRL) Transfer and periodic transfer trigger */ -#define DMAC_CHEVCTRL_EVACT_CTRIG_Val _U(0x2) /**< \brief (DMAC_CHEVCTRL) Conditional transfer trigger */ -#define DMAC_CHEVCTRL_EVACT_CBLOCK_Val _U(0x3) /**< \brief (DMAC_CHEVCTRL) Conditional block transfer */ -#define DMAC_CHEVCTRL_EVACT_SUSPEND_Val _U(0x4) /**< \brief (DMAC_CHEVCTRL) Channel suspend operation */ -#define DMAC_CHEVCTRL_EVACT_RESUME_Val _U(0x5) /**< \brief (DMAC_CHEVCTRL) Channel resume operation */ -#define DMAC_CHEVCTRL_EVACT_SSKIP_Val _U(0x6) /**< \brief (DMAC_CHEVCTRL) Skip next block suspend action */ -#define DMAC_CHEVCTRL_EVACT_INCPRI_Val _U(0x7) /**< \brief (DMAC_CHEVCTRL) Increase priority */ +#define DMAC_CHEVCTRL_EVACT_NOACT_Val _Ul(0x0) /**< \brief (DMAC_CHEVCTRL) No action */ +#define DMAC_CHEVCTRL_EVACT_TRIG_Val _Ul(0x1) /**< \brief (DMAC_CHEVCTRL) Transfer and periodic transfer trigger */ +#define DMAC_CHEVCTRL_EVACT_CTRIG_Val _Ul(0x2) /**< \brief (DMAC_CHEVCTRL) Conditional transfer trigger */ +#define DMAC_CHEVCTRL_EVACT_CBLOCK_Val _Ul(0x3) /**< \brief (DMAC_CHEVCTRL) Conditional block transfer */ +#define DMAC_CHEVCTRL_EVACT_SUSPEND_Val _Ul(0x4) /**< \brief (DMAC_CHEVCTRL) Channel suspend operation */ +#define DMAC_CHEVCTRL_EVACT_RESUME_Val _Ul(0x5) /**< \brief (DMAC_CHEVCTRL) Channel resume operation */ +#define DMAC_CHEVCTRL_EVACT_SSKIP_Val _Ul(0x6) /**< \brief (DMAC_CHEVCTRL) Skip next block suspend action */ +#define DMAC_CHEVCTRL_EVACT_INCPRI_Val _Ul(0x7) /**< \brief (DMAC_CHEVCTRL) Increase priority */ #define DMAC_CHEVCTRL_EVACT_NOACT (DMAC_CHEVCTRL_EVACT_NOACT_Val << DMAC_CHEVCTRL_EVACT_Pos) #define DMAC_CHEVCTRL_EVACT_TRIG (DMAC_CHEVCTRL_EVACT_TRIG_Val << DMAC_CHEVCTRL_EVACT_Pos) #define DMAC_CHEVCTRL_EVACT_CTRIG (DMAC_CHEVCTRL_EVACT_CTRIG_Val << DMAC_CHEVCTRL_EVACT_Pos) @@ -1075,17 +1075,17 @@ typedef union { #define DMAC_CHEVCTRL_EVACT_SSKIP (DMAC_CHEVCTRL_EVACT_SSKIP_Val << DMAC_CHEVCTRL_EVACT_Pos) #define DMAC_CHEVCTRL_EVACT_INCPRI (DMAC_CHEVCTRL_EVACT_INCPRI_Val << DMAC_CHEVCTRL_EVACT_Pos) #define DMAC_CHEVCTRL_EVOMODE_Pos 4 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Mode */ -#define DMAC_CHEVCTRL_EVOMODE_Msk (_U(0x3) << DMAC_CHEVCTRL_EVOMODE_Pos) +#define DMAC_CHEVCTRL_EVOMODE_Msk (_Ul(0x3) << DMAC_CHEVCTRL_EVOMODE_Pos) #define DMAC_CHEVCTRL_EVOMODE(value) (DMAC_CHEVCTRL_EVOMODE_Msk & ((value) << DMAC_CHEVCTRL_EVOMODE_Pos)) -#define DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val _U(0x0) /**< \brief (DMAC_CHEVCTRL) Block event output selection. Refer to BTCTRL.EVOSEL for available selections. */ -#define DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val _U(0x1) /**< \brief (DMAC_CHEVCTRL) Ongoing trigger action */ +#define DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val _Ul(0x0) /**< \brief (DMAC_CHEVCTRL) Block event output selection. Refer to BTCTRL.EVOSEL for available selections. */ +#define DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val _Ul(0x1) /**< \brief (DMAC_CHEVCTRL) Ongoing trigger action */ #define DMAC_CHEVCTRL_EVOMODE_DEFAULT (DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val << DMAC_CHEVCTRL_EVOMODE_Pos) #define DMAC_CHEVCTRL_EVOMODE_TRIGACT (DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val << DMAC_CHEVCTRL_EVOMODE_Pos) #define DMAC_CHEVCTRL_EVIE_Pos 6 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Enable */ -#define DMAC_CHEVCTRL_EVIE (_U(0x1) << DMAC_CHEVCTRL_EVIE_Pos) +#define DMAC_CHEVCTRL_EVIE (_Ul(0x1) << DMAC_CHEVCTRL_EVIE_Pos) #define DMAC_CHEVCTRL_EVOE_Pos 7 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Enable */ -#define DMAC_CHEVCTRL_EVOE (_U(0x1) << DMAC_CHEVCTRL_EVOE_Pos) -#define DMAC_CHEVCTRL_MASK _U(0xF7) /**< \brief (DMAC_CHEVCTRL) MASK Register */ +#define DMAC_CHEVCTRL_EVOE (_Ul(0x1) << DMAC_CHEVCTRL_EVOE_Pos) +#define DMAC_CHEVCTRL_MASK _Ul(0xF7) /**< \brief (DMAC_CHEVCTRL) MASK Register */ /* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -1101,15 +1101,15 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel n Interrupt Enable Clear */ -#define DMAC_CHINTENCLR_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */ +#define DMAC_CHINTENCLR_RESETVALUE _Ul(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */ #define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENCLR_TERR (_U(0x1) << DMAC_CHINTENCLR_TERR_Pos) +#define DMAC_CHINTENCLR_TERR (_Ul(0x1) << DMAC_CHINTENCLR_TERR_Pos) #define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENCLR_TCMPL (_U(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) +#define DMAC_CHINTENCLR_TCMPL (_Ul(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) #define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENCLR_SUSP (_U(0x1) << DMAC_CHINTENCLR_SUSP_Pos) -#define DMAC_CHINTENCLR_MASK _U(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */ +#define DMAC_CHINTENCLR_SUSP (_Ul(0x1) << DMAC_CHINTENCLR_SUSP_Pos) +#define DMAC_CHINTENCLR_MASK _Ul(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */ /* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -1125,15 +1125,15 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel n Interrupt Enable Set */ -#define DMAC_CHINTENSET_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel n Interrupt Enable Set */ +#define DMAC_CHINTENSET_RESETVALUE _Ul(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel n Interrupt Enable Set */ #define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENSET_TERR (_U(0x1) << DMAC_CHINTENSET_TERR_Pos) +#define DMAC_CHINTENSET_TERR (_Ul(0x1) << DMAC_CHINTENSET_TERR_Pos) #define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENSET_TCMPL (_U(0x1) << DMAC_CHINTENSET_TCMPL_Pos) +#define DMAC_CHINTENSET_TCMPL (_Ul(0x1) << DMAC_CHINTENSET_TCMPL_Pos) #define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENSET_SUSP (_U(0x1) << DMAC_CHINTENSET_SUSP_Pos) -#define DMAC_CHINTENSET_MASK _U(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */ +#define DMAC_CHINTENSET_SUSP (_Ul(0x1) << DMAC_CHINTENSET_SUSP_Pos) +#define DMAC_CHINTENSET_MASK _Ul(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */ /* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -1149,15 +1149,15 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */ -#define DMAC_CHINTFLAG_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */ +#define DMAC_CHINTFLAG_RESETVALUE _Ul(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */ #define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ -#define DMAC_CHINTFLAG_TERR (_U(0x1) << DMAC_CHINTFLAG_TERR_Pos) +#define DMAC_CHINTFLAG_TERR (_Ul(0x1) << DMAC_CHINTFLAG_TERR_Pos) #define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ -#define DMAC_CHINTFLAG_TCMPL (_U(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) +#define DMAC_CHINTFLAG_TCMPL (_Ul(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) #define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ -#define DMAC_CHINTFLAG_SUSP (_U(0x1) << DMAC_CHINTFLAG_SUSP_Pos) -#define DMAC_CHINTFLAG_MASK _U(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */ +#define DMAC_CHINTFLAG_SUSP (_Ul(0x1) << DMAC_CHINTFLAG_SUSP_Pos) +#define DMAC_CHINTFLAG_MASK _Ul(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */ /* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/W 8) CHANNEL Channel n Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -1174,17 +1174,17 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel n Status */ -#define DMAC_CHSTATUS_RESETVALUE _U(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel n Status */ +#define DMAC_CHSTATUS_RESETVALUE _Ul(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel n Status */ #define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ -#define DMAC_CHSTATUS_PEND (_U(0x1) << DMAC_CHSTATUS_PEND_Pos) +#define DMAC_CHSTATUS_PEND (_Ul(0x1) << DMAC_CHSTATUS_PEND_Pos) #define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ -#define DMAC_CHSTATUS_BUSY (_U(0x1) << DMAC_CHSTATUS_BUSY_Pos) +#define DMAC_CHSTATUS_BUSY (_Ul(0x1) << DMAC_CHSTATUS_BUSY_Pos) #define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ -#define DMAC_CHSTATUS_FERR (_U(0x1) << DMAC_CHSTATUS_FERR_Pos) +#define DMAC_CHSTATUS_FERR (_Ul(0x1) << DMAC_CHSTATUS_FERR_Pos) #define DMAC_CHSTATUS_CRCERR_Pos 3 /**< \brief (DMAC_CHSTATUS) Channel CRC Error */ -#define DMAC_CHSTATUS_CRCERR (_U(0x1) << DMAC_CHSTATUS_CRCERR_Pos) -#define DMAC_CHSTATUS_MASK _U(0x0F) /**< \brief (DMAC_CHSTATUS) MASK Register */ +#define DMAC_CHSTATUS_CRCERR (_Ul(0x1) << DMAC_CHSTATUS_CRCERR_Pos) +#define DMAC_CHSTATUS_MASK _Ul(0x0F) /**< \brief (DMAC_CHSTATUS) MASK Register */ /* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -1205,60 +1205,60 @@ typedef union { #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ -#define DMAC_BTCTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ +#define DMAC_BTCTRL_RESETVALUE _Ul(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ #define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ -#define DMAC_BTCTRL_VALID (_U(0x1) << DMAC_BTCTRL_VALID_Pos) +#define DMAC_BTCTRL_VALID (_Ul(0x1) << DMAC_BTCTRL_VALID_Pos) #define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Block Event Output Selection */ -#define DMAC_BTCTRL_EVOSEL_Msk (_U(0x3) << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_Msk (_Ul(0x3) << DMAC_BTCTRL_EVOSEL_Pos) #define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) -#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */ -#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Block event strobe */ -#define DMAC_BTCTRL_EVOSEL_BURST_Val _U(0x3) /**< \brief (DMAC_BTCTRL) Burst event strobe */ +#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _Ul(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */ +#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _Ul(0x1) /**< \brief (DMAC_BTCTRL) Block event strobe */ +#define DMAC_BTCTRL_EVOSEL_BURST_Val _Ul(0x3) /**< \brief (DMAC_BTCTRL) Burst event strobe */ #define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) #define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) #define DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos) #define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ -#define DMAC_BTCTRL_BLOCKACT_Msk (_U(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_Msk (_Ul(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) #define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) -#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ -#define DMAC_BTCTRL_BLOCKACT_INT_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ -#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _Ul(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ +#define DMAC_BTCTRL_BLOCKACT_INT_Val _Ul(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _Ul(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ +#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _Ul(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ #define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) #define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) #define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) #define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) #define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ -#define DMAC_BTCTRL_BEATSIZE_Msk (_U(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_Msk (_Ul(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) #define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) -#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _Ul(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _Ul(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_WORD_Val _Ul(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ #define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) #define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) #define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) #define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ -#define DMAC_BTCTRL_SRCINC (_U(0x1) << DMAC_BTCTRL_SRCINC_Pos) +#define DMAC_BTCTRL_SRCINC (_Ul(0x1) << DMAC_BTCTRL_SRCINC_Pos) #define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ -#define DMAC_BTCTRL_DSTINC (_U(0x1) << DMAC_BTCTRL_DSTINC_Pos) +#define DMAC_BTCTRL_DSTINC (_Ul(0x1) << DMAC_BTCTRL_DSTINC_Pos) #define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ -#define DMAC_BTCTRL_STEPSEL (_U(0x1) << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_DST_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ -#define DMAC_BTCTRL_STEPSEL_SRC_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ +#define DMAC_BTCTRL_STEPSEL (_Ul(0x1) << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_DST_Val _Ul(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ +#define DMAC_BTCTRL_STEPSEL_SRC_Val _Ul(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ #define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) #define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) #define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ -#define DMAC_BTCTRL_STEPSIZE_Msk (_U(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) +#define DMAC_BTCTRL_STEPSIZE_Msk (_Ul(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) #define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) -#define DMAC_BTCTRL_STEPSIZE_X1_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1< - #if defined(__SAMD51G18A__) || defined(__ATSAMD51G18A__) #include "samd51g18a.h" #elif defined(__SAMD51G19A__) || defined(__ATSAMD51G19A__) diff --git a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51g18a.h b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51g18a.h index df7e476..0059567 100644 --- a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51g18a.h +++ b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51g18a.h @@ -61,6 +61,17 @@ typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volati typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _Ul(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _Sl(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _Ul(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _Sl(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif #endif /* ************************************************************************** */ diff --git a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51g19a.h b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51g19a.h index a5e6337..ac2b892 100644 --- a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51g19a.h +++ b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51g19a.h @@ -61,6 +61,17 @@ typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volati typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _Ul(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _Sl(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _Ul(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _Sl(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif #endif /* ************************************************************************** */ diff --git a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51j18a.h b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51j18a.h index 5c023a5..4c814fa 100644 --- a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51j18a.h +++ b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51j18a.h @@ -61,6 +61,17 @@ typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volati typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _Ul(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _Sl(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _Ul(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _Sl(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif #endif /* ************************************************************************** */ diff --git a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51j19a.h b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51j19a.h index 60c8172..249fb49 100644 --- a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51j19a.h +++ b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51j19a.h @@ -61,6 +61,17 @@ typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volati typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _Ul(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _Sl(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _Ul(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _Sl(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif #endif /* ************************************************************************** */ diff --git a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51j20a.h b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51j20a.h index cd45dcf..62a3fe4 100644 --- a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51j20a.h +++ b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51j20a.h @@ -61,6 +61,17 @@ typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volati typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _Ul(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _Sl(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _Ul(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _Sl(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif #endif /* ************************************************************************** */ diff --git a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51n19a.h b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51n19a.h index 8faa9e5..bb5011d 100644 --- a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51n19a.h +++ b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51n19a.h @@ -61,6 +61,17 @@ typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volati typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _Ul(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _Sl(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _Ul(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _Sl(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif #endif /* ************************************************************************** */ diff --git a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51n20a.h b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51n20a.h index 243ff08..6e1e8e5 100644 --- a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51n20a.h +++ b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51n20a.h @@ -61,6 +61,17 @@ typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volati typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _Ul(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _Sl(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _Ul(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _Sl(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif #endif /* ************************************************************************** */ diff --git a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51p19a.h b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51p19a.h index 5d2275d..fd73d47 100644 --- a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51p19a.h +++ b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51p19a.h @@ -61,6 +61,17 @@ typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volati typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _Ul(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _Sl(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _Ul(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _Sl(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif #endif /* ************************************************************************** */ diff --git a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51p20a.h b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51p20a.h index 343157e..b8bf20d 100644 --- a/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51p20a.h +++ b/CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/samd51p20a.h @@ -61,6 +61,17 @@ typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volati typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _Ul(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _Sl(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _Ul(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _Sl(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif #endif /* ************************************************************************** */