Lacking post-index operand for AArch64 ld1r instruction on "next" branch

[jj16791]

The framework doesn’t seem to recognise the 3rd post-index operand of the ld1r post-index instruction, an example/comparison would be against the correctly disassembled ldrb instruction with post-indexing:

ldrb w1, [x0], #1:
op_count: 3
                operands[0].type: REG = w1
                operands[0].access: WRITE
                operands[1].type: MEM
                        operands[1].mem.base: REG = x0
                operands[1].access: READ | WRITE
                operands[2].type: IMM = 0x1
                operands[2].access: READ
        Write-back: True
        Registers read: x0
        Registers modified: w1 x0

ld1r {v0.4s}, [x0], #4:
op_count: 2
                operands[0].type: REG = v0
                operands[0].access: READ | WRITE
                        Vector Arrangement Specifier: 0x9
                operands[1].type: MEM
                        operands[1].mem.base: REG = x0
                operands[1].access: READ | WRITE
        Write-back: True
        Registers read: v0 x0
        Registers modified: v0 x0

This data was printed after using the cs_disasm_iter function. It can be seen that there exists no operands[2] for the post-index immediate of #4.

[jiegec]

The access attribute of the first operand of ld1r is wrong as well:

op_count: 2
                operands[0].type: REG = v0
                operands[0].access: READ | WRITE

It should be:

op_count: 2
                operands[0].type: REG = v0
                operands[0].access: WRITE

The problem exists in master and next branches: cstool -d arm64 0x21c8df4d