Description
Description
Access flags of registers and memory accesses are incorrect for several AArch64 instructions.
After disassembling some sample functions that were compiled for AArch64, I have found that several instructions have incorrect access flags (or am I missing something?). I suspect that the examples given below are not an exhaustive list of instruction types that have incorrect access flags.
I am not sure if the access flags in AArch64MappingInsnOp.inc are automatically generated from an external resource. If it is, it might make sense to raise an issue on the issue tracker of the external project.
To reproduce
On commit 0de88ed (next):
$ cstool -d arm64 a0019ed2
0 a0 01 9e d2 mov x0, #0xf00d
ID: 488 (mov)
op_count: 2
operands[0].type: REG = x0
operands[0].access: READ | WRITE
operands[1].type: IMM = 0xf00d
Registers read: x0
Registers modified: x0
$ cstool -d arm64 200000f9
0 20 00 00 f9 str x0, [x1]
ID: 762 (str)
op_count: 2
operands[0].type: REG = x0
operands[0].access: READ
operands[1].type: MEM
operands[1].mem.base: REG = x1
operands[1].access: READ | WRITE
Registers read: x0 x1
$ cstool -d arm64 3000df4c
0 30 00 df 4c ld4 {v16.16b, v17.16b, v18.16b, v19.16b}, [x1], #64
ID: 311 (ld4)
op_count: 5
operands[0].type: REG = v16
operands[0].access: READ | WRITE
Vector Arrangement Specifier: 0x1
operands[1].type: REG = v17
operands[1].access: READ | WRITE
Vector Arrangement Specifier: 0x1
operands[2].type: REG = v18
operands[2].access: READ
Vector Arrangement Specifier: 0x1
operands[3].type: REG = v19
Vector Arrangement Specifier: 0x1
operands[4].type: MEM
operands[4].mem.base: REG = x1
Write-back: True
Registers read: v16 v17 v18 x1
Registers modified: v16 v17 x1
Groups: neon
On commit 5d32a95 (master):
Same results, except for the instruction ld4 {v16.16b, v17.16b, v18.16b, v19.16b}, [x1], #64, which has the same access flags but different vector arrangement specifier (0x2) and has an additional operand for the immediate 0x40.
Expected behavior
For mov x0, #0xf00d, the register x0 operand access flag should be WRITE.
For str x0, [x1], the memory operand access flag should be WRITE.
For ld4 {v16.16b, v17.16b, v18.16b, v19.16b}, [x1], #64, the memory operands of all vector registers should be WRITE. The access flag of the memory operand is missing, and should be READ.